Low Profile Edge Launch Clam Shell Connector System Marketing Briefs and Specifications Aug 29, 2009

Product Description The test and characterization engineer is faced with many difficult challenges interfacing test equipment to SOC devices. Signal Integrity has designed a family of high bandwidth connector and signal distribution systems to meet the challenges of limited board space for large banks of connectors and signal trace break out patterns that optimize the probing of SOC devices with highly scaled Serdes IO. One of the other challenges that the test/characterization engineer faces is how to address the port wide probing in system or off of a test board that is need to test functional word wide operations of the specific Serdes protocols. The clam shell connector system is designed with the intent of observing and debugging traffic and interconnects within a system or under mission mode test and debug suites, protocol issues device. Product Design Features The Clam Shell operates at bit rates to 5Gb/s targeting protocols such as PCI Express 2, FBDIMM and Hyper-transport 2. The connector is modular in design with two break out points. It is designed to mount on the top and bottom of an edge launch card. The top to bottom clearance requires less 0.802" total height with a typical 0.141" board thickness. Cables launch horizontally from the connector and can be positioned for either right angle or vertical probe boards. The cables used are low dielectric high flexible light cables to allow operation in the tight confines of a system or tester functional debug board. When trying to scale 32 cables, the flexibility and weight of the bundle is a critical component of the over all usability and total reliability of the interface.

Side View of Clam Shell Connectors This view shows the dimensions of the calm shell board. It is designed with back plane and system clearance for multiple board locations. The signal path from the cable to the board is short at approximately 0.192". This minimizes inductance and return loss.

Application Example Shown here is a card used to plug into a system back plane connector. Signals are routed through the switch to allow signals to loop back to the system or bus out through the Signal Integrity clam shell connector to a protocol analyzer test platform. Connector Signal Integrity S p e c ific a tio n s

TDR

N um b e r of C ha nn e ls Im p e d a n c e Lo ss Ta n g e n t @ 1 0 G hz B a n d w id th (-3d B ) R e tu rn Lo ss C on n e c to r C ro ssta lk Im p u lse R e sp o nse th ru 1 m

32 5 0 o h m s + /- 5 % -1.6 9 d B / ft 4G Hz ² -30 d B to 10 G H z < -1 10 d B a t 4 G H z 35 p s _ 1 2 3 p s

Board to Connector Interface TDR This measurement is made from the board side through the connector. This TDR plot shows the effects of the connector inductance and board to connector capacitance. The signal is a micro-strip trace to the connector pins. The total impedance variance through the connector is approximately 5 ohms over 150 ps. The effective bandwidth of the connection between the cable exceeds 8 GHz. The complete system also consists of a OEM cable bulk head. This allows the cables to be organized by system test functions and lets the user interface to a number of different terminations. In this application, the cable termination to the instrument is through standard SMA connectors.

Cable System Organization The importance of cable organization in a large scale high bandwidth test bench cannot be minimized. Accuracy, reliability, productivity, and efficiency of the process hinge on being able to quickly set up and tear down a rack to DUT fixture. The OEM bulkhead shown here is one example of good cable distribution design. Bringing a 32 cable coaxial bundle into a central point for distribution allows point to point cable connections close to the rack instrumentation, this eases cable swarming and allows for a transition to different terminations that the instruments or system may require

Cable Bulkhead TDR The cable bulkhead maintains an impedence between 54 and 51 ohms. It operates well past 5 GHz with low return loss making it an ideal component to use in 5 Gb/s test channels. The importance of low return loss rises as the complexity of device IOs increases.

Total System TDT : Measure Rise Time Bandwidth This plot illustrates the signal rise time through a clam shell interconnect through the cable bulkhead to the TDR unit receiver. The system input rise time is normalized to 35 ps. Using the traditional central limit theorem equation to solve for a Gaussian step response, yields a system rise time of 123ps = √ 35ps2+ Trise(system) ps2 or Trise(system) = 117ps Quick total BW estimate .336/117ps = 2.87 GHz From these calculations we can estimate that we would be able to properly measure and function with signal bit rates up to 6 Gb/s. This connector system can address PCI Express 2, FBDIMM 1, XAUI and Hyper Transport 2 bit rates as well as clock distribution channels up to 3 GHz.

System S Parameters Actual channel measurements show a 3 dB cutoff that is 4 GHz indicating we can push this system to higher speeds from the initial calculation, thus even getting good results for FBDIMM2 or Buffer on Board memory systems. Note the low return loss. This is a result of careful impedance control through the connector to board interface. A proprietary GND return design in the connectors and low loss dielectric material with well controlled impedance at each stage of the signal channel pays off in lower return loss, making this ideal for physical layer testing of FFE (feed forward equalization) and FIR (fast impulse response) serdes architectures.

Eye Pattern Performance A well controlled impedance and a low loss fast rise time cable system should result in a balanced open eye pattern to the DUT. With smooth roll off characteristics, it is also more straightforward to program and characterize the linearity of the de-emphasis functions that the test system transmitters or DUT receiver/transmitters use to compensate for channel loss. Lowering ISI and DCD help maintain stable Bit Error Rate measurements. Reducing cross talk in the cable connection housings by completely shielding all signals and signal return paths helps minimize total system jitter and bounded uncorrelated test effects. Eye pattern Performance at various Bit Rates Test Conditions PRBS 27-1 pattern Channel 4 scope trace - direct output of JBERT through 40 GHz cable system into 18 GHz plug in Channel 3 scope trace - JBERT through full able system and matched 40 GHz cable. Scope deskewed for clam shell path delay. Attached to the right is the two channels of the JBERT routed and deskewed the scope. They are identical with minimal loss.

Each below indicates the percentage of Eye opening that results through the clam shell interconnect system.

Table of Results for Eye Pattern Closure Through Clam Shell Interconnect Bit Rate

Clam Shell Interconnect Eye

Gore Calibration Cable Eye

1 Gb/s

407mV height 980ps width

470mV height 984ps width

3 Gb/s

338mV height 321.8ps width

440mV height 325.4 ps width

5 Gb/s

312mV height 189.52 width

444mV height 189.42 ps width

6.4 Gb/s

291mV height 132.16 ps width

433mV height 149ps width

8.0 Gb/s

286 mV height 106.01 ps width

418mV height 112.78 ps width

12.0 Gb/s

213 mV height 66.72ps width

413 mV height 66.72ps width

12 Gb/s comparison between the pure source from a jBERT (red) and the same signal sent through the clam shell connector. Even at more than two times the specified and measured interconnect bandwidth there is still a functional eye pattern to pass protocol and system BER measurements. This also illustrates that a clam shell interconnect system's losses will be dominated by the interface boards used in making the back plane or DUT board connections.