Low Cost Ultrasonic Sensor Unit

Low Cost Ultrasonic Sensor Unit First Semester Report Fall Semester 2013 -Full ReportBy A.J. Vander Ploeg Jason Ritzman Prepared to Partially Fulfill ...
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Low Cost Ultrasonic Sensor Unit First Semester Report Fall Semester 2013 -Full ReportBy A.J. Vander Ploeg Jason Ritzman Prepared to Partially Fulfill the Requirements for ECE 401 Department of Electrical and Computer Engineering Colorado State University Fort Collins, CO 80523

Project Supervisors: Jarrod Zacher and Dr. Azimi Approved by:

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ABSTRACT The content of this report contains an overview of the design of the low cost ultrasonic sensor unit and addresses the problem of the unavailability of a low cost, low power, passive monitoring system for bats. Currently there are passive monitoring units for bats available however the cost for these units range from $1000 to $6000. The system we are currently designing has a target cost between $100 and $200. The lower cost will allow larger quantities of systems to be placed in the field and therefore facilitate a larger amount of data. A previous engineer originally started this project but had to put it on hold which makes this project is a continuation of previous work. A prototype of the PCB was manufactured before they put the project on hold. Building on the previous engineers work, the senior design team had identified numerous issues with the previous hardware. Throughout the report, there will be discussion on the hardware debugging process that took place during the semester as well as the updates that had to be made to the ultrasonic sensor unit using Altium PCB Design software. These issues were analyzed and resolved through hardware modifications and a complete PCB redesign.

The PCB was

manufactured, and components were ordered and assembled on the PCB resulting in a new prototype. This new prototype was tested and results have shown that the hardware modifications resolved the issues with the previous hardware.

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Table of Contents

I. II. III.

IV.

Title Abstract Table of Contents List of Figures and Tables Introduction System Overview and Components Hardware Modification A. DC to DC Switching Converter Issues B. Power Saving Scheme Issues C. Replacement Ultrasonic Microphone D. Designing the New PCB E. Testing Revised PCB 1. The Power Saving System 2. The DC-DC Switching Converter 3. Microphone Testing Conclusions and Further Work A. Conclusions B. Future Work References Appendices Appendix A – Abbreviations Appendix B – Budget Appendix C – Project Timelines Appendix D – 3D Modeling and Views Acknowledgements

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List of Figures Figure 1: The Project Scheme Figure 2: Block Diagram of the Signal Processing Figure 3: System Block Diagram Figure 4: Output of Buck Boost Converter When LED is ON Figure 5: Output of Buck Boost Converter When LED is OFF Figure 6: New DC-DC Switching Converter Schematic Figure 7: Schematic of Problematic Power Saving Scheme Figure 8: MOSFET Symbol Figure 9: MOSFET I-V Curve Figure 10: Datasheet MOSFET Symbol Figure 11: Datasheet MOSFET I-V Curve Figure 12: Schematic of Revised Power Saving Scheme Figure 13: Frequency Response of Obsolete Microphone Figure 14: Frequency Response of Knowles SPU1410LR5H Microphone Figure 15: Bandpass-Filter Schematic Figure 16: Component Schematic for TPS63031 Figure 17: Footprint for TPS60631 Figure 18: PCB Complete Layout Figure 19: PCB Top Layer Only Figure 20: PCB Bottom Layer Only Figure 21: Split Internal Power Plane of PCB Figure 22: FreeDFM Potential Show Stoppers Figure 23: FreeDFM No Show Stoppers Figure 24: BOM for Ultrasonic Sensor Unit Figure 25: Converter Output with 200 mV Division Figure 26: Converter Output with 10 mV Division Figure 27: Original Converter Output with 200 mV Division Figure 28: New Converter Output with 200 mV Division Figure 29: Output Voltage of Op Amp vs. Frequency Figure 30: Gain of Op Amp vs. Frequency Figure 31: Input and Output Voltage of Op Amp @ 30 KHz Figure 32: Input and Output Voltage of Op Amp @ 60 KHz

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List of Tables Table 1: Microphone Testing Results

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I. Introduction The National Park Service (NPS) is interested in the large scale monitoring of bats to study bat populations and the reason there is interest in this is due to a fungus that is spreading around and wiping out bat populations. Monitoring bats can help identify their population concentrations and migration patterns, which could provide great information to potentially save bat populations from diminishing. A way to monitor these bats is to record their ultrasonic calls. Most of the ultrasonic recorders currently available cost thousands of dollars and have at most a passive recording ability of one week [1]. Due to the high cost, it is not feasible to buy a large quantity of these recorders. Also because of the short on-time for passive monitoring these units need to have batteries replaced in order to monitor over longer periods of time. To fill this need, our design team is currently working on developing a low cost and low power device. This report starts with an overview of the system and components where the basic setup and operation of the system will be outlined. The next chapter is the bulk of the report and deals with several hardware modifications. Large subsections deal with problems with the previous design including the DC to DC converter, power savings scheme, and replacing the previous ultrasonic microphone. The next subsection deals with revising of the design and the manufacture of a new PCB which was necessary to solve the issues of the previous design. The last subsection deals with the testing of the revised PCB in relation to previous issues found. The last chapter contains a short conclusion for the report and future work plans for the next semester. At the end of this paper are the references, appendices and acknowledgements.

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II. System Overview and Components The system will detect a bat’s ultrasonic call, process the signals to shift them in the frequency domain and output the conditioned signal to a low cost off-the-shelf commercial audio recorder with a sampling frequency of 96 KHz as shown in Figure 1. A commercial recorder doesn’t have a high enough sampling frequency to record some of the bat’s ultrasonic calls so a printed circuit board (PCB) will be developed to eliminate this limitation of the off the shelf recorders. An ultrasonic microphone is utilized to detect/capture bat calls and process these signals using a field programmable gate array (FPGA) as shown in Figure 2. The purpose of conditioning the signal is to shift the incoming signals in the frequency domain to a low enough frequency so a commercial audio recorder can record it.

Figure 1: The Project Scheme

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Figure 2: Block Diagram of Signal Processing The system utilizes battery power and must be deployed for greater than a month, therefore it must be low power. The device will include a power saving scheme to achieve low power consumption, it will be designed to not record during the daytime and record during the nighttime. A light sensor and microcontroller will be used to implement this low power design as shown in Figure 3. The light sensor will detect whether it is day or night and when it is nighttime, the sensor will communicate with the microcontroller to power on the FPGA and analog channels. The bottom portion of the block diagram is analogous to the signal-processing diagram of Figure 2. The power sources available for use will be an AC adapter plug-in or 2 AA batteries. To regulate power, a buck-boost switching converter was utilized to deliver a supply voltage of 3.3V to the microcontroller. The microcontroller will then distribute power to the FPGA and analog channels accordingly when it is nighttime. To control power flow to the FPGA and analog channels, low on-resistance load switches were employed at the output of one of the microcontroller ports. The switch in figure 3 represents where the load switches are placed. Once the analog channels and FPGA are powered on, bat signals can then be

4 processed. The signals will be picked up by an ultrasonic microphone and then output to a bandpass filter to only pass certain frequencies. The frequencies of interest are 30KHz60KHz but the band on the filter will be set a little higher than that range to make sure the frequencies of interest don’t get filtered out. The output of the bandpass filter will then be fed converted to a digital signal using an ADC and then that digital signal can then be processed by the FPGA. Once the signal is processed, it will be converted to an analog signal using a DAC and that signal can be output to a commercial audio recorder to record the processed signals.

Power

Microcontroller

Light Sensor

Component Power

Amp Stage

ADC

FPGA

DAC

To Recorder

Microphone

Figure 3: System Block Diagram

III. Hardware Modifications The original engineer who started this project, Katalin Orova, had to put this project on hold when she moved back to Europe. A prototype of the board was manufactured and testing revealed several hardware issues that needed to be corrected. The project was picked up and given to our senior design team to work on. The goal of this semester was to debug the hardware and make sure each component was working the way it was

5 intended. A.J. Vander Ploeg was in charge of debugging and redesigning the problematic hardware on the PCB while Jason Ritzman was responsible for learning the PCB design software (Altium) and designing a new PCB layout for the ultrasonic sensor unit. The first portion of the paper will show the old and new designs of the hardware and then the testing results of the newly manufactured board will be discussed

A. DC to DC Switching Converter Issue One major issue with the original prototype was a large amount of audible noise being generated when powered on. This is extremely undesired for the reason that our unit is designed to capture sound and if there is any audible noise created by the board’s hardware, this will distort the signals we are recording and reduce the integrity of the design. After performing several tests on the PCB, the potential problems were narrowed down. The source of this noise stems from the DC-to-DC switching converter on the PCB. When the audible noise problem was discovered, the first thing that was done was measuring the supply voltage on the input and output of the switching regulator. After further examination of the supply voltage, it was noticed there was a huge ripple voltage output by the power supply. Switching converters are generally a probable cause for issues like this because they employ the use of switching and magnetics (i.e. inductors) in the voltage conversion process. The switching converter originally utilized for this project was the TPS63020 buck boost converter designed by Texas Instruments. The output of the buck boost converter was measured and it was discovered that the noise problem was stemming from this component. There is an LED on board that blinks on

6 and off every second and the frequency that the voltage ripple was occurring at when the LED was on was 4,845 Hz as seen in Figure 3. When the LED was off, the frequency of the ripple changed to 1,493 Hz as seen in Figure 4.

Figure 4: Output of Buck Boost Converter When LED is ON; Switching Frequency of 4,845 Hz

Figure 5: Output of Buck Boost Converter When LED is OFF; Switching Frequency of 1,493 Hz

7 There was some uncertainty at first as to why this audible noise was occurring at different frequencies. It was determined that the change in frequencies had something to do with the load changing but there was still confusion on why the frequency of the converter was changing when this occurred. After pouring through the datasheet for the TPS63020, it was soon discovered why the frequencies were changing. From the TPS63020 datasheet, “If PS/Sync is set to low then Power Save Mode is entered when the average inductor current gets lower than 100 mA. At this point the converter operates with reduced switching frequency and with minimum quiescent current to maintain high efficiency,” [2]. The PS/Sync pin was connected to ground allowing the device to enter power saving mode with light loads. The current drawn by the power supply was measured and was only pulling 4.7 mA with the LED is off and 9.6 mA with the LED is on. Since the inductor current was well below 100mA, the converter was entering the power saving mode and lowering the switching frequency. The switching frequency of this component is 2.4 MHz, but once it enters power save mode it changes the switching frequency down to the KHz range, this was why there was audible noise stemming from the converter. Another part of the noise problem stemmed from the originally selected inductor. The inductor specifications did not closely match the recommended inductor values recommended by Texas Instruments. Voltage spikes with values around 400mVpp can be seen on the rising section of each period on the output ripple in figures 4 and 5. These voltage spikes are a little exaggerated due to probe parasitics, but these spikes still were present on the converter output ripple. The parasitics arise from the inductance and capacitance created by the scope probe when the leads are attached across the load being

8 measured. These parasitics can cause overshoot and fluctuation in the probe output so that is why the spikes in figures 4 and 5 seem a bit high. To rectify these interference issues, a different switching converter rated for lower output current was selected. The replacement converter is the TPS63031, which is in the same family as the original converter except it is rated for an output current of 800 mA. The original converter was rated for an output current of 4 Amps, which is overkill for system requirements. Instead of connecting the PS/SYNC pin to ground, a jumper was added as shown in Figure 5 to allow this converter’s power save mode to be toggled. An electrolytic cap (C7) was added to lower the ESR at the output as well as the inductor (L1) with recommended specifications as found in the Texas Instruments datasheet.

Figure 6: New DC-DC Switching Converter Schematic Power Saving Scheme Issues Another problem that was discovered during debugging was related to the power saving scheme. A feature on this board that allows us to save power, utilizes a light sensor that detects whether it is night or day. It is desired to have the board only process signals during the nighttime and go into sleep mode during the day. When the light

9 sensor detects that it is light outside, the light sensor communicates with our microcontroller to shut off power to the ultrasonic microphone and the FPGA. When this project was handed off to this design team, it was noticed that the power saving scheme was not working correctly. A new design was required to make this power saving feature work. The original schematic with the faulty power saving scheme is shown below.

Figure 7: Schematic of Problematic Power Scheme When the light sensor senses that it is night, it tells the microcontroller to send a logic level high voltage of 3.3 V to the wire labeled “From Output Pin of Microcontroller”. This voltage is connected to the gates of the MOSFETS controlling power to the analog channels and FPGA. Both branches include a MOSFET transistor and a couple of resistors. The transistors are used as switches and the resistors are there to bias the transistor. The intention of this design was that if a voltage of 3.3 V were to be set on the microcontroller output, this would bias both transistors and turn them “on”.

10 After further analysis of the biasing of Q3, it was realized that Q3 wasn’t working. A potential problem was that this transistor wasn’t in saturation mode. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has three modes of operation; cutoff, linear (or triode), and saturation. An important parameter a MOSFET has is a threshold voltage which is usually denoted as Vt. When the gate to source voltage VGS, is less than Vt, the MOSFET will not conduct current as the drain to source voltage, VDS, increases. This mode of operation is referred to as the cutoff mode. When VGS is greater than Vt, the MOSFET will conduct current as VDS increases. Figure 8 represents the parametric plot of the MOSFET current. There are five different current plots each having a different gate voltage. As shown in Figure 8, as VDS increases the current starts to increase in a linear fashion within the triode region. The region shaded in yellow is the linear region (triode region). Once the I-V plot reaches the blue shaded portion, it enters the saturation region. The VDS at which the linear region crosses over to the saturation region is known as the overdrive voltage, VOV, and this voltage is equal to VGS – Vt. In the saturation region, notice how variations in VDS will not cause the current to fluctuate. The linear region will cause large fluctuations in the current as VDS changes, which is undesirable if you are using a MOSFET as a switch. For a MOSFET to operate as a switch, one would like the MOSFET to operate in the saturation mode due to the small fluctuations in the current as the drain to source voltage changes. A MOSFET will be in saturation under the condition that VDS>VOV or if VGD