Lecture 18: VLSI Design Styles
Deming Chen
CMOS VLSI Design 4th Ed.
Outline Overview – Microprocessor/DSP – Programmable Logic – Gate Arrays and Sea of Gates – Cell-based Design – Full Custom Design – System on a Chip – Intellectual Property (IP) Reading – Part of the lecture is coming from Text 14.3 ECE 425
CMOS VLSI Design 4th Ed.
Slide 2
Where are we? Throughout the course, we’ve been increasing the scope of the modules – Transistors and gates – ALUs, multipliers, memories – Now, on to discussions of full-scale chip design Today’s lecture is intended as a bridge between what we’ve covered and where we’re going – Different design styles for chips Later, we’ll start talking about design flow, CAD tools, synthesis and high-level modeling, etc. ECE 425
CMOS VLSI Design 4th Ed.
Slide 3
Design Methodologies Different design methodologies provide varying degrees of freedom, cost and performance: – Microprocessor/DSP – Programmable Logic (FPGA and CPLD) – Gate array, sea of gates, and structured ASIC – Standard Cell – Custom – System-on-chip (core-based)
ECE 425
CMOS VLSI Design 4th Ed.
Slide 4
Microprocessor/DSP Standard microprocessor or digital signal processor (DSP) are very practical and usually offer great flexibility Systems can be upgraded in the field through software patches Off-the-shelf processors with wide range of clock speeds, memory sizes, and analog I/O capability Embedded processors are available for system-onchip design methodology May not be most efficient in terms of cost, speed and power dissipation ECE 425
CMOS VLSI Design 4th Ed.
Slide 5
Hardware Specialization: Efficiency vs. Flexibility"
Benefit of Hardware The Dilemma: FlexibilitySpecialization vs. Efficiency
MOPS/mW
P r o g r a m m a b le P r o c e s s in g
Source: “High-performance Energy-Efficient Reconfigurable Accelerator Circuits for the Sub-45nm Era” July 2011 Ram K. Krishnamurthy, Corp. by Ram Source: K. Krishnamurthy, Circuits Research Labs,Intel Intel Corp.
10 © 2 0 1 2 A lte r a C o r p o r a tio n — Public 1 6
CMOS VLSI Design 4th Ed.
Design Productivity Gap • Increasing complexity of designs • Reduced time-to-market
Verification/Predictability Gap • Delayed final tapeout
Quality Gap
Productivity/Complexity
Gaps Are Widening
• RTL design focusing on limited architecture alternatives
Gates/cm2 Moore’s Law (59%*) Design Gap Design Productivity (20-25%*)
Technology Scaling * Compound Annual Growth Rate Source: Semico Research Corp.
CMOS VLSI Design 4th Ed. Source: Pittsburgh Digital Greenhouse
Source: EETimes.com
One Case Study
Comparative study on Monte Carlo option pricing Data for a single option pricing, using 524,288 simulation paths
Source: “Reconfigurable Computing in the Multi-Core Era,” Khaled Benkrid, HEART’2010.
CMOS VLSI Design 4th Ed.
The Trend: High-level Synthesis (HLS) System level
Design spec. in high-level languages SW/HW Co-design C, C++, SystemC
Behavior level
• 10X code reduction High-level Synthesis
• 1000X simulation time reduction
RT level (VHDL, Verilog) controller
datapath
[Source: NEC]
Logic Synthesis
Levels of Abstraction
Gate level (netlist)
Chips 4th Ed. & Route CMOS Place VLSI Design
Two Major Types of Programmable Logic FPGA (field programmable gate array) – fine-grained logic cells – high logic density – good design flexibility CPLD (complex programmable logic device) – coarse-grained two-level AND-OR programmable logic arrays (PLAs) – fast and more predictable delay – simpler interconnect structures Low or no nonrecurring engineering cost (NRE) ECE 425
CMOS VLSI Design 4th Ed.
Slide 10
A Generic FPGA Architecture
K LUT
Inputs
Out
D FF
Clock
Programmable IO BLE #1
Programmable I Logic (CLB) Inputs
I
N
N Outputs
BLE #N
Clock
Programmable Routing
ECE 425
CMOS VLSI Design 4th Ed.
Slide 11
An Implementation of a 4-input Lookup Table (4-LUT) In0
In1
In2
16 SRAMs
In3
Out
…
Out = f (in0, in1, in2, in3) ECE 425
CMOS VLSI Design 4th Ed.
Slide 12
One Commercial FPGA, Altera Stratix II
ECE 425
CMOS VLSI Design 4th Ed.
Slide 13
Building Blocks of CPLD: PLA Structure
(k, m, p)PLA
ECE 425
CMOS VLSI Design 4th Ed.
Slide 14
One Commercial CPLD, Altera MAX7000
ECE 425Each
4th Ed. (36,80,16)-PLA LAB can be treated as Design a special CMOS VLSI Slide 15
Gate Array and Sea of Gates Another way of lowering NRE Construct a common base array of transistors Personalize the chip by altering the metallization (metal and via masks) Newer and modern versions are called Structured ASIC Vendors stock master or base wafers that have been processed up to the polysilicon gate layer Contacts and metallization are then specified on a per-design basis Wafer cost reduced by producing many base wafers for a variety of different chips Packaging cost reduced by using standard packages and pinouts Test and production costs are reduced by reusing common test fixtures ECE 425
CMOS VLSI Design 4th Ed.
Slide 16
Sea of Gates (SOG) Floorplan
ECE 425
CMOS VLSI Design 4th Ed.
Slide 17
SOG and Gate Array Cell Layouts
(a) SOG
(b) Gate Array
Gate array: array of transistors not continuous, can be grouped and perhaps individually sized ECE 425
CMOS VLSI Design 4th Ed.
Slide 18
SOG Programming Example
Custom design ECE 425
3-input NAND gate CMOS VLSI Design 4th Ed.
Slide 19
Cell-Based Design Design composed out of a set of pre-designed blocks, called standard cells – Cells often simple gates/latches, can be more complex – Cells pre-tested and pre-characterized – Companies offer standard cell libraries for use with their fabrication and CAD technologies • Amortize the effort of designing the cell library over all the designs that use it
ECE 425
CMOS VLSI Design 4th Ed.
Slide 20
Standard-Cell Design Organize cells into rows to make placement easier – Require that all cells have the same height
ECE 425
CMOS VLSI Design 4th Ed.
Slide 21
Full-Custom Design What we’ve been doing so far Designer specifies size, position, connections of every device in a circuit, down to the mask level Gives highest performance and device density Disadvantages: – Very tedious and complex – Long design times – Higher design cost – Error prone Nowadays, this design style is used only for parts of state-ofthe-art designs where performance and area are pushed to the limits (to achieve an A grade). ECE 425
CMOS VLSI Design 4th Ed.
Slide 22
System-on-a-Chip (Platform-Based) Motivation: Even with synthesis from VHDL/Verilog, design effort for modern chips is very large. Observation: Many VLSI systems incorporate similar components – ALUs – Memory Interfaces – RAM blocks – DSP modules Idea: Provide a set of cores (Intellectual Properties) that perform common functions, let designers use them – Eliminate the need to re-design – Becomes worth the effort to heavily optimize cores ECE 425
CMOS VLSI Design 4th Ed.
Slide 23
Intellectual Property (IP) Building block components (roughly equivalent terms) – Macros, cores, IPs, virtual components (VCs)
Examples – Microprocessor core, A/D converter, Digital filter, Audio compression algorithm
Three types of IP blocks – Hard (least flexible) – Firm – Soft (most flexible) CMOS VLSI Design 4th Ed.
IPs Consumer Wireless Set-top box Smart devices ……
SoC System
Hardware
Software
ASICs Processors
Memories
OS
IOs CMOS VLSI Design 4th Ed.
Application
Hard IP Delivered in physical form (e.g., GDSII file) Fully – Designed – Placed and routed – Characterized for timing, power, etc.
Tied to a manufacturing process – Actual physical layout – Fixed shape
Complete characterization – Guaranteed performance – Known area, power, speed, etc.
No flexibility CMOS VLSI Design 4th Ed.
Fixed Schematics and Layout Power
Hard Macros C A
A-Input
Data Out
B-Input
B
Ground Schematic of a NAND gate
Layout of a NOR gate CMOS VLSI Design 4th Ed.
Hard IP Examples and Constraints A microprocessor core – PowerPC, ARM
AMS (analog/mixed-signal) blocks – ADC, DAC, filter
A phase-locked loop (PLL) A memory block design Features – Deeply process dependent – Stricter performance requirements – Electrical constraints, such as capacitance, resistance, and inductance ranges – Geometric constraints, such as symmetry, dimension, pin location, etc. – Need to provide interface for functional and timing verification CMOS VLSI Design 4th Ed.
Soft IP Delivered as synthesizable RTL HDL code (e.g., VHDL or Verilog) – can be SystemC/C/C++ code now. Performance is synthesis and process dependent Synthesizable Verilog/VHDL/SystemC/C/C++ Synthesis scripts, timing constraints Scripts for testing issues – Scan insertion, ATPG (automatic test pattern generation), etc.
CMOS VLSI Design 4th Ed.
Soft IP Example in VHDL ENTITY example IS PORT(clock, a, b, sel:IN BIT; d:OUT BIT); END example;
ARCHITECTURE behavior OF example IS BEGIN PROCESS (clock) IF (clock’EVENT AND clock=‘1’) THEN IF (sel=‘1’) THEN d