Lecture 15: Processor Design
Why Everything You’ve learned Matters
HW3 Assigned • Due: June 2, 4:30pm, via homework dropbox
Pushing the Bubbles • When a logic unit has just NAND/AND gates, you can convert it into using just NOR/OR/ NOT gate by bubble-‐pushing – Using DeMorgan’s Law
• The same applies to NOR/OR gates
Outline of Today’s Lecture • Design a processor: step-‐by-‐step • Requirements of the InstrucUon Set • Hardware components that match the instrucUon set requirements
5 components of any Computer Personal Computer!
Computer! Processor! ! Control! (“brain”)! Datapath! (“brawn”)!
Memory! ! ! (where " programs, " data " live when" running)!
Devices! Input!
Output!
Keyboard,
Mouse" Disk
(where " programs, " data " live when" not running)"
Display,
Printer"
An Abstract View of the ImplementaUon Control
Clk
PC
Address
A
32
Rw
Ra
Rb
32
32 32-bit
Registers
B
Clk
ALU
Next Address
Ideal
Instruction
Instruction
Control Signals
Conditions
Memory
Rd
Rs
Rt
5
5
5
Instruction
Data
Data
32
Address
Ideal
Out
Data
Data Memory
In
32
Datapath
Clk
How to Design a Processor: step-‐by-‐step • Analyze instrucUon set architecture (ISA) • Find out datapath requirements – meaning of each instrucUon is given by the register transfers – datapath must include storage element for ISA registers – datapath must support each register transfer
• Select set of datapath components and establish clocking methodology • Assemble datapath meeUng requirements • Analyze implementaUon of each instrucUon to determine se]ng of control points that effects the register transfer. • Assemble the control logic
The MIPS InstrucUon Formats • All MIPS instrucUons are 32 bits long. 3 formats: 31
26
21
16
11
6
– R-‐type
– I-‐type
– J-‐type
op
6 bits
31
26
op
6 bits
31
26
op
6 bits
rs
5 bits
21
rs
5 bits
• The different fields are:
rt
5 bits
16
rt
5 bits
rd
5 bits
shamt
5 bits
0
funct
6 bits
0
address/immediate
16 bits
0
target address
26 bits
– op: operaUon (“opcode”) of the instrucUon – rs, rt, rd: the source and desUnaUon register specifiers – shamt: shic amount – funct: selects the variant of the operaUon in the “op” field – address / immediate: address offset or immediate value – target address: target address of jump instrucUon
Step 1a: The MIPS-‐lite Subset • ADDU and SUBU
31
– addu rd,rs,rt
op
6 bits
– subu rd,rs,rt
• OR Immediate:
31
– ori rt,rs,imm16
• LOAD and STORE Word
26
31
26
op
6 bits
26
op
6 bits
21
rs
5 bits
21
rs
5 bits
21
rs
5 bits
16
rt
5 bits
11
rd
5 bits
6
shamt
5 bits
16
rt
5 bits
funct
6 bits
0
immediate
16 bits
16
rt
5 bits
0
0
immediate
16 bits
– lw rt,rs,imm16 – sw rt,rs,imm16
• BRANCH:
31
– beq rs,rt,imm16
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
Register Transfer Language • RTL gives the meaning of the instrucUons {op , rs , rt , rd , shamt , funct} = MEM[ PC ]
, rs , rt , {op
Imm16}
= MEM[ PC ]
• All start by fetching the instrucUon inst
Register Transfers
ADDU
R[rd] = R[rs] + R[rt];
PC = PC + 4
SUBU
R[rd] = R[rs] – R[rt];
PC = PC + 4
ORI
R[rt] = R[rs] | zero_ext(Imm16);
PC = PC + 4
LOAD
R[rt] = MEM[ R[rs] + sign_ext(Imm16)];
PC = PC + 4
STORE
MEM[ R[rs] + sign_ext(Imm16) ] = R[rt];
PC = PC + 4
BEQ if ( R[rs] == R[rt] ) then
PC = PC + 4 + (sign_ext(Imm16) || 00) elese PC = PC + 4
Steps again Analyze ISA Select components Assemble datapath Determine control points Build control logic
Step 1: Requirements of the InstrucUon Set • Memory (MEM)
– instrucUons & data
• Registers (R: 32 x 32) – read RS – read RT – Write RT or RD
• PC • Extender (sign extend) • Add and Sub register or extended immediate • Add 4 or extended immediate to PC
Step 2: Components of the Datapath • CombinaUonal Elements • Storage Elements
CombinaUonal Logic Elements (Building Blocks) Select
CarryIn
A
A
32
32
Sum
B
CarryOut
Adder
32
MUX
Adder
B
32
32
MUX OP
A
ALU
B
32
32
ALU
32
Result
32
Y
Storage Element: Idealized Memory • Memory (idealized) – One input bus: Data In – One output bus: Data Out • Memory word is selected by:
Write Enable
Address
Data In
32
Clk
DataOut
32
– Address selects the word to put on Data Out – Write Enable = 1: address selects the memory word to be wrigen via the Data In bus
• Clock input (CLK) – The CLK input is a factor ONLY during write operaUon – During read operaUon, behaves as a combinaUonal logic block: • Address valid ⇒ Data Out valid acer “access Ume.”
Storage Element: Register (Building Block) – Similar to D Flip Flop except • N-‐bit input and output • Write Enable input
– Write Enable: • negated (or deasserted) (0): Data Out will not change • asserted (1): Data Out will become Data In
Write Enable
Data In
N
Data Out
N
Clk
Storage Element: Register File • Register File consists of 32 registers: – Two 32-‐bit output busses: busA and busB – One 32-‐bit input bus: busW
• Register is selected by:
RW
RA
RB
Write Enable
5
5
5
busA
busW
32
32 32-bit
32
Registers
busB
Clk
32
– RA (number) selects the register to put on busA (data) – RB (number) selects the register to put on busB (data) – RW (number) selects the register to be wrigen via busW (data) when Write Enable is 1
• Clock input (CLK) – The CLK input is a factor ONLY during write operaUon – During read operaUon, behaves as a combinaUonal logic block: • RA or RB valid => busA or busB valid acer “access Ume.”
Step 3: Assemble DataPath meeUng requirements • Register Transfer Requirements ⇒ Datapath Assembly • InstrucUon Fetch • Read Operands and Execute OperaUon
3a: Overview -‐ InstrucUon Fetch Unit • The common RTL operaUons – Fetch the InstrucUon: mem[PC] – Update the program counter: • SequenUal Code: PC = PC + 4 • Branch and Jump: PC = “something else” Clk
PC
Next Address
Logic
Address
Instruction
Memory
Instruction Word
32
3b: Add & Subtract • R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt – Ra, Rb, and Rw come from instrucUon’s Rs, Rt, and Rd 31
26
21
16
11
6
0
fields op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
– ALUctr and RegWr: control logic acer decoding the instrucUon Rd
Rs
Rt
RegWr
5
5
Already
Rw
Ra
Rb
32 32-bit
Registers
busA
32
busB
32
ALU
busW
32
Clk
ALUctr
5
Result
32
defined register file, ALU
3c: Logical OperaUons with Immediate • R[rt] = R[rs] op ZeroExt[imm16] ] 31
26
op
31
6 bits
21
16
rs
5 bits
11
rt
immediate
5 bits
16
15
rd?
16 bits
ALU
immediate
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rd
Rt
RegDst
16 bits
16 bits
Mux
Rt register read??! Rs
Rt?
What about ALUct RegWr
5
5
5
r
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit
32
Registers
32
busB
Clk
32
Mux
Already
16
ZeroExt
imm16
32
ALUSrc
defined 32-bit MUX; Zero Ext?
0
0
3d: Load OperaUons • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 31
Rd
RegDst
Mux
RegWr
5
32
Clk
op
6 bits
Rt
rt
5 bits
0
immediate
16 bits
ALUctr
busA
W_Src
32
ExtOp
Mux
32
32
MemWr
Mux
busB
32
Extender
16
16
rs
5 bits
Rs
Rt
5
5
Rw
Ra
Rb
32 32-bit
Registers
imm16
21
ALU
busW
26
WrEn
Adr
??
ALUSrc
Data In
32
Clk
Data
Memory
32
3e: Store OperaUons • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 31
26
21
op
rs
6 bits
5 bits
Rd
Rt
RegDst
Mux
RegWr
5
5
rt
5 bits
immediate
16 bits
ALUctr
MemWr
W_Src
32
ExtOp
32
WrEn
Adr
Data In
32
32
Data
Clk
Memory
ALUSrc
Mux
Extender
16
32
ALU
busA
Rw
Ra
Rb
32
32 32-bit
Registers
busB
imm16
0
Rs
Rt
5
Mux
busW
32
Clk
16
3f: The Branch InstrucUon 31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
• beq rs, rt, imm16 – mem[PC] Fetch the instrucUon from memory – Equal = R[rs] == R[rt] Calculate branch condiUon – if (Equal) Calculate the next instrucUon’s address • PC = PC + 4 + ( SignExt(imm16) x 4 )
else • PC = PC + 4
Datapath for Branch OperaUons • beq rs, rt, imm16 Datapath g26
enerates condiUon (equal) 31
21
16
nPC_sel
4
Adder
00
PC
Mux
Already
Rs
Rt
5
busA
Rw
Ra
Rb
32
32 32-bit
Registers
busB
32
Cond
RegWr
5
5
32
Adder
PC Ext
imm16
rs
rt
immediate
5 bits
5 bits
16 bits
Inst Address
busW
Clk
Equal?
op
6 bits
0
Clk
MUX, adder, sign extend, zero
A Single Cycle Datapath Instruction
Inst
Memory
Adr
Rs
Rt
Rd
Imm16
imm16
Mux
ExtOp
ALUSrc
ALU
Extender
Mux
PC
PC Ext
Adder
Mux
Adder
00
4
nPC_sel
RegDst
ALUctr
MemWr
MemtoReg
Equal
Rt
Rd
1
0
Rs
Rt
RegWr
5
5
5
busA
Rw
Ra
Rb
=
busW
32
32 32-bit
0
32
32
Registers
busB
0
32
Clk
32
WrEn
Adr
1
1
Data In
Data
imm16
32
Clk
16
Clk
Memory
An Abstract View of the ImplementaUon Control
Clk
PC
Address
A
32
Rw
Ra
Rb
32
32 32-bit
Registers
B
Clk
ALU
Next Address
Ideal
Instruction
Instruction
Control Signals
Conditions
Memory
Rd
Rs
Rt
5
5
5
Instruction
Data
Data
32
Address
Ideal
Out
Data
Data Memory
In
32
Datapath
Clk
Peer InstrucUon (true of false) A. If the desUnaUon reg is the same as the source reg, we could compute the incorrect value! B. We’re going trdo be able to read 2 registers and write a 3 in 1 cycle C. Datapath is hard, Control is easy The answer is 3 (FTF)
1: 2: 3: 4: 5: 6: 7: 8:
ABC FFF FFT FTF FTT TFF TFT TTF TTT
Summary: Single cycle datapath
° 5 steps to design a processor • 1. Analyze instruction set ⇒ datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic Processor
Input
Control
Memory
Datapath
Output