Lecture 1- Introduction Erno Salminen TKT-1212 Digitaalijärjestelmien toteutus Tampere University of Technology 2012-2013
Department of Computer Systems
Lecture contents 1. Course organization 2. Introduction to implementing digital
systems
#2/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Course Goals Get to know practical digital system design Aware of challenges of digital system design Design for efficiency Design for large scale Large module, large system, overall development process Design for portability Device independency, software independency, design reuse
#3/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Course Description Web: http://www.tkt.cs.tut.fi/kurssit/1212/ Note: This course is as POP-free as possible Lectures, starting at 8.1.2013 Tuesday 10-12 TB223 (Period 3) and TB222 (Per4) Wednesday 12-14 TB223 (three times in January! )
Exercises at TC417, starting at 8.1.2013 Arto Perttula, Jussi Raasakka Tue 8-10 Thu 14-16
#4/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Course Description (2) Course requirements: Regular exam or two midterm exams (own notes are allowed) Succesful exercises/exercise work Course primarily based on book: RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Chu, Pong P. (2006)
Can be borrowed from the lecturer Available at TUT library
Snippets from other sources also Available from the lecturer Lectures and lecture notes should be enough for
passing the course
#5/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Course contents I.
VHDL language Very High Speed Integrated Circuit Hardware Description language = VHSIC HDL = VHDL Familiarize with the language constructs
II. Testbenches and simulators, synthesis,
guidelines for re-use III. FPGA circuits, designing for them IV. Advanced topics: Multiple clock domains, clock synchronization, system design challenges
#6/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Preliminary schedule, spring 2013 # 1 2 3 4 5 6 7 8 9 ‐ 10
I. II. III.
11 12 13
IV.
14 15 16 (x)
#7/44
PÄIVÄ AIKA 8.1.2013 Ti 10‐12 9.1.2013 Ke 12‐14 15.1.201 Ti 10‐12 16.1.201 Ke 12‐14 22.1.201 Ti 10‐12 23.1.201 Ke 12‐14 29.1.201 Ti 10‐12 5.2.2013 Ti 10‐12 12.2.201 Ti 10‐12 19.2.201 Ti 10‐12 26.2.201 Ti 10‐12 viikko 10 5.3.2013 Ti 10‐12 12.3.201 Ti 10‐12 26.3.201 Ti 10‐12 2.4.2013 9.4.2013 Ti 10‐12 16.4.201 Ti 10‐12 24.4.201 Ti 10‐12 30.4.2013 7.5.2013 Ti 10‐12 Viikko 20‐21
Spring 2013 - Erno Salminen
PAIKKA TB223 TB223 TB223 TB223 TB223 TB223 TB223 TB223 TB223 TB223 TB223 TB222 TB222 TB222 TB222 TB222 TB222 TB222
AIHE Kurssin järjestelyt, johdanto VHDL‐perusteet #1, mm. entity ja arkkitehtuuri VHDL‐perusteet #2 ‐ prosessit, signaalit, tyypit VHDL‐perusteet #3 ‐ paketit, kirjastot, operaattorit, attribuutit VHDL: Kombinatorisen ja sekventiaalisen logiikan kuvaaminen generic‐parametrit, lausekkeet RTL‐synteesi, tilakoneen toteuttaminen Testipenkit HDL‐simulaattorit Uudelleenkäyttö, Välikoe luentojen 1‐8 aiheista , ei tarvitse ilmoittautua, 1 A4‐arkillinen muistiinpanoja sallittu FPGA‐piirit yleisesti (luennot 10+11 samassa pdf:ssä) tenttiviikko 1. välikokeen käsittely , Esimerkki‐piiri: Altera Stratix III, suunnitteluesimerkki SDRAM‐liitynnästä Sekalaisia huomioita, kuten reset, muuttujat ja latchit Kellotus ja synkronointi Pääsiäisloma Kellotus ja synkronointi (jatkuu) Projektin hallinta , Vierailuluennon tarkka päivä varmistuu myöh. Järjestelmäsuunnittelun haasteita Wappu (varalla) 2 x tenttiviikko
Department of Computer Systems
Exercise work Simple audio synthesizer implemented on
FPGA development board Each of the four buttons produces different tone Sound is heard from the external speakers
Block diagram of the synthesizer #8/44
Spring 2013 - Erno Salminen
DE2 development board Department of Computer Systems
During the exercises, you’ll learn 1. to describe, synthesize, and verify digital
systems using VHDL
De facto standard in European microelectronic industry
2. to read data sheets 3. to use I2C bus developed by Philips. Serial bus used e.g. in car industry 4. to operate Wolfson audio codec chip also used e.g. in some iPods
#9/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Exercises in practice Weekly exercises in TC417 (Linux class) Done in groups of two (alone only in special cases) Two guidance sessions per week
Presence is not required
Return is mandatory Deadline is within two weeks (due Sunday 23:59)
The first exercise on week 2, 7-11.01.2013 Possibility to gain 6 bonus points to the passed
exam by completing separate bonus tasks You must report (avg) hours per person for each exercise
#10/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Reserve enough time Exercises take 3-4h/week on average but verification is harder than you think large variations between groups
8
avg (kaikki)
7
min
6
7.46
7.33
5.84 4.70
5
4.28
3.96
4 2.64
gen. +
hier.
tied-tb
kolmio
audioctrl
2
1.85
2.07
3-b +
3
2
3
4
5
6
7
1.45
1.55
tutoriaali 1
1.87
2.18
1.97
1.71
1
8
synth
fifo
debug
i2c tb
i2c
0 audio tb synth top quartus
Harjoituskohtaiset ajankäyttö, [tuntia]
Start early!
9 10 11 12 13 14 15
Harjoitus #11/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Getting the development boards and softwares Students may borrow an FPGA kit to do exercises and own hobby projects. You may keep the kit if you write a
BSc/MSc thesis for Department of Computer Systems. Next pickups Wed 9.1.2013 and Thu 10.1.2013 at 16-17 from the room TG312 http://www.tkt.cs.tut.fi/Opetus/Fpga_board
Students may install the needed
EDA tools to their own computer http://www.tkt.cs.tut.fi/tools/public/tutorials/me
ntor/licensing/licensing.html
#12/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Action points 1. Apply for a Birdland account if you do not
have one (http://www.cs.tut.fi/lintula/) 2. Fill and sign Access application and confidentiality agreement
Return the form to Jari Salo’s at room TE207 Access rights from fall 2012 are still valid
3. Register to one of the exercise groups 4. Optional: You may install the needed SW
tools to your home computer 5. Optional: You may borrow an Altera DE2 FPGA board #13/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Yksinkertaistetut kurssien esitiedot 11/12, laatinut ES Esitiedot /Koulutusohjelmakohtaiset
TKT-1101 DigTeknPer. 4 op (s1)
Kandidaatin tutkinto 25 op TKT-1212 DigJärjTot 8 op (k3)
tai ELE1010 TKT-1220 Aritmetiikka 4 op (k3) TKT-1230 Laboratorio 3 op (k4)
TKT-3200 Tietokonetekn. I 5 op (s1)
TKT-3400 Tietokonetekn. II 5 op (k3)
tai ELE-2300
TKT-1570 Kandityö semin. 8 op
pakollinen Esitietoksi käy TKT-1202 tai TKT-1212 suositeltava Tarkista eksaktit esitietovaatimukset opintooppaasta. #14/44
Spring 2013 - Erno Salminen
TKT-2431 SoC-Suunn 5 op (s1) TKT-1400 ASIC I 5 op (s1)
TKT-1202 DigSuunn 5 op (s1)
TKT-1110 Mikroprosess. 5 op (k3)
DI-tutkinto 30 op
TKT-1410 SuunnVarm 5 op (s3)
TKT-3541 Soc-Alustat 5 op (k3)
Major changes to curriculum are expected for study year 2013-2014 due to TUT organizational restructuring
TKT-1527 DigSysDesIss. 5 op (k3)
TKT-3500 Mikrokontroll. 5 op (s1) TKT-2301 Lang. sens.v sov. 5 op (s1) TKT-2530 SatellPaikann 5 op (s1)
TKT-2526 Project work 5-8 op
TKT-3526 Proc. Design 5 op (k3)
TKT-2456 Wireless.sen s. 5 op (k3)
TKT-9626/9636 Seminar 3-6 op TKT-1540/1550 DI-työ semin. 1+0 op TKT-9646 Colloqium 3 op
TKT-2566 GNSS. 5 op (k3) TKT-2556 Inertial nav. 5 op (k4)
TKT-9617 ScientificPubl 6 op (s1) Department of Computer Systems
1. Introduction
Department of Computer Systems
Acknowledgements Prof. Pong . P. Chu provided ”official” slides
for the book which is gratefully aknowledged See also: http://academic.csuohio.edu/chu_p/
Most slides were made by Ari Kulmala and other previous lecturers (Teemu Pitkänen, Konsta Punkka, Mikko Alho…)
#16/44
Spring 2013 - Erno Salminen
TKT-1212 Dig.järj.tot., syksy 2008, A. Kulmala, TTY
Department of Computer Systems
Digital Circuits Nowadays found everywhere - From washing machines to
space shuttles Digital circuits are typically integrated circuits (IC) Minimize the number of discrete components Typical digital systems, such as cellular phones, contain (Several) Processors and co-processors Application-specific hardware An on-chip interconnection between the components Memory
RAM, FLASH, even hard disks
RF/Analog IC Out of the scope of this course
#17/44
Spring 2013 - Erno Salminen
Department of Computer Systems
How to implement a digital system No two applications are identical and every one
needs certain amount of customization Basic methods for customization 1. “General-purpose hardware” with custom software General purpose processor (GPP): e.g., performance-
oriented processor (e.g., Pentium), cost-oriented processor (e.g., AVR micro-controller) Special purpose processor: architecture with a specific set of functions: e.g., DSP processor (efficient multiply-add), network processor (to do buffering and routing), GPU (to do 3D rendering)
2. Custom software on a custom platform (CPU+other
hardware) (requires hardware-software co-design) 3. Custom hardware (no software) #18/44
Spring 2013 - Erno Salminen
Department of Computer Systems
How to implement a digital system (2) Trade-off between flexibility,
programmability, design effort, cost, performance, and power consumption A complex application contains many different tasks and use more than one customization methods
#19/44
Spring 2013 - Erno Salminen
Department of Computer Systems
1a. Device Technologies
Department of Computer Systems
Fabrication of an IC Transistors and connections are made from many layers
(typical 10 to 15 in CMOS) built on top of one another Ever increasing number of layers (more layers, more cost, though) Each layer has a special pattern defined by a mask One important aspect of an IC is the length of a smallest feature that can be fabricated Feature may stands for channel legnth of the transistor or the width of a wire (or something completely different…) Unit is micrometer (m, 10-6 meter), or nanometer, 10-9m E.g., we may say an IC is built with 0.35 μm process The process continues to improve (Moore’s law) even in deep sub-micron era The state-of-art commercial process is 22 nm, and Intel has demonstrated 14nm #21/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Fabrication of an IC (2) 1. 2. 3. 4. 5. 6.
#22/44
Purified silicon ingot (cylinder) is sliced into wafers (e.g. 12inch diameter) Wafer is coated with photoresist Light shines through the mask Photoresist not hit by light is washed away New layers (n-well, dielectric, copper wire, via etc.) are created on top of the silicon Finally, the rectangular dies (chips, e.g. 1-200 mm2) are sawed from the wafer, tested, and packaged
Spring 2013 - Erno Salminen
Department of Computer Systems
Example lithography machine
[K.M. Palmer, An extremely fine line , IEEE Spectrum, Jan 2012, pp. 47 - 50] #23/44
Spring 2013 - Erno Salminen
Department of Computer Systems
...
What does an IC looks like? M3
M2
insulator
Interconnect
via
via M1
M1
Cells
contact ...
silicon substrate transistor
#24/44
Spring 2013 - Erno Salminen
Department of Computer Systems
What does an IC look like? (2) Several metal layers Less congention
Hierarchical scaling Wires on top
levels are wider and taller than on lower levels
Top layers for Power supply Clock Global signals
transistors
[ITRS 2003] #25/44
Spring 2013 - Erno Salminen
Department of Computer Systems
What does an IC look like? (3) Intel Penryn dual core.
The IC
Package http://www.namedevelopment.com/blog/archives/Intel-penryn.gif http://www.intel.com/pressroom/kits/45nm/photos.htm #26/44
Spring 2013 - Erno Salminen
Department of Computer Systems
What does an IC look like? (4) 45 nm, quad-core Note the symmetry Two dual-cores integrated
#27/44
Spring 2013 - Erno Salminen
http://www.intel.com/pressroom/kits/45nm/photos.htm
Department of Computer Systems
What does an IC look like (5) Actel Fusion Mixed-signal FPGA 1. Integrated Analog-to-Digital
Converter (ADC) 2. Fusion Supports Low Power, synchronization 3. Embedded Flash Memory 4. Advanced I/O Standards 5. Charge Pumps 6. Analog Quads 7. Flash FPGA VersaTile 8. SRAM and FIFOs 9. Integrated Oscillators—Crystal and RC 10.Routing Structure 11.JTAG http://www.actel.com/documents/Fusion_PIB.pdf #28/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Classification: Where HW customization is done
a) In a fabrication facility: ASIC Full-custom, Standard cell, and Gate array ASIC (Application Specific IC) b) In the “field”: non-ASIC Simple/Complex field programmable logic device Off-the-shelf SSI/MSI (Small/Medium Scaled IC) components
#29/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Full-custom ASIC All aspects (e.g., size of a transistor) of a circuit
are tailored for a particular application. Circuit fully optimized Design extremely complex Very time consuming design (Typically only feasible for small components) Masks needed for all layers Very expensive Fabrication time up to months
Example: Intel, AMD , and
IBM processors are (partly) full-custom
#30/44
Spring 2013 - Erno Salminen
Fig. Silicon layout editor
Department of Computer Systems
Standard-Cell ASIC Circuit made using a set of pre-defined logic
components , known as standard cells
E.g., basic logic gates, 1-bit adder, D-FF Library cannot be altered albeit
some basic parameters can (e.g. fan-out) Height of a cell is pre-determined Layout of the complete circuit is customized 1. The location and type of the standard cells 2. Connections between cells
SC-ASIC has fixed-height rows of std cells
Layout created with special
EDA tools Masks needed for all layers Same fabrication cost as
with full custom
Eg. Mobile phone digital ICs #31/44
Closer look at 4 standard cell rows. Power can ground lines run horizontally inside the cells Spring 2013 - Erno Salminen
Department of Computer Systems
Gate array ASIC Circuit is built from an array of a single type of cell
(known as base cell) Base cells are pre-arranged and placed in fixed positions, aligned as one- or two-dimensional array Connections customized by the designer
More sophisticated components (macro cells) can
be constructed from base cells Masks needed only for metal layers (connection wires) Cheaper than full custom
or standard cell
Aka. channelless array or
sea of gates array #32/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Complex Field Programmable Logic Device Device consists of an array of generic logic 1.
cells and general interconnect structure Logic cells and interconnect can be “programmed” by utilizing “semiconductor fuses” or “switches” Customization is done “in the field” Two categories: CPLD (Complex Programmable Logic Device) Sea-of-gates to implement logic
2. FPGA (Field Programmable Gate Array) Look-up tables to implement logic No custom mask needed For example, Cisco 2600 series routers and
this course
#33/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Simple Field Programmable Logic Device (PLD) Programmable device with simple internal structure E.g., PROM (Programmable Read Only Memory), PAL (Programmable Array Logic) No custom mask needed Outdated technology Replaced by CPLD/FPGA
Fig.1 Example PAL (AND-OR net) #34/44
Spring 2013 - Erno Salminen
Department of Computer Systems
SSI/MSI components Small discrete parts with fixed,
limited functionality
E.g. few AND-ports in Printed
Circuit Board (PCB)
E.g., 7400 TTL series has
more than 100 parts Resources (e.g., power, board area, manufacturing cost etc.) is consumed by package but not silicon No longer a viable option except for hobby projects #35/44
Spring 2013 - Erno Salminen
Fig.1 Example component
Fig. 2 TTL clock with 7400s. Rather hackish, ehh. Department of Computer Systems
Viable technologies
FPGA and Standard Cell ASIC This course TKT-1400 ASIC-suunnittelu I
#36/44
Spring 2013 - Erno Salminen
Department of Computer Systems
1b. Comparing the technologies
Kludgetech
Gizmotech
Department of Computer Systems
Comparison criteria Area (Size, silicon real-estate): [mm2], [eq. gates] Speed (Performance): [MHz], operations/second [op/s] Time required to perform a task, [s] Power consumption, [mW] Cost, [€] Design effort, [person-month]
#38/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Std cell ASIC versus FPGA 1. Area [1] ASIC is smaller since the cells and interconnect are customized FPGA has overhead for programmability and capacity cannot be completely utilized Roughly: FPGA area is approximately 35x using the LUT-based logic elements
However, that is not directly seen by FPGA end users – high volume compensates some costs ($$)
2. Performance [1] Roughly: ASIC has 3.4 - 4.6x frequency compared to FPGA
3. Power [2] ASIC is bettter, the ratio ~10x [1] I. Kuon and J. Rose, "Measuring the Gap between FPGAs and ASICs" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 2, FEBRUARY 2007, pp. 203 - 215. [2] John Blyler, Navigating the Silicon Jungle: FPGA or ASIC?, June / July 2005 issue of Chip Design Magazine, [online]: http://chipdesignmag.com/display.php?articleId=115&issueId=11 #39/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Cost of Integrated Circuits Types of cost:
1. Chip costs NRE (Non-Recurring Engineering) cost: onetime, per-design cost Part cost: per-unit cost 2. Indirect design costs Lead time: time to get the chip out of the factory Time-to-market “cost” loss of revenue Standard cell: high NRE, small part cost and large lead time FPGA: low NRE, large part cost and small lead time #40/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Cost of Integrated Circuits (2) For ASIC, first-time-right necessary FPGA has lower NRE, but higher RE Suitable for low volumes
faster growth rate than with ASIC
cost [€]
Break even volume getting bigger all the time
FPGA cheaper
ASIC cheaper
FPGA ASIC
trend
Xilinx Inc. #41/44
Spring 2013 - Erno Salminen
#chips break even Department of Computer Systems
Summary of technologies
Trade-off between optimal use of hardware resource
and design effort/cost No single best technology #42/44
Spring 2013 - Erno Salminen
Department of Computer Systems
Conclusions
Department of Computer Systems
Conclusions Two viable implementation technologies: ASIC
and FPGA ASICs are smaller in area and faster than FPGA ASICs have low unit cost but high NRE, FPGA vice versa ASICs used in high volume products, FPGAs in
tailorable products
FPGA is a ”programmable ASIC” (custom IC,
actually)
i.e. someone (Altera, Xilinx etc.) has done an IC
the application of which is FPGA Extra resources needed to provide in-field configuration #44/44
Spring 2013 - Erno Salminen
Department of Computer Systems