LatticeSC PCI Express x8 Evaluation Board User’s Guide

April 2007 Revision: EB19_01.3

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

Introduction This user’s guide describes the LatticeSC PCI Express x8 Evaluation Board featuring the LatticeSC LFSCM3GA80EP1-6FC1152C FPGA device. This stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces and/or PCI Express protocols. The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. The board has several debugging and analyzing features for complete user evaluation of the LatticeSC device. This user’s guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeSC FPGA. Figure 1. LatticeSC PCI Express x8 Evaluation Board SERDES Channels 360/CH#0/#3

SERDES Quad 361/CH#0:3 Test LEDs

BNC Video Input/Output 360 Ch#1

ispVM Connector

16-Segment Display

Test Input Switches

LVDS

DDR2 SDRAM 84 fpBGA

PCI Express x8 2 Quads 3E0-3E1

LatticeSC 1152 fpBGA

Reference Clock Management

Features • LatticeSCM-80 device in 1152 fcBGA package • SERDES interface to x8 PCI Express edge fingers • DDR2 memory device • SERDES high-speed interface SMA test points and clock connections • Power connections and power sources • ispVM® programming support • On-board and external reference clock sources • Interchangeable clock oscillators • On-board reference clock management using Lattice ispClock™ devices • ORCAstra demonstration software interface via standard ispVM JTAG connection

2

Power Supplies

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor • Various high-speed layout structures • User-defined input and output points

• SMA connectors included (10) for high-speed clock or data interfacing • Performance monitoring via test headers, LEDs and switches This user’s guide includes top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 2 shows the functional partitioning of the board.

Additional Resources For additional information and resources related to this board, including updated documentation and hardware/software demos, please see the Lattice web site at: www.latticesemi.com/boards, and navigate to the appropriate page for this board. A PCI Express demonstration is also available on-line, including a GUI and drivers for a PCI Express solution using this board. Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development. However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout in the user's application may significantly affect circuit performance and reliability. Figure 2. Evaluation Board Block Diagram

Gennum SMPTE Board

One 3G Quad (4 channels) One 6G Dual (2 channels)

BNC Connector

SMAs

PCIe Card Edge Fingers

LatticeSC 1152 fcBGA PCIe x8

DDR2 Memory 84 fBGA

Note: This board not included with Evaluation Kit.

3

LVDS SMAs 4-bit Input/Output

LVDS Bus Loop

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

LatticeSC Device This board features a LatticeSC FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeSC devices in the 1152-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeSC Family Data Sheet on the Lattice web site at www.latticesemi.com. Note: The connections referenced in this document refer to the LFSCM3GA80 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family.

Applying Power to the Board The LatticeSC PCI Express x8 Evaluation Board is ready to power on. The evaluation board can be supplied with power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a benchtop supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board. To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord to J3 and plug the wall transformer into an AC wall outlet.

Power Supplies (see Appendix A, Figure 4) The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is provided to use with a bench-top supply adjusted to provide a nominal 12V DC. All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs to indicate power GOOD status of the intermediate supplies Table 1. Board Power Supply Fuses- (see Appendix A, Figure 4) F1

1.0V/1.2V Fuse

F2

3.3V Fuse

F3

1.5V Fuse

F4

1.2V Fuse

F5

2.5V Fuse

F6

1.8V Fuse

Table 2. Board Power Supply Indicators- (see Appendix A, Figure 4) D14

1.0V/1.2V VCC Core Source Good Indicator

D15

1.5V Source Good Indicator

D16

1.8V Source Good Indicator

D12

2.5V Source Good Indicator

D13

3.3V Source Good Indicator

D17

1.2V Source Good Indicator

Alternatively, external power can be connected rather than the wall transformer power pack. Table 3. Board Supply Disconnects- (see Appendix A, Figure 3) TB1

Screw terminal for 12V DC Pin1(square PCB pad) -> +12V DC Pin2 -> Ground

4

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor PCI Express Power Interface (see Appendix A, Figure 5)

Power can be sourced to the board via the PCB Edge Finger (CN1). This interface allows the user to provide power from a PCI Express host board.

Programming/FPGA Configuration (see Appendix A, Figure 2) A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port. Note: An ispDOWNLOAD® Cable is included with each ispLEVER® design tool shipment. Cables may also be purchased separately from Lattice.

ispVM Download Interface J2 is a10-pin JTAG connector used in conjunction with the ispVM System software and ispDOWNLOAD Cable to program and control the device. Table 4. JTAG Programming Connector (see Appendix A, Figure 2) Pin 1

VCC

Pin 2

TDO

Pin 3

TDI

Pin 4

PROGRAMN

Pin 5

NC

Pin 6

TMS

Pin 7

GND

Pin 8

TCK

Pin 9

DONE

Pin 10

INITN

Programming Daisy Chain This board includes two Lattice programmable devices that can be programmed in a daisy chain. A jumper setting of J93 controls the chain. Both devices are in the programming chain from the JTAG header J2 with jumpers across Pins{1-2} and Pins{3-4}. If the user desires to only program U1, only a jumper should be across Pins{2-4}.

Download Procedures Requirements • PC with ispVM System v.14.3 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System set-up. • ispDOWNLOAD Cable (HW-USBN-2A, HW-DLN-3C, etc.) JTAG Download The LatticeSC device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion. 1. Connect the ispDOWNLOAD cable to the appropriate header. J2 is used for the 1x10 cable. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any

5

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and render the board inoperable. 2. Connect the LatticeSC Evaluation Board to the appropriate power sources and power up the board. 3. Start the ispVM System software. 4. Press the SCAN button located in the toolbar. The LatticeSC device should be automatically detected. Figure 3. ispVM Main Window

5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.

6

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor Figure 4. Device Information Dialog Box

6. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational. Configuration Status Indicators (see Appendix A, Figure 2) These LEDs indicate the status of configuration to the FPGA. • D1 illuminated (red) – This indicates that the programming was aborted or reinitialized driving the INITN output low. • D4 illuminated (green) – This indicates the successful completion of configuration by releasing the open collector DONE output pin. • D11 illuminated (green) – Flashes to indicate TDI activity. • D21 illuminated (red) – This indicates that PROGRAMN is low. • D23 illuminated (red) – This indicates that GSRN is low. PROGRAMN & RESETN (see Appendix A, Figure 2) These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW5) and RESETN (SW4). Depressing the button drives a logic level “0” to the device.

7

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor MODE [3:0] (see Appendix A, Figure 2)

The FPGA MODE pins are preset on the board for SPI03 programming mode. JTAG programming is independent of the MODE pins and is always available to the user On-Board Flash Memory (see Appendix A, Figure 2) Three memory devices (U2, U3 and U22) are on board for non-volatile configuration memory storage. SW3 is used to control writing and reading from the memory. U2 and U3 are 4M 8-pin SOIC Flash devices and U22 is a 64M 16pin TSSOP Flash device. U22 is located on the bottom side (secondary) of the PCB. U2 and U22 occupy the same connections. Therefore, they can not be populated simultaneously. U22 is typically installed at assembly. Refer to Lattice technical note TN1100, SPI Serial Flash Programming Using ispJTAG on LatticeSC FPGAs for recommended procedures and software usage. To use both SPI Flash devices to program the LatticeSC device, the user must write to the Flash devices individually. This is accomplished by setting SW3 accordingly. Writing to Flash #1 (U2), close 3 and 5 switch positions (ON) and open all others. Writing to Flash #2 (U3), close 2 and 4 switch positions (ON) and open all others. For reading from the Flash devices individually, use the same switch settings as described for writing. For reading from both Flash devices in a cascading format, close switch positions (1, 3, 4, 5, 8).

FPGA Clock Management (see Appendix A, Figure 9) The evaluation board includes various features for generating and managing on-board clocks. The clocks are generated from either input provided from SMAs (see Table 5) or from crystal oscillators (Y1 and Y3. Y1 is socketed for interchangeability and Y3 is a 312.5MHz surface-mount with an enable/disable jumper J101). Both of these input clock sources are routed through the Lattice ispClock5620A Programmable Clock Management devices (U21). These clock management devices allow for clock synthesis and buffering. Table 5. Reference Clock Input SMA Connections J91

U21 Reference + Input

J92

U21 Reference - Input

U21 are Lattice ispClock5620A In-System-Programmable analog circuits. These devices allow designers to implement clock distribution networks supporting multiple synchronized output frequencies using a single integrated circuit. By integrating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620A can derive up to five separate output frequencies from a single input reference frequency. The PAC-Designer® software (available from the Lattice web site at www.latticesemi.com) is used to program the ispClock features. ispClock supports reference clocks in the range of 10 to 320 MHz. The duty cycle of the clock source need not be 50%; the only requirement is that both the HIGH and LOW times of this signal must be 1.25ns or longer. The following standards are supported with either minimal or no external components: LVTTL / LVCMOS / SSTL2 / SSTL3 / HSTL / LVDS / LVPECL. When the ispClock5620A is in a LOCKED state, the LOCK output pin goes LOW. The LOCKN pins are connected to amber LED D21 and will illuminate when the LOCKN pin goes low. The lock detector has two operating modes; phase lock mode and frequency lock mode. In phase-lock mode, the LOCK signal is asserted if the phases of the reference and feedback signals match, whereas in frequency-lock mode the LOCK signal is asserted when the frequencies of the feedback and reference signals match. 8

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

U21 is controlled by SW8 or from predefined connection to U1(LatticeSC). The DIP switch controls the ispClock device. The reference clock selection and device reset is controlled using the switches. The switches control the ispClock outputs can be synchronously controlled by the SGATE output on a bank-by-bank basis or tri-stated on an output-by-output basis using the OEXb and OEYb inputs. All outputs may be tri-stated by bringing the GOEb input high. The VCCO voltage is board connected to 2.5V or 3.3V, based on the on-board connection of FB21 or FB22. The output clocks of U21 are routed to devices to provide system level clocking. These pre-defined board clocks are routed to input LatticeSC input clock pins for SERDES reference clocks, primary clocks, PLL inputs and DLL inputs as well as connection to an SMA (J99). This SMA is 50-ohm terminated for off-board interconnection to test equipment. A 100.0MHz surface-mounted oscillator (Y2) is also provided and fanned-out to four general-purpose FPGA inputs. A clock input to the ispClock device can be provided from the PCI Express Edge Fingers. This is accomplished by configuring the on-board resistor jumpers R181, R182, R183, R184 (see Appendix A, Figure 9).

SERDES (see Appendix A, Figure 5)

SERDES Reference Clock The 50-ohm terminated SMA connectors provide the supply reference clocks directly to the LatticeSC device from the ispClock management device. This device with drive clocks to both SERDES quads via 100-ohm LVDS signaling. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same SERDES reference clocks.

SERDES Channels Surface Mounted SMA Connections (see Appendix A, Figure 5) DC coupled top-mounted SMA connectors connect to the SERDES Tx and Rx channels of Quad B SERDES on the left side (PCS 361). These pins are directly coupled to the designated SMA connector creating a path for both input and output differential data.

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LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

Table 6. SERDES Connectors (see Appendix A, Figure 5) J11

B_HDINN0_L

J6

B_HDINP0_L

J20

B_HDINN1_L

J16

B_HDINP1_L

J27

B_HDINN2_L

J23

B_HDINP2_L

J31

B_HDINN3_L

J28

B_HDINP3_L

J10

B_HDOUTN0_L

J5

B_HDOUTP0_L

J19

B_HDOUTN1_L

J15

B_HDOUTP1_L

J26

B_HDOUTN2_L

J22

B_HDOUTP2_L

J30

B_HDOUTN3_L

J28

B_HDOUTP3_L

Edge Launched SMA Connections (see Appendix A, Figure 5) DC coupled high-performance edge-launch SMA connectors connect to the SERDES Tx and Rx channels of Quad A SERDES on the left side (PCS 360). These pins are directly coupled to the designated SMA connector, creating a path for both input and output differential data. Table 7. SERDES Connectors (see Appendix A, Figure 5) J12

A_HDINN0_L

J7

A_HDINP0_L

J24

A_HDINN3_L

J17

A_HDINP3_L

J13

A_HDOUTN0_L

J8

A_HDOUTP0_L

J25

A_HDOUTN3_L

J18

A_HDOUTP3_L

SERDES SMPTE Channels (see Appendix A, Figure 5) A single-channel 75-ohm SERDES channel is connected to BNC edge connectors. These connections are provided to connect to SMPTE video equipment. The channels include the appropriate passive components for interoperability to SMPTE devices.

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LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

Table 8. SERDES SMPTE BNC Connectors (see Appendix A, Figure 5) J9

A_HDINN1_L

J4

A_HDINP1_L

J21

A_HDOUTN1_L

J14

A_HDOUTP1_L

SERDES PCI Express Channels (see Appendix A, Figure 5) This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1) to fit directly into an x8 host receptacle. Power can be supplied directly from the PCI Express host via the edge-finger connections. FPGA Test Pins (see Appendix A, Figure 7) General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS designated according to the following table. Table 9. FPGA Test Pins (see Appendix A, Figure 7) Switch

BGA

Netname

LED

BGA

SW2D

A20

Switch1

D2

A19

RED1

SW2C

K22

Switch2

D5

J21

YELLOW1

SW2B

K21

Switch3

D7

H21

GREEN1

SW2A

G20

Switch4

D9

B18

BLUE1

SW1D

F20

Switch5

D3

A18

RED2

SW1C

J22

Switch6

D6

H20

YELLOW2

SW1B

H22

Switch7

D8

H19

GREEN2

SW1A

B19

Switch8

D10

E19

BLUE2

NetName

Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be programmed on FPGA output pins.

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LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor 17-Segment LED Display (see Appendix A, Figure 7)

General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins can be driven low to illuminate the display segments. Table 10. 17-Segment LED Display Segment

BGA

A

AC33

B

AA30

C

AD34

D

AA28

E

AA33

F

AB34

G

AA29

H

Y31

K

Y32

M

W24

N

W33

P

Y34

R

W26

S

V34

T

W25

U

U33

DP

Y27

A

H

B

K M N U

G

P

T S F

C

R

E

D DP

Test SMA Connections General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit the evaluation of several FPGA I/O buffer types. The use of several termination schemes permits easy interfaces for each buffer type. Table 11. FPGA I/O Test SMA Connectors SMA Designation

Name

1152 BGA

LFSC80 Signal

Termination Description

Termination Resistor(s)

See Appendix A, Figure 7 J36

LVDS_INP0

PL22A

E34

DC-Coupled

n/a

J38

LVDS_INN0

PL22B

F34

DC-Coupled

n/a

J33

LVDS_INP1

PL24A

F33

DC-Coupled

n/a

J35

LVDS_INN1

PL24B

G33

DC-Coupled

n/a

J40

LVDS_INP2

PL25A

K30

DC-Coupled

n/a

J42

LVDS_INN2

PL25B

L30

DC-Coupled

n/a

J44

LVDS_INP3

PL26A

G34

DC-Coupled

n/a

J46

LVDS_INN3

PL26B

H34

DC-Coupled

n/a

J37

LVDS_OUTP0

PL17A

F31

100-ohm Differential Termination

J32

LVDS_OUTN0

PL17B

G31

100-ohm Differential Termination

J34

LVDS_OUTP1

PL18A

D33

100-ohm Differential Termination

J39

LVDS_OUTN1

PL18B

E33

100-ohm Differential Termination

J41

LVDS_OUTP2

PL20A

F32

100-ohm Differential Termination

12

R114 R116 R117

LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor Table 11. FPGA I/O Test SMA Connectors (Continued) SMA Designation

Name

1152 BGA

LFSC80 Signal

Termination Description

J43

LVDS_OUTN2

PL20B

G32

100-ohm Differential Termination

J45

LVDS_OUTP3

PL21A

H30

100-ohm Differential Termination

J47

LVDS_OUTN3

PL21B

J30

100-ohm Differential Termination

Termination Resistor(s) R118

See Appendix A, Figure 8 J48

URC_PLLT

PR16A/URC_PLLC_IN_A

F5

50-ohm Ground Termination

R166

J49

URC_PLLC

PR16B/URC_PLLT_IN_A

G5

50-ohm Ground Termination

R167

J50

PCLKT3_1

PR50C

U6

50-ohm Ground Termination

R168

J51

PCLKC3_1

PR50D

V6

50-ohm Ground Termination

R169

High Speed Test Point DP1 (see Appendix A, Figure 7) General-purpose FPGA pins are available via a differential test pad. These connections allow a high-impedance probe to measure the performance of a coupled- differential output buffer pair.

DDR2 Memory U18 (see Appendix A, Figure 10) The LatticeSC Evaluation Board is equipped with an 84-BGA DDR2 SDRAM memory device such as a Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation board includes termination of address and command signals. It includes all power and external components needed to demonstrate the memory controller of the LatticeSC device.

Ordering Information Ordering Part Number

Description LatticeSC PCI Express x8 Evaluation Board

LFSC80E-P8-EV

Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com

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China RoHS Environment-Friendly Use Period (EFUP)

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LatticeSC PCI Express x8 Evaluation Board User’s Guide

Lattice Semiconductor

Revision History Date

Version

October 2006

01.0

Change Summary Initial release.

December 2006

01.1

Includes new SERDES schematic in Appendix A.

March 2007

01.2

Added Ordering Information section.

April 2007

01.3

Minor text changes to On-Board Flash Memory section. Added important information for proper connection of ispDOWNLOAD (Programming) Cables.

© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Title

Cover Page S he e t

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of

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R ev 2.0

C

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D a te :

S iz e C

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SC PCI EXPRESS Card

P roje c t

A

1

A

4

2

Board will meet PCI Express Electromechanical Specification Rev 1.0 Add-in card form factor for standard height and full length 4.376" Height x 9.5" Length

3

B

5

LatticeSC-1152BGA x8 PCI Express Platform Evaluation Board

4

B

C

D

5

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Appendix A. Schematics Figure 5.

A

B

C

C1

R35

C2

2_5V

R67 4_7K-0603SMT

[5] PCIE_PERSTN

10NF-0603SMT

R25 10K-0603SMT

SCSN_0 Q_0

R161 4_7K-0603SMT

0R-0603SMT

R41

5

GSRN

SW5

6

3

2Y

1Y

U2

CK D DU8 DU7 DU6 DU5 VSS W#

3

3

5

4

2

1

3

1

Q_1 3_3V

SCSN Q_0

OUT2

OUT1

MAX6817

IN2

IN1

U4

FLASH_DIS

4

6

3_3V 3_3V

2_5V

2_5V

SPI3 MODE SETTING

PP11

1

4

LED-SMT1206_RED D23

680R-0603SMT R170

2

2_5V

U1F

7

7

Q3 2N2222/SOT23

D4

1

R

D1

R11 10K-0603SMT

LED-SMT1206_RED

DONE

INITN

2_5V

3

G21 F21 M19 M20 E21 D21 K19 L19 E20 D20 L20 L21 B20 A20 K22 K21 G20 F20 J22 H22 B19 A19 J21 H21 B18 A18 H20 H19 E19 D19 L18 K18 C19 C20 J19 J18 F18 E18 H18 G18 B17 A17 H17 G17 F17 E17 L17 C16 C15 H16 H15 E16 D16 J17 J16 E15 D15 H13 J13 B16 H14 J14 K14 F15 G15 K16 E14 L14 L15 F14 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 RED1 YELLOW1 GREEN1 BLUE1 RED2 YELLOW2 GREEN2 BLUE2

BLUE2

470R 9 RN1H 8 EXB2HV471JV

2_5V

OSC_IN_4 [9]

PLL_BYPASS [9] PS0 [9] PS1 [9] GOE [9] SGATE [9] REFSEL [9] OEX [9] OEY [9] ISPCLK_RST [9] ISPCLK_LOCK [9] PCIE_SMCLK [5] PCIE_SMDAT [5] PCIE_WAKEN [5]

GREEN2

470R 10 RN1G 7 EXB2HV471JV

470R

YELLOW2

470R 6 11 RN1F EXB2HV471JV

5 12 RN1E EXB2HV471JV RED2

BLUE1

470R 4 13 RN1D EXB2HV471JV 470R

GREEN1

YELLOW1

RED1

470R 3 14 RN1C EXB2HV471JV

2 15 RN1B EXB2HV471JV

470R

1 16 RN1A EXB2HV471JV

PT51A/D15 PT51B/A21 PT51C/DP1 PT51D/D14 PT52A/MPITEAN PT52B/A18 PT52C/A20 PT52D/A19 PT53A/A17 PT53B/A15 PT53C/D13 PT53D/A16 PT55A/A14 PT55B/A13 PT55C/D12 PT55D/D11 PT56A/A12 PT56B/A11 PT56C/D31/PCLKT1_7 PT56D/D30/PCLKC1_7 PT57A/A10 PT57B/A9 PT57C/D29/PCLKT1_6 PT57D/D28/PCLKC1_6 PT59A/A8 PT59B/A7 PT59C/VREF1_1 PT59D/D27 PT60A/A6 PT60B/A5 PT60C/D26/PCLKT1_5 PT60D/D25/PCLKC1_5 PT61A/A4 PT61B/A3 PT61C/A2 PT61D/A1 PT63A/A0 PT63B/MPIRTRYN PT63C/D24/PCLKT1_4 PT63D/DP3/PCLKC1_4 PT65A/MPICLK/PCLKT1_0 PT65B/PCLKC1_0 PT65C/DP2 PT65D/D23 PT66A/MPIACKN PT66B/DP0 PT66D/EXTDONEO PT67A/EXTCLKP2I PT67B/EXTCLKP2O PT67C/D22/PCLKT1_1 PT67D/D21/PCLKC1_1 PT69A/EXTCLKP1I PT69B/EXTCLKP1O PT69C/D20/PCLKT1_2 PT69D/D19/PCLKC1_2 PT70A/EXTDONEI PT70B/DOUT PT70C/D18 PT70D/VREF2_1 PT71A/QOUT PT71C/D17/PCLKT1_3 PT71D/D16/PCLKC1_3 PT73D/D4 PT74A/D5 PT74B/D6 PT74C/D7 PT75A/RDN PT75C/D10 PT75D/D9 PT77B/D8

INITN indicator will light if an error occurs during configuration programming

R4 680R-0603SMT

2_5V

CONFIG/TOP

LFSC1152BGA

1 SW1A SWITCH8

1 SW2A SWITCH4 3 SW2B SWITCH3

12

4 SW2C SWITCH2

10

6 SW2D SWITCH1

9

12 3 SW1B SWITCH7 4 SW1C SWITCH6

10

6 SW1D SWITCH5

9

LFSC 1152BGA

PT71B/D0 PT73A/D1 PT73B/D2 PT73C/D3

TCK TDI TDO TMS RESETN PROGRAMN

PT74D/WRN PT75B/CS0N PT77A/CS1 PT77C/LDCN PT77D/HDC PT66C/RDY

M0 M1 M2 M3 INITN DONE CCLK

RDCFGN MPIIRQN

DONE indicator will light when configuration is successfully completed

LED-SMT1206_RED D21

680R-0603SMT R162

A16 A15 B15 K13

D1 C1 M9 L9 B33 J8

TCK TDI_SC TDO_SC TMS GSRN PROGRAMN DATA0 DATA1

L16 D14 G14 M16 M15 K17

J27 K27 M26 L26 C33 D34 B2

C34 K8

WRN CS0N CS1 SCSN SI SCK

INITN DONE

R17 470R-0603SMT M3

3_3V

FLASH_DIS

3_3V

SN74LVC125A/SO14

2A

2OE_N

1A

1OE_N

U6A

8 7 6 5

16 15 14 13 12 11 10 9

8 7 6 5

20 19 18 17 16 15 14 13 12 11

3_3V

M25P80-FLASH

S# VCC Q HOLD# W# CLK GND DI

U3

FLASH1

M25P64-FLASH

HOLD# VCC DU1 DU2 DU3 DU4 S# Q

U22

M25P80-FLASH

S# VCC Q HOLD# W# CLK GND DI

4 2 Momentary Switch B3F-1150

1

PROGRAMN

PROGRAMN

R36

1 2 3 4

1 2 3 4 5 6 7 8

1 2 3 4

FLASH0

TDA10H0SK1

2 4 Momentary Switch B3F-1150

1

FPGA RESETN/GSRN

SCSN_1 Q_1 WRITE_PROT_N

SW4

FLASH_DIS

WRITE_PROT_N

3_3V

SCSN_0 Q_0 WRITE_PROT_N

DATA1

20 19 18 17 16 15 14 13 12 11

C3

3_3V

100NF-0603SMT

10 9 8 7 6 5 4 3 2 1

R33

R21 4_7K-0603SMT

SW3

4_7K-0603SMT

R160 4_7K-0603SMT

4_7K-0603SMT

5 VCC

10 9 8 7 6 5 4 3 2 1

R37

100NF-0603SMT

R16 10K-0603SMT

GND 2

R38 100R-0603SMT

R31 4_7K-0603SMT

R18 4_7K-0603SMT M2

WRITE_PROT_N FLASH_DIS CS0N CS1 WRN SCSN_0 SCSN_1 DATA0

100R-0603SMT

R26 10K-0603SMT R32 4_7K-0603SMT

R19 470R-0603SMT M1 Y

R22 4_7K-0603SMT

1 0

8

1 0

11

1 0

11

1 0

5 1 0

1 0

2

1 0

2

D

4_7K-0603SMT

Y GSRN

R20 4_7K-0603SMT M0 PROGRAMN

4_7K-0603SMT R30

GND

7

R15 680R-0603SMT

R12 680R-0603SMT

R10 680R-0603SMT

4.7K

TDO_SC LOCAL_TDO

EXBV8V472JV

2

RED1

RN2A

4.7K

1

1

1 3

2

2

HEADER 2X2

2 4

J93

JUMPER1

J94 JUMPER1

J95

4.7K

4.7K

2

TCK

[9]

TDI_ISPCLK [9] TDO_ISPCLK [9]

TMS

[9]

4

6

OUT Y2

OUT Y1

6

4

TMS

TCK

OUT Y2

OUT Y1

3_3V

10 7 1 EXB2HV103JV 10K

RN2G

NC7WZ16-MACO6A/Fairchild TinyLogic

R34 220R-0603SMT

D11 LED-SMT1206_GREEN

This LED indicates activity on TDI.

TDI_SC

BLUE2

3_3V

IN A2

IN A1

U5

U7

IN A2

IN A1

3

1

Q8 2N2222/SOT23

D a te :

S iz e C

Title

3

1

LOCAL_TMS LOCAL_TCK DONE INITN

LOCAL_TDO LOCAL_TDI PROGRAMN

J2

SC PCI EXPRESS Card 1

VCC

INITN GND

DONE

TCK

TMS

NC

ispEN_N

TDI

TDO

S he e t

HEADER 10

2 3 4 5 6 8 9 10

Configuration/Testpoints P roje c t

LED-SMT1206_BLUE D10

7

1

2

of

FROM ISPVM CABLE

8 91 EXB2HV103JV 10K

RN2H

LED-SMT1206_GREEN D8

3_3V

Q9 2N2222/SOT23

12_0V R28

6 11 1 EXB2HV103JV 10K

RN2F

LED-SMT1206_YELLOW D6

Q7 2N2222/SOT23

12_0V

470R-1206SMT

R24

470R-1206SMT LED-SMT1206_BLUE D9

GREEN2

RN2D

4 13 1 EXB2HV103JV 10K

LED-SMT1206_RED D3

Q5 2N2222/SOT23

12_0V

470R-1206SMT

R14

15 1 2 EXB2HV103JV 10K

RN2B

Q2 2N2222/SOT23

12_0V

470R-1206SMT

R2

R27

12_0V

Q6 2N2222/SOT23

LED-SMT1206_GREEN D7

YELLOW2

RED2

1

470R-1206SMT

5 12 1 EXB2HV103JV 10K

RN2E

LED-SMT1206_YELLOW D5

Q4 2N2222/SOT23

12_0V

470R-1206SMT

R23

3 14 1 EXB2HV103JV 10K

RN2C

NC7WZ16-MACO6A/Fairchild TinyLogic

BLUE1

GREEN1

YELLOW1

12_0V

470R-1206SMT

R13

1 16 1 EXB2HV103JV 10K

LED-SMT1206_RED D2

Q1 2N2222/SOT23

12_0V

470R-1206SMT

R1

R9 680R-0603SMT

RN3D

R8 680R-0603SMT

R7 680R-0603SMT

R5 680R-0603SMT

R3 680R-0603SMT

RN3B

1 0 R6

RN3C

8 LED-SMT1206_GREEN

1 RN3A

5 220R-0603SMT G

3 2

R

2 Y

3 2 G

3 2 B

2_5V

R56 4_7K-0603SMT

2 7

TCK

3 6

TMS

8

TDO_SC

4 TDI_SC

5

R

3 5

3

C4 100NF-0603SMT

3 2 C7

VCC GND 2 5 VCC GND 2

100NF-0603SMT

2_5V

R29

4

4_7K-0603SMT

R

3 2 Y

3 2 G

3 2 B

3 2

16

10

C6

5

R ev 2.0

100NF-0603SMT

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 6. Configuration/Testpoints

A

B

C

2_5V

R39

100NF-0603SMT

+

C42

MC_VREF_REG

1_8V

C12

C36

100NF-0603SMT C13

C10

4

2

1UF-16V-0805SMT

VREF

SD

VDDQ

C37

SC_VTT

LP2996-SO8

5

U8

C38

VTT

VSENSE

C43

C29

8

3

+ C47

3_3V

C48

+

C41

C44

C22

C23 +

0.9V VTT PROBE POINT

C213

C214

C215

C216

C217

C218 C219

PP3

C220

C221

TP4

C460

C459

C456

C457

C458 C454

C453

C455

C452

5

10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT

C451

100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT

C212

VCC_CORE

SC_VTT

PP13

VCCAUX PROBE POINT

R40 0R-0603SMT

+ C40

2_5V

22UF-16V_TANTBSMT

1 1UF-16V-0805SMT 2

100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT

C35

[6] MC_VREF_REG

4_7K-0603SMT

47UF-16V_TANTBSMT

C11

1_8V

6 7

AVIN PVIN

GND

1

D

4

PP7

AB22 AB13 AA21 AA18 AA19 AA16 AA17 AA14 V21 Y20 Y18 Y17 Y15 V14 W21 W19 W16 W14 V20 V18 V17 V15 U20 U18 U17 U15 T21 T19 T16 T14 U21 R20 R18 R17 R15 U14 P21 P18 P19 P16 P17 P14 N22 N13

VCC_CORE U1J

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC LFSC1152BGA

VCC CORE

LFSC 1152BGA

LFSC1152BGA

SUPPLIES

LFSC 1152BGA

1_8V

C444

C443

C278

C279

C280

C281

C282

C283

C284

C285

C286

C485

C484

C486

C479

C482

C483

C481

C480

C494

C493

C495 C488

C491

C492 C490

C489

+ C30

1_5V

+ C39

2_5V

VDDTX

VDDRX

VDDP

1_5V

C34

C31

F29 F6 F28 F7 F27 F8 F26 F9 H25 H10 C32 C3 C29 C6 C28 C7 C25 C10 E30 E5 E29 E6 E28 E7 E27 E8 M23 M12 A_VDDOB0_L A_VDDOB0_R A_VDDOB1_L A_VDDOB1_R A_VDDOB2_L A_VDDOB2_R A_VDDOB3_L A_VDDOB3_R A_VDDP_L A_VDDP_R A_VDDRX0_L A_VDDRX0_R A_VDDRX1_L A_VDDRX1_R A_VDDRX2_L A_VDDRX2_R A_VDDRX3_L A_VDDRX3_R A_VDDTX0_L A_VDDTX0_R A_VDDTX1_L A_VDDTX1_R A_VDDTX2_L A_VDDTX2_R A_VDDTX3_L A_VDDTX3_R VDDAX25_L VDDAX25_R

U1B

3

VDDAX25 PROBE POINT

PP5

VDDIB PROBE POINT

PP8

ANALOG POWER

LFSC 1152BGA

100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT

C496

10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT

C487

100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT

22UF-16V_TANTBSMT

22UF-16V_TANTBSMT

22UF-16V_TANTBSMT

C446

100NF-0603SMT

C239

VDDRX

100NF-0603SMT

C240

VDDTX

C16

C467

C26

C17

10NF-0603SMT

C241

10NF-0603SMT

C243

10NF-0603SMT

C21

100NF-0603SMT

C469

VDDP

C15

C28

100NF-0603SMT

C242

100NF-0603SMT

C463

100NF-0603SMT

C468

C27

C18

C25

10NF-0603SMT

C244

10NF-0603SMT

C461

10NF-0603SMT

C465

2

2

100NF-0603SMT

C245

100NF-0603SMT

C462

100NF-0603SMT

C466

D25 D10 D24 D11 D23 D12 D22 D13 L22 L13 G25 G10 G24 G11 G23 G12 G22 G13 K25 K10 L25 L10 K24 K11 L24 L11

PP4

C464

VDDTX

VDDRX

VDDP

1_5V

10NF-0603SMT

C246

10NF-0603SMT

C247

10NF-0603SMT

VDDOB PROBE POINT

B_VDDOB0_L B_VDDOB0_R B_VDDOB1_L B_VDDOB1_R B_VDDOB2_L B_VDDOB2_R B_VDDOB3_L B_VDDOB3_R B_VDDP_L B_VDDP_R B_VDDRX0_L B_VDDRX0_R B_VDDRX1_L B_VDDRX1_R B_VDDRX2_L B_VDDRX2_R B_VDDRX3_L B_VDDRX3_R B_VDDTX0_L B_VDDTX0_R B_VDDTX1_L B_VDDTX1_R B_VDDTX2_L B_VDDTX2_R B_VDDTX3_L B_VDDTX3_R

22UF-16V_TANTBSMT

LFSC1152BGA

+ C24

A_VDDIB0_L

C14 100NF-0603SMT 100UF-FKSMT

C445

A_VDDIB1_L

D32

1UF-16V-0805SMT C49 1UF-16V-0805SMT

C442

A_VDDIB2_L

D31

1

C449

A_VDDIB3_L

D30

1UF-16V-0805SMT

C447

B_VDDIB0_L

D29

100NF-0603SMT

C448

B_VDDIB1_L

D28

2 10UF-16V_TANTBSMT

C450

B_VDDIB2_L

D27

1 2 R43 1K-0603SMT TP1 1 TP2 1 TP3 1 1

10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT

B_VDDIB3_L

D26

U1H

VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCJ VTT_2 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 XRES PROBE_VCC PROBE_GND TEMP

1UF-16V-0805SMT

N14 P13 AA13 AB14 AB21 AA22 P22 N21 AB20 AB15 Y22 Y13 R22 R13 N20 N15 M21 M22 N23 P23 T22 U22 V23 V22 W22 AA23 AB23 AC23 AC22 AC21 AB19 AB18 AC17 AB17 AB16 AC14 AC13 AC12 AB12 AA12 W13 V13 U13 T13 U12 P12 N12 M14 M13 M18 N19 N18 N17 N16 C2 N11 R12 T12 W12 Y12 AB11 AD13 AC15 AC16 AC19 AC20 AD22 AB24 W23 Y23 N24 R23 T23 AF28 AF7 AF8 AF27 A_VDDIB0_R D3

E26

PP9

A_VDDIB1_R D4

VCC12 PROBE POINT

A_VDDIB2_R D5 100NF-0603SMT

C54

A_VDDIB3_R D6

100NF-0603SMT

2_5V

+ C19

1_8V

1

PP2

1

C9

1_2V FB3

D a te :

S iz e C

Title

+ C51

VDDRX

+ C45

VDDTX

+ C32

VDDP

D17 C18 F16 G19 K12 K15 J20 L23 J9 J25 E3 G6 H4 K7 L3 M11 N6 P4 R9 T7 U3 V4 W6 Y10 AA3 AB7 AC10 AD4 AE6 AG3 AK4 AF9 AD12 AF15 AJ7 AH10 AJ13 AH16 AM5 AL8 AM11 AL14 AM17 AE20 AE23 AE26 AJ19 AH22 AJ25 AH28 AL18 AM21 AL24 AM27 AL30 AK32 AG31 AE28 AD32 AC24 AB29 AA31 Y26 W28 V32 U31 T29 R25 P32 N28 M25 L31 K29 H32 G28 E31

U1I

C46

C52

C33

VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7

1

S he e t

3

PP12

of

10

VDDRX PROBE POINT

PP10

VDDTX PROBE POINT

PP6

VDDP PROBE POINT

LFSC1152BGA

VCCIO

LFSC 1152BGA

1

SC PCI EXPRESS Card

P roje c t

Power Supplies

BLM41PG600SN1

FB7

BLM41PG600SN1

FB5

BLM41PG600SN1

C20

1.8V PROBE POINT

2

+ C8

PP1

2.5V PROBE POINT

2

22UF-16V_TANTBSMT

3

B_VDDIB0_R D7

100NF-0603SMT

+ C53

22UF-16V_TANTBSMT

B_VDDIB1_R D8

100NF-0603SMT

D9

100NF-0603SMT

B_VDDIB2_R 100NF-0603SMT

B_VDDIB3_R E9 100NF-0603SMT

1 2

2_5V

1UF-16V-0805SMT

1UF-16V-0805SMT 1UF-16V-0805SMT

4

22UF-16V_TANTBSMT

1_2V

1 2

1 2

100NF-0603SMT

5

1UF-16V-0805SMT

1 2

1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT

22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT

1 2 1 2 1

17

2

R ev 2.0

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 7. Power Supplies

A

B

C

R163 0R-0805SMT

C70 10UF-16V_TANTBSMT

3_3VIN

1

1

1

1

1

R164 0R-0805SMT

TP15

TP13

TP11

TP9

TP7

1

C63 10UF-16V_TANTBSMT

3_3VIN

TESTPOINT

TESTPOINT

TESTPOINT

TESTPOINT

TESTPOINT

TESTPOINT

TP5

5

1

TP16

1

TP14

1

TP12

1

TP10

1

TP8

1

TP6

TESTPOINT

TESTPOINT

TESTPOINT

TESTPOINT

TESTPOINT

TESTPOINT

GND Pads Distributed around the board

C73

2

4

5

100NF-0603SMT

R75

1

3

1.8V

1_8V

C74 22UF-16V_TANTBSMT

124R-0603SMT

BOURNS-3224W-5K

R101

AMS1503CT

OUTPUT VCONTROL SENSE ADJUST_GND

R68

1

1_5V

C66

C75

4

R77 OPEN-0805SMT

1

2

1

2

U10

U14

12_0V

12_0V

Q12 2N2222/SOT23

R165 OPEN-0805SMT

R52 1 10K-0603SMT

GND

VIN

GND

VIN

R53 1 10K-0603SMT

LED-SMT1206_GREEN D16 1_8V

1. 8V

R46 470R-1206SMT

12_0V

PTH12060W

SENSE

PTH12060W

BOURNS-3224W-10K

R64

R59 0R-0603SMT

5

6

0R-0603SMT

R73

R81 OPEN-0603SMT

3

1.2V R71 100K-0603SMT

1_8K-0603SMT

R62

C71 10UF-16V_TANTBSMT

SENSE

VOUT

BOURNS-3224W-10K

R60

5

6

R55 100K-0603SMT

1_2V R54 1 10K-0603SMT

LED-SMT1206_GREEN D17

C58 10UF-16V_TANTBSMT

VOUT

Q13 2N2222/SOT23

1.2V

R47 470R-1206SMT

12_0V

POWER RAIL GOOD INDICATORS

LED-SMT1206_GREEN D15 1_5V

1.5V

R45 470R-1206SMT

F3 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse

F6 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse

124R-0603SMT C65 22UF-16V_TANTBSMT

BOURNS-3224W-2K

R78

AMS1503CT

3

VCC_CORE R51 Q11 1 10K-0603SMT 2N2222/SOT23

LED-SMT1206_GREEN D14

1.5V

Q10 2N2222/SOT23

OUTPUT VCONTROL SENSE ADJUST_GND

VPOWER

U12

VPOWER

U16

C64

2

4

5

R44

470R-1206SMT

VCC CORE

12_0V

3

3_3V

C60 10UF-16V_TANTBSMT

R48

D18 LED-SMT1206_GREEN

12V INPUT GOOD

12_0V

470R-1206SMT

2

12_0V

2

1

R74 OPEN-0805SMT

1

2

U15

12_0V

2

GND

VIN

OPEN-0805SMT

R63

3_3VIN

PTH12060W

1

2

U11

VOUT

GND

PTH03010W

VOUT

R65

5

6

0R-0603SMT

R72

R70 100K-0603SMT

2.5V

R79 2_2K-0603SMT

4.32K Typical

0R-0603SMT

D a te :

S iz e C

Title

1 3

SET VALUE 1V= 36.5K 1.2V=17.4K

330UF-FKSMT

C62 +

DC/DC Conversion

1

SC PCI EXPRESS Card

P roje c t

J3

1

12_0V

S he e t

R66 15K/SMT0603

4

JUMPER1

J98

R156 24K/SMT0603

1

2

F1 F1251CT-ND 10A Fast-Blo SMT Socketed Fuse

F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse

HEADER 3x1

1V ADJ 1.2V

J60

330UF-FKSMT

C69 +

2_5V

2

C61 10UF-16V_TANTBSMT

5

R61

R58 100K-0603SMT

VCC_CORE

100UF-FKSMT

+ C56

+ 470UF-FKSMT

12_0V

12_0V

6

C55

1

Male Power Jack 2.1mm 22HP037 3

POWER INPUT

SENSE

BOURNS-3224W-10K

C68 10UF-16V_TANTBSMT

SENSE

BOURNS-3224W-10K

R80

SC VCC_CORE

VIN

GND

+12VDC

Terminal Block/ED1202DS

TB1

VCC12 power supply must always be higher than VCC Core, or if lower, then well within 150mV of VCC Core

R50 150R-0603SMT

3.3V

D13

LED-SMT1206_GREEN

3_3V

F2 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse

F4 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse

330UF-FKSMT

C72 +

1_2V

330UF-FKSMT

C59 +

3_3VIN

3.3V

R49 100R-0603SMT

2. 5V

D12

LED-SMT1206_GREEN

2_5V

G

4

G

12_0V

R69

D

100NF-0603SMT

G

3 2 OPEN-0603SMT

2

5

R76

G

3 2

G

3 2

G

3

3_3K-0603SMT

INHIBIT# 3 10 MUP

2 100NF-0603SMT

8

INHIBIT#

100NF-0603SMT

10 MUP

9

3

INHIBIT# 3

MDWN ADJUST 4 3_3_TRIM

9 MDWN

8 TRACK

ADJUST 4

ADJUST 4

TRACK 7

1_2_TRIM

10 MUP INHIBIT# 3

GND

G

9 MDWN ADJUST 4

10 MUP

9 MDWN

8 TRACK

GND 7 CORE_TRIM

7 GND

8 TRACK

7 2_5_TRIM

18

GND

of

10

R ev 2.0

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 8. DC/DC Conversion

A

B

C

[8,9] [8,9]

PCIE_CLKP PCIE_CLKN

[2] PCIE_PERSTN

2 4 6

J96

2 4 6

x1 x4 x8

PRSNT1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# GND REFCLK+ REFCLKGND PERp0 PERn0 GND RSVD_A19 GND PERp1 PERn1 GND GND PERp2 PERn2 GND GND PERp3 PERn3 GND RSVD_A32 RSVD_A33 GND PERp4 PERn4 GND GND PERp5 PERn5 GND GND PERp6 PERn6 GND GND PERp7 PERn7 GND

CN1

+12V +12V RSVD_B3 GND SMCLK SMDAT GND +3.3V JTAG1 3.3Vaux WAKE# RSVD_B12 GND PETp0 PETn0 GND PRSNT3# GND PETp1 PETn1 GND GND PETp2 PETn2 GND GND PETp3 PETn3 GND RSVD_B30 PRSNT4# GND PETp4 PETn4 GND GND PETp5 PETn5 GND GND PETp6 PETn6 GND GND PETp7 PETn7 GND PRSNT2# GND

X8 PCIe Board Fingers

PCI Express x8 Edge Finger Conn.

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

R190 4_02K-0603SMT

PRSNT SELECT

HEADER 3X2

1 3 5

R189 4_02K-0603SMT

PETp3 PETn3

PETp2 PETn2

PETp1 PETn1

x8

PETp7 PETn7

PETp6 PETn6

PETp5 PETn5

PETp4 PETn4

x4

5

1

TP17 TESTPOINT

6G_360_OUTP1 6G_360_OUTN1 3G_361_INP0 3G_361_INN0 3G_361_INP1 3G_361_INN1 3G_361_INP2 3G_361_INN2 3G_361_INP3 3G_361_INN3 3G_361_OUTP0 3G_361_OUTN0 3G_361_OUTP1 3G_361_OUTN1 3G_361_OUTP2 3G_361_OUTN2 3G_361_OUTP3 3G_361_OUTN3

4

[9] A_RXREFCLK_L

[9] A_REFCLKN_R

[9] A_REFCLKP_R

[9] A_REFCLKN_L

[9] A_REFCLKP_L

100R-0603SMT

PCIE_WAKEN [2] PETp0 PETn0 x1

2

PCIE_SMCLK [2] PCIE_SMDAT [2]

JUMPER1

PCIE_3V3

1

J97

R92

C90 100NFX5R-0402SMT

100R-0603SMT

C88 100NFX5R-0402SMT

100R-0603SMT R91

B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM)

PERp7 PERn7

PERp6 PERn6

PERp5 PERn5

PERp4 PERn4

PERp3 PERn3

PERp2 PERn2

PERp1 PERn1

PERp0 PERn0

PCIE_CLKP PCIE_CLKN

PCIE_3V3

12_0V

A_RESP_L

1 3 5

R90

C85 100NFX5R-0402SMT

6G_360_INP1 6G_360_INN1 6G_360_OUTP0 6G_360_OUTN0 A_HDOUTP1_L A_HDOUTN1_L

U1A

SERDES

LFSC-1152BGA

R185

R187 R188

B_REFCLKN_R 100R-0603SMT

A_REFCLKN_R 100R-0603SMT

B_REFCLKN_L 100R-0603SMT

A_REFCLKN_L 100R-0603SMT

SMPTE_360_INN1

A_HDOUTP1_L

A_HDOUTN1_L

BNC-Trompeter/UCBBJE20-7

1

J21

BNC-Trompeter/UCBBJE20-7

1

J14

BNC-Trompeter/UCBBJE20-7

1

J9

A_HDINP1_L

A_HDINN1_L 0.018UF-0402SMT

C112

0.018UF-0402SMT

C111

VIDEO BNCs SMPTE_360_INP1

BNC-Trompeter/UCBBJE20-7

1

J4

LVDS Ref Clk Terminations Place close to U1

B_REFCLKP_R

A_REFCLKP_R

B_REFCLKP_L R186

B_REFCLKP_L

A_RXREFCLK_L A_REFCLKP_L

B_REFCLKN_L

B_REFCLKP_R

A_REFCLKP_R A_REFCLKN_R

B_REFCLKN_R

A_REFCLKN_L

A_REFCLKP_L

A_HDINP0_L A_HDINN0_L A_HDINP1_L A_HDINN1_L A_HDINP2_L A_HDINN2_L A_HDINP3_L A_HDINN3_L A_HDOUTP0_L A_HDOUTN0_L A_HDOUTP1_L A_HDOUTN1_L A_HDOUTP2_L A_HDOUTN2_L A_HDOUTP3_L A_HDOUTN3_L B_HDINP0_L B_HDINN0_L B_HDINP1_L B_HDINN1_L B_HDINP2_L B_HDINN2_L B_HDINP3_L B_HDINN3_L B_HDOUTP0_L B_HDOUTN0_L B_HDOUTP1_L B_HDOUTN1_L B_HDOUTP2_L B_HDOUTN2_L B_HDOUTP3_L B_HDOUTN3_L

3

LFSC1152BGA

A_HDINP0_R A_HDINN0_R A_HDINP1_R A_HDINN1_R A_HDINP2_R A_HDINN2_R A_HDINP3_R A_HDINN3_R A_HDOUTP0_R A_HDOUTN0_R A_HDOUTP1_R A_HDOUTN1_R A_HDOUTP2_R A_HDOUTN2_R A_HDOUTP3_R A_HDOUTN3_R B_HDINP0_R B_HDINN0_R B_HDINP1_R B_HDINN1_R B_HDINP2_R B_HDINN2_R B_HDINP3_R B_HDINN3_R B_HDOUTP0_R B_HDOUTN0_R B_HDOUTP1_R B_HDOUTN1_R B_HDOUTP2_R B_HDOUTN2_R B_HDOUTP3_R B_HDOUTN3_R

A_HDINP0_R A_HDINN0_R A_HDINP1_R A_HDINN1_R A_HDINP2_R A_HDINN2_R A_HDINP3_R A_HDINN3_R A_HDOUTP0_R A_HDOUTN0_R A_HDOUTP1_R A_HDOUTN1_R A_HDOUTP2_R A_HDOUTN2_R A_HDOUTP3_R A_HDOUTN3_R B_HDINP0_R B_HDINN0_R B_HDINP1_R B_HDINN1_R B_HDINP2_R B_HDINN2_R B_HDINP3_R B_HDINN3_R B_HDOUTP0_R B_HDOUTN0_R B_HDOUTP1_R B_HDOUTN1_R B_HDOUTP2_R B_HDOUTN2_R B_HDOUTP3_R B_HDOUTN3_R

[9]

J31 Rosenberger 32K153-400E3

J29 Rosenberger 32K153-400E3

J27 Rosenberger 32K153-400E3

J23 Rosenberger 32K153-400E3

J20 Rosenberger 32K153-400E3

J16 Rosenberger 32K153-400E3

J11 Rosenberger 32K153-400E3

J6 Rosenberger 32K153-400E3

B_REFCLKP_L [9]

B_REFCLKN_L [9]

B_REFCLKP_R [9]

B_REFCLKN_R

B_HDOUTN3_R

B_HDOUTP3_R

B_HDOUTN2_R

B_HDOUTP2_R

B_HDOUTN1_R

C76

C78

C80

C82

C84

C87

C91

C93

C95

C97

C99

C101

C103

C105

C107

C109 100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

100NFX5R-0402SMT

J10 Rosenberger 32K153-400E3

J15 Rosenberger 32K153-400E3

J19 Rosenberger 32K153-400E3

J22 Rosenberger 32K153-400E3

J26 Rosenberger 32K153-400E3

J28 Rosenberger 32K153-400E3

J30 Rosenberger 32K153-400E3

3G_361_INN0

3G_361_INP1

3G_361_INN1

3G_361_INP2

3G_361_INN2

3G_361_INP3

3G_361_INN3

1

1

1

1

1

1

1

2

J5 Rosenberger 32K153-400E3

3G_361_OUTP0

3G_361_OUTN0

3G_361_OUTP1

3G_361_OUTN1

3G_361_OUTP2

3G_361_OUTN2

3G_361_OUTP3

3G_361_OUTN3

1

1

1

1

1

1

1

1

200K

200K

PCIe Terminations

2

3G_361_INP0

3G SMAs

HDOUT

50

50

50

50

50

B_HDOUTP1_R

B_HDOUTN0_R

B_HDOUTP0_R

50

50

50

A_HDOUTP3_R A_HDOUTN3_R

50 50

A_HDOUTP2_R A_HDOUTN2_R

50

A_HDOUTP1_R A_HDOUTN1_R

50

A_HDOUTN0_R

50

B_HDINN3_R

A_HDOUTP0_R

50

50 50

B_HDINP3_R

50

50

B_HDINP2_R B_HDINN2_R

50 50

B_HDINP1_R B_HDINN1_R

B_HDINN0_R

50

50

B_HDINP0_R

50

50

A_HDINP3_R A_HDINN3_R

50

A_HDINN2_R

50

50

A_HDINP2_R

A_HDINP1_R A_HDINN1_R

50 50 50

50

1

Place Capacitors and Resistors as Physically close to device pin as possible

A3 B3 A6 B6 A7 B7 A10 B10 A4 B4 A5 B5 A8 B8 A9 B9 E10 F10 E11 F11 E12 F12 E13 F13 A11 B11 A12 B12 A13 B13 A14 B14

A_HDINP0_R A_HDINN0_R

50

C110

C108

C106

C104

C102

C100

C98

C96

C94

C92

C89

C86

C83

C81

C79

C77

J7

J12

J17

J24

Title

D a te :

S iz e C

AC Coupled receiver + 200K Ohm to GND

1

STUFF OPTION A: R82,R83,R84,R85,R86,R87,R88,R89 R93,R94,R98,R95,R99,R96,R100,R97 ==OPEN

J8

J13

J18

J25

1

SC PCI EXPRESS Card

P roje c t

SERDES

6G_360_INN1 1 SMA Edge Launch Rosenberger 32K243

6G_360_INP1 1 SMA Edge Launch Rosenberger 32K243

6G_360_INN0 1 SMA Edge Launch Rosenberger 32K243

6G_360_INP0 1 SMA Edge Launch Rosenberger 32K243

S he e t

5

of

10

6G_360_OUTN1 1 SMA Edge Launch Rosenberger 32K243

6G_360_OUTP1 1 SMA Edge Launch Rosenberger 32K243

6G_360_OUTN0 1 SMA Edge Launch Rosenberger 32K243

6G_360_OUTP0 1 SMA Edge Launch Rosenberger 32K243

6G Edge Launch SMAs

HDIN

PERn0

PERp0

PERn1

PERp1

PERn2

PERp2

PERn3

PERp3

PERn4

PERp4

PERn5

PERp5

PERn6

PERp6

PERn7

PERp7

PETn0

PETp0

PETn1

PETp1

PETn2

PETp2

PETn3

PETp3

PETn4

PETp4

PETn5

PETp5

PETn6

PETp6

PETn7

PETp7

PETp0 PETn0

STUFF OPTION A: REPLACE C76, C77, C78,C79,C80,C81 C82,C83,C84,C85,C86,C87,C89,C91, C92,C93,C94 WITH 0-OHM SHUNTS

PETp1 PETn1

3

PETp3 PETn3

For SMPTE Video Mode Remove 100-ohm resistors

A32 B32 A29 B29 A28 B28 A25 B25 A31 B31 A30 B30 A27 B27 A26 B26 E25 F25 E24 F24 E23 F23 E22 F22 A24 B24 A23 B23 A22 B22 A21 B21

A_RESP_L

PETp4 PETn4

6G_360_INP0 6G_360_INN0 A_HDINP1_L A_HDINN1_L

A_RESP_R

PETp5 PETn5

For 6G MODE on 360 Ch#0 & 3 Only FILT external filter for 6G mode needed

A_RESP_R

A_REFCLKP_L A_REFCLKN_L A_REFCLKP_R A_REFCLKN_R RESERVED1 ULC_RESP RESERVED2 URC_RESP B_REFCLKP_L B_REFCLKN_L B_REFCLKP_R B_REFCLKN_R RESERVED3 RESERVED4 RESERVED5 RESERVED6 G27 H27 G8 H8 G26 H26 G9 H9 H24 J24 H11 J11 H23 J23 H12 J12

PETp6 PETn6

4

2

PETn7

D

5

2 2 2 2

2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2

PETp2 PETn2

2

2 2 2 2

PETp7

R82 200K-0402SMT R83 200K-0402SMT R84 200K-0402SMT R85 200K-0402SMT R86 200K-0402SMT R87 200K-0402SMT R88 200K-0402SMT R89 200K-0402SMT R93 200K-0402SMT R94 200K-0402SMT R98 200K-0402SMT R95 200K-0402SMT R99 200K-0402SMT R96 200K-0402SMT R100 200K-0402SMT R97 200K-0402SMT

2

19

2

R ev 2.0

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 9. SERDES

A

B

R105 1K-0603SMT

R108 1K-0603SMT

1_8V

1_8V

1_8V

10NF-0603SMT

10NF-0603SMT

FB9

BLM41PG600SN1

+ C132

VDDL

R107 OPEN-0603SMT

10NF-0603SMT

1K_ADJ/SMT3MM

C142

C151

C131

R106

C125 10NF-0603SMT

R103 4_7K-0603SMT

C130

100NF-0603SMT

100NF-0603SMT

C

1_8V

C143

C152

100NF-0603SMT

5

22UF-16V_TANTBSMT

R104 0R-0603SMT

10NF-0603SMT

10NF-0603SMT

C141

C150

100NF-0603SMT

C113

C133

C144

C153

1_8V

4

2

C114

5

VREF

SD

C115

8

3

100NF-0603SMT C116 PP58

C124

C118

LP2996-SO8

VTT

VSENSE

+ C123

1_8V

+ C117

1_8V

VDDQ

22UF-16V_TANTBSMT

1UF-16V-0805SMT C134 C145 C154

1UF-16V-0805SMT

100NF-0603SMT

100NF-0603SMT

6 7 AVIN PVIN GND 1 22UF-16V_TANTBSMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT

47UF-16V_TANTBSMT C119

C120 +

VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREF VDDL VSSDL

U18B

C122 + 10UF-16V_TANTBSMT

R113

1K_ADJ/SMT3MM

R110

R109

1_8V

DDR2-SDRAM-84FBGA

A1 E1 J9 M9 R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J2 J1 J7

C121

100UF-FKSMT

U17

C135

1UF-16V-0805SMT

D

C136

1UF-16V-0805SMT 10NF-0603SMT

100NF-0603SMT 100NF-0603SMT

1UF-16V-0805SMT C146 C155

1 2 100NF-0603SMT 100NF-0603SMT

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK CK# CKE WE# RAS# CAS# ODT CS# BA0 BA1 NC_A2 NC_E2 NC_R8 RFU_L1 RFU_R3 RFU_R7

4

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 F7 E8 B7 A8 F3 B3 J8 K8 K2 K3 K7 L7 K9 L8 L2 L3 A2 E2 R8 L1 R3 R7

OPEN-0603SMT

R112

DDR2-SDRAM-84FBGA

U18A

PP63

DDR_VTT

MC_VREF MemIntf_ODT0

MemIntf_BA0 MemIntf_BA1

MemIntf_CS0# MemIntf_CAS#

PP59

MC_VREF MemIntf_DQS1

MemIntf_DQS0

MemIntf_DM1 MemIntf_DQ7 MemIntf_DQ8 MemIntf_DQ9 MemIntf_DQ10 MemIntf_DQ11 MemIntf_DQ12 MemIntf_DQ13 MemIntf_DQ14 MemIntf_DQ15 MemIntf_K MemIntf_K#

MemIntf_DM0 MemIntf_DQ0 MemIntf_DQ1 MemIntf_DQ2 MemIntf_DQ3 MemIntf_DQ4 MemIntf_DQ5 MemIntf_DQ6

MemIntf_CE0#

MemIntf_A12

MemIntf_A10 MemIntf_A11

MemIntf_A4 MemIntf_A5 MemIntf_A6 MemIntf_A7 MemIntf_A8 MemIntf_A9

MemIntf_A2 MemIntf_A3

MemIntf_A0 MemIntf_A1

MC_VREF_REG [3]

MC_VREF

R111 0R-0603SMT

MemIntf_DM0 MemIntf_DM1 MemIntf_K MemIntf_K# MemIntf_CE0# MemIntf_WE# MemIntf_RAS# MemIntf_CAS# MemIntf_ODT0 MemIntf_CS0# MemIntf_BA0 MemIntf_BA1

MemIntf_DQS1

MemIntf_DQ15 MemIntf_DQ14 MemIntf_DQ13 MemIntf_DQ12 MemIntf_DQ11 MemIntf_DQ10 MemIntf_DQ9 MemIntf_DQ8 MemIntf_DQ7 MemIntf_DQ6 MemIntf_DQ5 MemIntf_DQ4 MemIntf_DQ3 MemIntf_DQ2 MemIntf_DQ1 MemIntf_DQ0 MemIntf_A0 MemIntf_A1 MemIntf_A2 MemIntf_A3 MemIntf_A4 MemIntf_A5 MemIntf_A6 MemIntf_A7 MemIntf_A8 MemIntf_A9 MemIntf_A10 MemIntf_A11 MemIntf_A12 MemIntf_DQS0

MemIntf_RAS# MemIntf_WE#

U1C

BANK 5

LFSC1152BGA

BOTTOM

PB65A PB65B PB65C PB65D PB66A PB66B PB66C PB99D PB66D PB67A PB67B PB67C PB67D PB69A PB69B PB69C PB69D PB70A PB70B PB70C PB70D PB71A PB71B PB71C PB71D PB73A PB73B PB73C PB73D PB74A/PCLKT4_2 PB74B/PCLKC4_2 PB74C/PCLKT4_7 PB74D/PCLKC4_7 PB75A/PCLKT4_1 PB75B/PCLKC4_1 PB75C/PCLKT4_6 PB75D/PCLKC4_6 PB77A/PCLKT4_0 PB77B/PCLKC4_0 PB77C/VREF2_4 PB77D PB79A/PCLKT4_5 PB79B/PCLKC4_5 PB79C/DIFFR_4 PB79D PB80A/PCLKT4_3 PB80B/PCLKC4_3 PB80C/PCLKT4_4 PB80D/PCLKC4_4 PB83A PB83B PB99A PB99B PB99C PB101A PB101B PB101C PB101D PB104A PB104B PB104C PB104D PB107A PB107B PB107C PB107D PB109A PB109B PB109C PB109D PB111A PB111B PB111C PB111D PB113A PB113B PB113C PB113D PB115A PB115B PB115C PB115D PB117A PB117B PB117C PB117D PB119A PB119B PB119C PB119D PB121A PB121B PB121C PB121D PB123A PB123B PB123C/VREF1_4 PB123D PB124A/LRC_DLLT_IN_C/LRC_DLLT_FB_D PB124B/LRC_DLLC_IN_C/LRC_DLLC_FB_D PB124C PB124D PB125A/LRC_PLLT_IN_A/LRC_PLLT_FB_B PB125B/LRC_PLLC_IN_A/LRC_PLLC_FB_B PB125C/LRC_DLLT_IN_D/LRC_DLLT_FB_C PB125D/LRC_DLLC_IN_D/LRC_DLLC_FB_C

LFSC 1152BGA

PB3A/LLC_PLLT_IN_A/LLC_PLLT_FB_B PB3B/LLC_PLLC_IN_A/LLC_PLLC_FB_B PB3C/LLC_DLLT_IN_C/LLC_DLLT_FB_D PB3D/LLC_DLLC_IN_C/LLC_DLLC_FB_D PB4A/LLC_DLLT_IN_D/LLC_DLLT_FB_C PB4B/LLC_DLLC_IN_D/LLC_DLLC_FB_C PB4C PB4D PB5A PB5B PB5C PB5D/VREF1_5 PB7A/ODT0 PB7B PB7C PB7D PB9A PB9B PB9C PB9D PB11A PB11B PB11C PB11D PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB17A PB17B PB17C PB17D PB19A PB19B PB19C PB19D PB21A PB21B PB21C PB21D PB24A PB24B PB24C PB24D PB27A PB27B PB27C PB27D PB29A PB29B PB29C PB29D PB45A PB45B PB48A/PCLKT5_3 PB48B/PCLKC5_3 PB48C/PCLKT5_4 PB48D/PCLKC5_4 PB49A/PCLKT5_5 PB49B/PCLKC5_5 PB49C/DIFFR_5 PB49D PB51A/PCLKT5_0 PB51B/PCLKC5_0 PB51C PB51D/VREF2_5 PB52A/PCLKT5_1 PB52B/PCLKC5_1 PB52C/PCLKT5_6 PB52D/PCLKC5_6 PB53A/PCLKT5_2 PB53B/PCLKC5_2 PB53C/PCLKT5_7 PB53D/PCLKC5_7 PB55A PB55B PB55C PB55D PB56A PB56B PB56C PB56D PB57A PB57B PB57C PB57D PB59A PB59B PB59C PB59D PB60A PB60B PB60C PB60D PB61A PB61B PB61C PB61D PB63A PB63B PB63C PB63D

BANK 4

AP17 AP16 AJ17 AH17 AN17 AN16 AE17 AF13 AD17 AK17 AK16 AG17 AF17 AM16 AM15 AJ15 AJ14 AL16 AL15 AG16 AF16 AP15 AP14 AH15 AH14 AP13 AP12 AK13 AK12 AN15 AN14 AE16 AD16 AK15 AK14 AG15 AG14 AM13 AM12 AJ12 AJ11 AL13 AL12 AH12 AH11 AN13 AN12 AD14 AD15 AP11 AP10 AN11 AN10 AF14 AM10 AM9 AE14 AE13 AP9 AP8 AK11 AK10 AL10 AL9 AF12 AF11 AN9 AN8 AG11 AG10 AP7 AP6 AG13 AG12 AN7 AN6 AK9 AK8 AP5 AP4 AD11 AE11 AM7 AM6 AJ9 AJ8 AP3 AN3 AF10 AE10 AL7 AL6 AK7 AK6 AN5 AN4 AH9 AH8 AM3 AM4 AG9 AG8 AN2 AM2 AJ6 AH6

3

VTT

U18 Pin X1

U1 Pin

2

C360

DDR_VTT

A3 B3 C3 D3 E3 F3 G3 H3 J3

A3 B3 C3 D3 E3 F3 G3 H3 J3

CTS-RT1402B7

A3 B3 C3 D3 E3 F3 G3 H3 J3

C237

C275

C276

C337

C338

C361

R1=50 Ohm

C362

R1

C394

R1

A1 B1 C1 D1 E1 F1 G1 H1 J1

C395

RP1

A1 B1 C1 D1 E1 F1 G1 H1 J1

C396

C397

MemIntf_A9 MemIntf_A10 MemIntf_A11 MemIntf_A12

MemIntf_A0 MemIntf_A1 MemIntf_A2 MemIntf_A3 MemIntf_A4 MemIntf_A5 MemIntf_A6 MemIntf_A7 MemIntf_A8

D a te :

S iz e C

Title

R1

R1

RP2

A1 B1 C1 D1 E1 F1 G1 H1 J1

1

SC PCI EXPRESS Card

P roje c t

DDR2

R1=50 Ohm

A1 B1 C1 D1 E1 F1 G1 H1 J1

S he e t

6

MemIntf_WE# MemIntf_RAS# MemIntf_CAS# MemIntf_BA1 MemIntf_BA0 MemIntf_CS0# MemIntf_ODT0 MemIntf_CE0#

of

100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT

C398

CTS-RT1402B7

A3 B3 C3 D3 E3 F3 G3 H3 J3

C236

1

100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT

SP67

SP61

SP64

SP58

SP66

SP65

SP60

SP59

SP63

SP62

SP57

SP37

DDR_VTT

Termination at end of line X1 needs to be matched length for all traces

X2

ALL Memory controller buses, clocks, and control traces must be 50 Ohm Transmission lines

AM33 AN33 AH29 AJ29 AM32 AM31 AG27 AG26 AL29 AL28 AH27 AH26 AN32 AP32 AF25 AE25 AN31 AN30 AK29 AK28 AP31 AP30 AD24 AE24 AM29 AM28 AJ27 AJ26 AP29 AP28 AK27 AK26 AN29 AN28 AG25 AG24 AL26 AL25 AG23 AG22 AN27 AN26 AF24 AF23 AP27 AP26 AK25 AK24 AN25 AN24 AE22 AE21 AM26 AM25 AF22 AF21 AN23 AN22 AP25 AP24 AD21 AD20 AL23 AL22 AH24 AH23 AM23 AM22 AJ24 AJ23 AN21 AN20 AE19 AD19 AK21 AK20 AK23 AK22 AP23 AP22 AG21 AG20 AL20 AL19 AG19 AF19 AP21 AP20 AH21 AH20 AM20 AM19 AJ21 AJ20 AK19 AK18 AE18 AD18 AN19 AN18 AG18 AF18 AP19 AP18 AJ18 AH18

2

C126

1 2 C148

10NF-0603SMT

R102 0R-0603SMT

1K-0603SMT 1K-0603SMT

C127 100NF-0603SMT C139

3

10NF-0603SMT C140

2_5V

10NF-0603SMT

J2 J2 J2

J2

+

C147

1 1 1

1 1 1

1

H2 H2 H2

H2

100NF-0603SMT C128

1

G2 G2 G2

C129

1

F2 F2 F2

F2 G2

4

10NF-0603SMT

C2

1_8V

1 2

E2 E2 E2

E2

2_5V

C149

MemIntf_A[0:12] 100NF-0603SMT

D2 D2 D2

D2

5

10NF-0603SMT

1 1

C137

B2 B2 B2

C2

100NF-0603SMT

1

100NF-0603SMT

A2 A2 C2

A2 B2

20

A2

MemIntf_DQ[0:15] 10NF-0603SMT C138

MemIntf_A[0:12]

C2

10

R ev 2.0

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 10. DDR2

J43 Johnson 142-0711-201

J45 Johnson 142-0711-201

J47 Johnson 142-0711-201

LVDS_INN_2

LVDS_INP_3

LVDS_INN_3

1

1

1

LVDS_OUTP_3

LVDS_OUTN_3

1

1

4

BOURNS-3224W-202E-2K

R154

DP1

3

[9] FPGA_PCLK_CLKP [9] FPGA_PCLK_CLKN

R155 0R-0603SMT

R153 100R-0603SMT

1

[9] OSC_IN_1

LVDS_INP_0 LVDS_INN_0 LVDS_INP_1 LVDS_INN_1 LVDS_INP_2 LVDS_INN_2 LVDS_INP_3 LVDS_INN_3 LVDS_PROBEP LVDS_PROBEN VREF_BANK7

LVDS_OUTP_3 LVDS_OUTN_3

VREF_BANK7 LVDS_OUTP_2 LVDS_OUTN_2

LVDS_OUTP_1 LVDS_OUTN_1

LVDS_OUTP_0 LVDS_OUTN_0 OSC_IN_1

FPGA_PLL_CLKP FPGA_PLL_CLKN

FPGA_PCLK_CLKP FPGA_PCLK_CLKN

3

F30 G30 H28 J28 F31 G31 N25 P25 D33 E33 H29 J29 F32 G32 P26 N26 H30 J30 L28 M28 E34 F34 F33 G33 K30 L30 G34 H34 J31 K31 L27 M27 J32 K32 L29 M29 H33 J33 N27 P27 K33 L33 M30 N30 M31 N31 P24 R24 M32 N32 P28 R28 J34 K34 P30 R30 M33 N33 U25 T25 L34 M34 P29 R29 N34 P34 R27 T27 R32 R31 U24 T24 P33 R33 T26 U26

BANK7

U1D

LFSC 1152BGA

PL50A/PCLKT6_0 PL50B/PCLKC6_0 PL50C/PCLKT6_1 PL50D/PCLKC6_1 PL51A PL51B PL51C/PCLKT6_3 PL51D/PCLKC6_3 PL52A PL52B PL52C/PCLKT6_2 PL52D/PCLKC6_2 PL55A PL55B PL55C/VREF1_6 PL55D PL56A PL56B PL56C PL56D PL57A PL57B PL57C PL57D PL59A PL59B PL60A PL60B PL60C PL60D PL61A PL61B PL63A PL63B PL63C PL63D PL64A PL64B PL65A PL65B PL65C PL65D PL67A PL67B PL68A PL68B PL69A PL69B PL76A PL76B PL76C PL76D/DIFFR_6 PL77A PL77B PL77C PL77D PL78A PL78B PL78C PL78D PL80A PL80B PL80C PL80D PL81A PL81B PL81C PL81D PL82A PL82B PL82C PL82D PL84A PL84B PL84C PL84D PL85A PL85B PL85C PL85D PL86A PL86B PL86C PL86D PL89A PL89B PL89C PL89D/VREF2_6 PL90A PL90B PL90C PL90D PL91A PL91B PL91C PL91D PL93A PL93B PL93C/LLC_DLLT_IN_E/LLC_DLLT_FB_F PL93D/LLC_DLLC_IN_E/LLC_DLLC_FB_F PL94A PL94B PL94C PL94D PL95A/LLC_DLLT_IN_F/LLC_DLLT_FB_E PL95B/LLC_DLLC_IN_F/LLC_DLLC_FB_E PL95C/LLC_PLLT_IN_B/LLC_PLLT_FB_A PL95D/LLC_PLLC_IN_B/LLC_PLLC_FB_A 7 11 12

3 RN5C 4 RN5D 13 12

21

TP_01 TP_02 TP_03 TP_04 TP_05 TP_06 TP_07 TP_08 TP_09 TP_10 TP_11 TP_12 TP_13 TP_14 TP_15 TP_16

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1

D20

D a te :

S iz e C

Title

TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33

18

2_5V

1

1

SC PCI EXPRESS Card

P roje c t

Differential I/O Test SMAs 7

BGA AC33 AA30 AD34 AA28 AA33 AB34 AA29 Y31 Y32 W24 W33 Y34 W26 V34 W25 U33 Y27

S he e t

Debug Testpoints

LTP-587HR/16-SEGMENT

2

16

8 RN6H

6 RN6F 7 RN6G 9

11 10

8 9 13

4 RN6D 5 RN6E

13 12

5 6

2 RN6B 3 RN7C

1 RN6A

8 RN5H 9 16

3 4

6 RN5F

15 EXB2HV121JV 150R 14

15 17

5 RN5E

7 RN5G

11 10

14

14

10

R159 150R-0603SMT 13 4 RN7D EXB2HV121JV 150R 15 2 RN4B

A

2

T32 T31 U29 V29 T30 U30 U27 V27 R34 T34 U28 V28 V30 W30 W27 Y27 T33 U33 V25 W25 U34 V34 V26 W26 W34 Y34 V33 W33 V24 W24 W32 Y32 W31 Y31 Y29 AA29 AA34 AB34 Y33 AA33 Y28 AA28 AC34 AD34 Y30 AA30 AB33 AC33 AB32 AC32 AA26 AA27 AB31 AC31 Y24 AA24 AE34 AF34 AB30 AC30 AD33 AE33 AD30 AE30 AE32 AF32 AA25 AB25 AJ34 AK34 AB27 AC27 AF33 AG33 AC29 AD29 AE31 AF31 AF30 AF29 AH33 AJ33 AC28 AD28 AH32 AJ32 AD27 AE27 AG34 AH34 AC26 AB26 AK33 AL33 AG30 AH30 AL34 AM34 AJ30 AK30 AJ31 AH31 AD26 AD25 AL32 AL31 AG29 AG28 B

LFSC1152BGA

LEFT

PL16A/ULC_PLLT_IN_A/ULC_PLLT_FB_B/DEBUG_BUS11 PL16B/ULC_PLLC_IN_A/ULC_PLLC_FB_B/DEBUG_BUS10 PL16C/DEBUG_BUS13 PL16D PL17A/ULC_DLLT_IN_C/ULC_DLLT_FB_D/DEBUG_BUS9 PL17B/ULC_DLLC_IN_C/ULC_DLLC_FB_D/DEBUG_BUS8 PL17C/ULC_PLLT_IN_B/ULC_PLLT_FB_A PL17D/ULC_PLLC_IN_B/ULC_PLLC_FB_A PL18A/ULC_DLLT_IN_D/ULC_DLLT_FB_C PL18B/ULC_DLLC_IN_D/ULC_DLLC_FB_C PL18C/DEBUG_BUS12 PL18D/VREF2_7/DEBUG_BUS6 PL20A PL20B PL20C PL20D PL21A PL21B PL21C PL21D PL22A PL22B PL24A PL24B PL25A PL25B PL26A PL26B PL29A/TESTCFGN PL29B/DEBUG_BUS7 PL29C/VREF1_7/DEBUG_BUS5 PL29D/DIFFR_7/DEBUG_BUS4 PL31A PL31B PL31C PL31D PL33A PL33B PL33C PL33D PL35A PL35B PL35C PL35D PL37A PL37B PL37C PL37D PL39A PL39B PL39C PL39D PL41A PL41B PL41C PL41D PL42A PL42B PL42C PL42D PL43A PL43B PL43C PL43D PL46A PL46B PL46C PL46D PL47A/PCLKT7_1/DEBUG_BUS3 PL47B/PCLKC7_1/DEBUG_BUS2 PL47C/PCLKT7_3 PL47D/PCLKC7_3 PL48A/PCLKT7_0/DEBUG_BUS1 PL48B/PCLKC7_0/DEBUG_BUS0 PL48C/PCLKT7_2/DEBUG_BUS14 PL48D/PCLKC7_2/DEBUG_BUS15 C

R121

LVDS_OUTN_2

1

PP60

LVDS_OUTP_2

1

[9] FPGA_PLL_CLKP [9] FPGA_PLL_CLKN

D

R120

LVDS_OUTN_1

1

E

1K_ADJ/SMT3MM

LVDS_OUTP_1

1

SEGMENT A B C D E F G H K M N P R S T U DP

F

5

J41 Johnson 142-0711-201

LVDS_INP_2

1

LVDS_OUTN_0

1

2

G

VREF_BANK7

J39 Johnson 142-0711-201

LVDS_INN_1

1

R119

J34 Johnson 142-0711-201

LVDS_INP_1

1

2_5V

J32 Johnson 142-0711-201

LVDS_INN_0

1

LVDS_OUTP_0

1

3

H

A

J46 Johnson 142-0711-201

J44 Johnson 142-0711-201

J42 Johnson 142-0711-201

J40 Johnson 142-0711-201

J35 Johnson 142-0711-201

J33 Johnson 142-0711-201

J38 Johnson 142-0711-201

J37 Johnson 142-0711-201

LVDS_INP_0

1

4

K

B

C

D

J36 Johnson 142-0711-201

2

2

2

2

2

2

2

2

2 2 2 2 2 2 2

R114 100R-0603SMT R116 100R-0603SMT R117 100R-0603SMT R118 100R-0603SMT

5

M

1K-0603SMT

N

C156

P

1K-0603SMT

R

10NF-0603SMT

S

2

T

2

U

R115 1_1K-0603SMT

DP

1 2

of

10

R ev 2.0

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 11. Differential I/O Test SMAs

BANK6

22

A

B

C

5

R124

2_5V

R128

1K_ADJ/SMT3MM

R127

R126

R123

C157 C158

1K-0603SMT 1K-0603SMT 1K-0603SMT 1K-0603SMT

PP62

VREF_BANK3

PP61

VREF_BANK2

1

2

1K_ADJ/SMT3MM

10NF-0603SMT 10NF-0603SMT

R122

J48 Johnson 142-0711-201

1 R166

4

4

J49 Johnson 142-0711-201 R167

1

[5,9] [5,9] PCIE_CLKP PCIE_CLKN

[9] OSC_IN_2

R125 1_1K-0603SMT

2_5V

1

2

D

5

LOOP_P1 LOOP_N1 OSC_IN_2

LOOP_P0 LOOP_N0

LOOP_P15 LOOP_N15

LOOP_P14 LOOP_N14

LOOP_P13 LOOP_N13

LOOP_P12 LOOP_N12

LOOP_P11 LOOP_N11

LOOP_P10 LOOP_N10

LOOP_P9 LOOP_N9

LOOP_P8 LOOP_N8

LOOP_P7 LOOP_N7

LOOP_P6 LOOP_N6 VREF_BANK2

LOOP_P5 LOOP_N5

LOOP_P4 LOOP_N4

LOOP_P3 LOOP_N3

VREF_BANK2 LOOP_P2 LOOP_N2

LOOP_P1 LOOP_N1

LOOP_P0 LOOP_N0

PLL_CLK_INP PLL_CLK_INN

3

3

F5 G5 H7 J7 F4 G4 N10 P10 D2 E2 H6 J6 F3 G3 P9 N9 H5 J5 L7 M7 E1 F1 F2 G2 K5 L5 G1 H1 J4 K4 L8 M8 J3 K3 L6 M6 H2 J2 N8 P8 K2 L2 M5 N5 M4 N4 P11 R11 M3 N3 P7 R7 J1 K1 P5 R5 M2 N2 U10 T10 L1 M1 P6 R6 N1 P1 R8 T8 R3 R4 U11 T11 P2 R2 T9 U9

BANK2

U1K

LFSC1152BGA

RIGHT

BANK3

2

PR50A/PCLKT3_0 PR50B/PCLKC3_0 PR50C/PCLKT3_1 PR50D/PCLKC3_1 PR51A PR51B PR51C/PCLKT3_3 PR51D/PCLKC3_3 PR52A PR52B PR52C/PCLKT3_2 PR52D/PCLKC3_2 PR55A PR55B PR55C/VREF1_3 PR55D PR56A PR56B PR56C PR56D PR57A PR57B PR57C PR57D PR59A PR59B PR60A PR60B PR60C PR60D PR61A PR61B PR63A PR63B PR63C PR63D PR64A PR64B PR65A PR65B PR65C PR65D PR67A PR67B PR68A PR68B PR69A PR69B PR76A PR76B PR76C PR76D/DIFFR_3 PR77A PR77B PR77C PR77D PR78A PR78B PR78C PR78D PR80A PR80B PR80C PR80D PR81A PR81B PR81C PR81D PR82A PR82B PR82C PR82D PR84A PR84B PR84C PR84D PR85A PR85B PR85C PR85D PR86A PR86B PR86C PR86D PR89A PR89B PR89C PR89D/VREF2_3 PR90A PR90B PR90C PR90D PR91A PR91B PR91C PR91D PR93A PR93B PR93C/LRC_DLLT_IN_E/LRC_DLLT_FB_F PR93D/LRC_DLLC_IN_E/LRC_DLLC_FB_F PR94A PR94B PR94C PR94D PR95A/LRC_DLLT_IN_F/LRC_DLLT_FB_E PR95B/LRC_DLLC_IN_F/LRC_DLLC_FB_E PR95C/LRC_PLLT_IN_B/LRC_PLLT_FB_A PR95D/LRC_PLLC_IN_B/LRC_PLLC_FB_A

LFSC 1152BGA

PR16A/URC_PLLT_IN_A/URC_PLLT_FB_B PR16B/URC_PLLC_IN_A/URC_PLLC_FB_B PR16C PR16D PR17A/URC_DLLT_IN_C/URC_DLLT_FB_D PR17B/URC_DLLC_IN_C/URC_DLLC_FB_D PR17C/URC_PLLT_IN_B/URC_PLLT_FB_A PR17D/URC_PLLC_IN_B/URC_PLLC_FB_A PR18A/URC_DLLT_IN_D/URC_DLLT_FB_C PR18B/URC_DLLC_IN_D/URC_DLLC_FB_C PR18C PR18D/VREF2_2 PR20A PR20B PR20C PR20D PR21A PR21B PR21C PR21D PR22A PR22B PR24A PR24B PR25A PR25B PR26A PR26B PR29A PR29B PR29C/VREF1_2 PR29D/DIFFR_2 PR31A PR31B PR31C PR31D PR33A PR33B PR33C PR33D PR35A PR35B PR35C PR35D PR37A PR37B PR37C PR37D PR39A PR39B PR39C PR39D PR41A PR41B PR41C PR41D PR42A PR42B PR42C PR42D PR43A PR43B PR43C PR43D PR46A PR46B PR46C PR46D PR47A/PCLKT2_1 PR47B/PCLKC2_1 PR47C/PCLKT2_3 PR47D/PCLKC2_3 PR48A/PCLKT2_0 PR48B/PCLKC2_0 PR48C/PCLKT2_2 PR48D/PCLKC2_2

2

LOOP_P2 T3 LOOP_N2 T4 PCLK_CLK_INP U6 PCLK_CLK_INN V6 LOOP_P3 T5 LOOP_N3 U5 U8 V8 LOOP_P4 R1 LOOP_N4 T1 U7 V7 LOOP_P5 V5 LOOP_N5 W5 VREF_BANK3 W8 Y8 LOOP_P6 T2 LOOP_N6 U2 V10 W10 LOOP_P7 U1 LOOP_N7 V1 V9 W9 LOOP_P8 W1 LOOP_N8 Y1 LOOP_P9 V2 LOOP_N9 W2 V11 W11 LOOP_P10 W3 LOOP_N10 Y3 LOOP_P11 W4 LOOP_N11 Y4 Y6 AA6 LOOP_P12 AA1 LOOP_N12 AB1 LOOP_P13 Y2 LOOP_N13 AA2 Y7 AA7 LOOP_P14 AC1 LOOP_N14 AD1 LOOP_P15 Y5 LOOP_N15 AA5 AB2 AC2 AB3 AC3 AA9 AA8 AB4 AC4 Y11 AA11 AE1 AF1 AB5 AC5 AD2 AE2 AD5 AE5 AE3 AF3 AA10 AB10 AJ1 AK1 AB8 AC8 AF2 AG2 AC6 AD6 AE4 AF4 AF5 AF6 AH2 AJ2 AC7 AD7 AH3 AJ3 AD8 VREF_BANK3 AE8 AG1 AH1 AC9 AB9 AK2 AL2 AG5 AH5 AL1 AM1 AJ5 AK5 AJ4 AH4 AD9 AD10 AL3 AL4 AG6 OSC_IN_3 AG7 R129 1_1K-0603SMT

51R-0603SMT D a te :

S iz e C

Title

1 2

J51 Johnson 142-0711-201 51R-0603SMT

1

SC PCI EXPRESS Card

P roje c t

Differential I/O Loops

OSC_IN_3 [9]

R169

1

1

S he e t

R168

8

of

10

R ev 2.0

J50 Johnson 142-0711-201

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 12. Differential I/O Loops

2

51R-0603SMT

2

51R-0603SMT

2

A

B

C

1

1_6R-0603SMT C162

R134

JUMPER1

J101

2

J102 HEADER 2X1

5

+

10UF-16V_TANTBSMT

3_3V

2

1

C163

10 9 8 7 6 5 4 3 2 1

NC

Q_N

5

4

Y3 CW-P423F-312.5MHZ

Q

R182 OPEN-0603SMT

REFA_P REFA_N

1

8

R137 82R-0603SMT

3_3V

REFA

82R-0603SMT

R138

OSC_N

OSC_P

R136 130R-0603SMT

3_3V

R184 0R-0603SMT

R183 0R-0603SMT

PCIe

20 19 18 17 16 15 14 13 12 11

SW8

TDA10H0SK1

10 9 8 7 6 5 4 3 2 1

20 19 18 17 16 15 14 13 12 11

3_3V

1 R143

R172 1K-0603SMT

R175 2_2K-0603SMT

4

ISPCLK_LOCK [2] PLL_BYPASS [2] PS0 [2] PS1 [2] GOE [2] SGATE [2] REFSEL [2] OEX [2] OEY [2] ISPCLK_RST [2]

1

39

92 89 88 87 85 43 44 45 86

REFA_N

PLL_BYPASS PS0 PS1 GOE SGATE REFSEL OEX OEY ISPCLK_RST

R144

REFCLK_EXT_IN_N

[7] OSC_IN_1 [8] OSC_IN_2

[2] TDI_ISPCLK [2] TDO_ISPCLK [2] TMS [2] TCK

72

41

42 REFB-

REFB+

LOCK

TEST1 TEST2

PLL_BYPASS PS0 PS1 GOE SGATE REFSEL OEX OEY RESET

REFA-

REFA+

U21

100NF-0603SMT

OSC_IN_1 OSC_IN_2

3_3V

ISPCLK_LOCK

91 90

38

C413 C414

ISPCLOCK VCCO CLK_VCCO

REFA_P

C165

FB21 BLM41PG471SN1L

EXB2HV102JV

51R-0603SMT

REFCLK_EXT_IN_P J92 Johnson 142-0711-201

D22 LED-SMT1206_ORANGE O

51R-0603SMT

C412 100NF-0603SMT

R177 680R-0603SMT

J91 Johnson 142-0711-201

To Drive any of the SERDES reference clocks directly from SMAs, put ispCLOCK in bypass

DIS#

Q_N

Q

OSC

R135 130R-0603SMT Y1 110-93-314-41-001

VDD GND 7

3_3V

PCIE_CLKN

15

14

Layout with minimum stubs and matched differential traces

[5,8]

R181 OPEN-0603SMT

13

D

PCIE_CLKN

14

C161

PCIE_CLKP

12

100NF-0603SMT

1 2

1 2

100NF-0603SMT

6

PCIE_CLKP

10

C415

1 2 3 4

3

CY2304-1

3

GND

N/C

REF FBK CLKA1 VDD CLKA2 CLKB2 GND CLKB1

U20

Y2

OUT

Vcc

8 7 6 5

2

1

CTS-CB3LV-3C-100.00MHZ

4

C418

10NF-0603SMT

ispCLK5620A-100TQFP

C419

100NF-0603SMT

C417

FB20 BLM41PG471SN1L

C416

31

[5,8]

2

9

10NF-0603SMT

30 VCCA

GNDA

FB22 BLM41PG471SN1L

1K

VCC

GND

3

16 RN9A

1

1K RN8B

2

1K RN8C

3

1K RN8D

4

1K RN8E

5

11 6

1K RN8G

7

1K RN8H

8

100NF-0603SMT 3_3V

C159

47 71

10NF-0603SMT

TDI TDO TMS TCK 84 73 82 83

1K RN8F

2

10NF-0603SMT

3 7 11 15 19 51 55 59 63 67 VCCO_0 VCCO_1 VCCO_2 VCCO_3 VCCO_4 VCCO_5 VCCO_6 VCCO_7 VCCO_8 VCCO_9 RESERVED1 RESERVED3 RESERVED2 RESERVED4 80 95 81 96

40 REFVTT

100NF-0603SMT

74 VCCJ

VCCD1 VCCD2

OSC_IN_3 OSC_IN_4

3_3V

C160

32 33 34 35 36 37 46 93 6 10 14 18 22 54 58 62 66 70

5 4 9 8 13 12 17 16 21 20 53 52 57 56 61 60 65 64 69 68

10NF-0603SMT

C167

GNDD_1 GNDD_2 GNDD_3 GNDD_4 GNDD_5 GNDD_6 GNDD_7 GNDD_8 GNDO_0 GNDO_1 GNDO_2 GNDO_3 GNDO_4 GNDO_5 GNDO_6 GNDO_7 GNDO_8 GNDO_9

3_3V

C421

100NF-0603SMT

100NF-0603SMT

BANK_0A BANK_0B BANK_1A BANK_1B BANK_2A BANK_2B BANK_3A BANK_3B BANK_4A BANK_4B BANK_5A BANK_5B BANK_6A BANK_6B BANK_7A BANK_7B BANK_8A BANK_8B BANK_9A BANK_9B

OSC_IN_3 [8] OSC_IN_4 [2]

100NF-0603SMT

C166

10NF-0603SMT C164

C420

NC1 NC2 NC3 NC4 NC5 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23

100NF-0603SMT

R193

R180 82R-0603SMT

R173 82R-0603SMT R174 82R-0603SMT R158 82R-0603SMT

2

R176 130R-0603SMT

3_3V

R142 82R-0603SMT

R179 130R-0603SMT

3_3V

R141 82R-0603SMT

R178 130R-0603SMT

3_3V

R140 82R-0603SMT

3_3V

R133 130R-0603SMT

3_3V

R132 130R-0603SMT

3_3V

R171 130R-0603SMT

3_3V

R139 82R-0603SMT

Trigger Out

1

D a te :

S iz e C

Title

R146 82R-0603SMT

R145 130R-0603SMT

3_3V

R151 82R-0603SMT

R148 130R-0603SMT

3_3V

1

3_3V

S he e t

82R-0603SMT

R152

R149 130R-0603SMT

SC PCI EXPRESS Card

P roje c t

Clocks

82R-0603SMT

R150

R147 130R-0603SMT

3_3V

Do Not Populate for LVDS Ref Clocks

1

J99 Johnson 142-0711-201

R157 51R-0603SMT

A_REFCLKP_L [5] A_REFCLKN_L [5] B_REFCLKP_L [5] B_REFCLKN_L [5] FPGA_PLL_CLKP [7] FPGA_PLL_CLKN [7] FPGA_PCLK_CLKP [7] FPGA_PCLK_CLKN [7] A_REFCLKP_R [5] A_REFCLKN_R [5] B_REFCLKP_R [5] B_REFCLKN_R [5] A_RXREFCLK_L [5]

R131 130R-0603SMT

3_3V

51R-0603SMT

R130 130R-0603SMT

100NF-0603SMT

A_REFCLKP_R

1 2 23 24 25 26 27 28 29 48 49 50 75 76 77 78 79 94 97 98 99 100

2

A_REFCLKN_L A_REFCLKN_R

3

B_REFCLKP_L B_REFCLKP_R

2_5V

B_REFCLKN_L B_REFCLKN_R

3_3V

A_REFCLKP_L

2 FPGA_PLL_CLKP

4

FPGA_PLL_CLKN

5

FPGA_PCLK_CLKP

23

FPGA_PCLK_CLKN 9

of

10

R ev 2.0

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 13. Clocks

24

A

B

C

D

K26 K9 V12 AC18 U23 M17 K23 K20 J15 L12 F19 G16 D18 C17 AP33 AP2 AN34 AN1 AM8 AL5 AM30 AL27 AM24 AL21 AM18 AL17 AM14 AL11 AK31 AK3 AJ28 AH25 AJ22 AH19 AJ16 AH13 AJ10 AH7 AG32 AG4 AF26 AD23 AF20 AE15 AE12 AE9 AE29 AE7 AD31 AD3 AC25 AC11 AB28 AB6 AA32 AA20 AA15 AA4 Y25 Y19 Y16 Y9 W29 W20 W18 W17 W15 W7 V31 Y21 V19 V16 Y14 V3 U32 R21 U19 U16 R14 U4 T28 T20 T18 T17 T15 T6 R26 R19 R16 R10 P31 P20 P15 P3 N29 N7 M24 M10 L32 L4 K28 K6 J26 J10 H31 H3 G29 G7 E32 E4 C31 C30 C27 C26 C24 C23 C22 C21 C14 C13 C12 C11 C9 C8 C5 C4 B34 B1 A33 A2

U1E

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

M HOLE2

M HOLE2

5

MH2

MH1

LFSC1152BGA

VSS

LFSC 1152BGA

5

M HOLE2

MH3

VCCIO7

VCCIO6

VCCIO3

VCCIO2

VCCIO1

VCCAUX

VCC12

VDDTX

VDDRX

VDDP

VDDOB

VCC CORE

C171 C172

C173

C174 C175

C176 C177

C178 C179

C180

C181 C182 C183

C184

C196

C197 C198

C199

C200 C201

C202

C203 C204 C205

C206 C207 C208

C209 C210 C211

C222 C223

C224 C225

C226

C227 C228

C229

C230 C231 C232 C233 C234 C435 C434

C432

C235

C249

C250

22PF-0402SMT

C251

C253

1000PF-0402SMT

C274

C252

2_5V

C254 C255

C256

VDDAX25 22PF-0402SMT

C277

C257

C258

C259 C260

C438 C437 C436

C262 C263

C264 C265

C266

C267 C268

C269

C270 C271

C272 C273

C441

C440 C439

C288

C289 C290

C291 C292 C293 C294

C295

C296

C297 C298

C299 C429

C428

C427

C185 C186

C187 C188 C189

2

C190 C191

C192 C193 C194

C301

C302 C303 C304

C305 C306

C307

C308 C309

C310 C311

C312 C313 C314

C315 C316

C317

C318

HSTL VTT C50

SC_VTT

C57

C67

C430 C431

C319

NC1 NC2 NC3 NC4

A1 A34 AP1 AP34

C320

C321

NO CONNECT DEVICE PINS

LFSC1152BGA

U1G

C322

C323

C324

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C433

C325

C326

C411

C422

C423

1

C424

C426

C425

C327 C328 C329

C330

C331

C332 C333 C334 C335

C336

C352 C353

C354

C355 C356

C357

2_5V

C358

C359

C383

C376

C384

C377 C385

C386

2_5V

C378 C387

C388

C379

C389

C363 C364

C365

C366

C367 C368 C369

C370

C371

C372

C373

C374

C380 C381

C390

C391 C392

2_5V

C393

4

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C375

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

2_5V

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C382

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C351

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

2_5V

3

C400

C401

C402

C403

C404

C405

1_8V

C406

C407

C408

C409

C410

C340

C341

C342

C343

C344

1_8V

C345

C346

C347

C348

C349

C350

2

D a te :

S iz e C

Title

1

SC PCI EXPRESS Card

P roje c t

VSS/Decoupling

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C339

VCCIO5

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C399

VCCIO4

S he e t

10

of

10

R ev 2.0

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C300

2_5V

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C287

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C261

VDDTX

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C248

VDDRX

1000PF-0402SMT

C238

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT VDDP

1_2V

C170

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C195

VCC_CORE

1_5V

C169

ALL CAPS PLACED UNDER BGA

3

1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT

C168

VCC_CORE

4

A

B

C

D

Lattice Semiconductor LatticeSC PCI Express x8 Evaluation Board User’s Guide

Figure 14. VSS/Decoupling