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Introduction to Hardware design and VHDL
SS2009 Introduction to Hardware design and VHDL Kevin Cheng, Felix Mühlbauer and Philipp Mahr University of Potsdam, Germany 14 May 2009 Department...
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SS2009
Introduction to Hardware design and VHDL Kevin Cheng, Felix Mühlbauer and Philipp Mahr
University of Potsdam, Germany 14 May 2009
Department of Computer Science, University of Potsdam, Germany
1
generate begin : for in generate end generate; : if generate end generate; end architecture example; 14 May 2009
Department of Computer Science, University of Potsdam, Germany
2
MSB / LSB architecture behaviour of example is signal down : std_logic_vector(7 downto 0); signal up : std_logic_vector(0 to 7); begin up
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