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Session-06
Introduction to Data Converter Session delivered by:
Chandramohan P.
1 ©M S Ramaiah School of Advanced Studies - Bangalore
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Session Topics • To understanding the concepts of – Introduction to ADC and DAC – DAC specifications – ADC specifications
2 ©M S Ramaiah School of Advanced Studies - Bangalore
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Session Topics • • • • • •
Introduction to ADC and DAC DAC specifications ADC specifications Types of ADCs and DACs Limitations of ADC and DAC in high frequency applications Trade off
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Introduction to ADC and DAC
(a) Analog signal is filtered by an anti-aliasing filter to remove any highfrequency components that may cause an effect known as aliasing (b) The signal is sampled and held and then converted into a digital signal (c) DAC converts the digital signal back into an analog signal (d) The output of the DAC is not as "smooth" as the original signal. A lowpass filter returns the analog signal back to its original form 4 ©M S Ramaiah School of Advanced Studies - Bangalore
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Converting Analog Signal to Digital Signal
(a) An analog signal representing the temperature where you live (b) A digital representation of the analog signal taking one sample per day with two quantization levels. If 0° F < T < 25° F Temperature is recorded as cold If 25° F < T < 50° F Temperature is recorded as hot Discretized version of the weather is not an accurate representation of the actual weather. 5 ©M S Ramaiah School of Advanced Studies - Bangalore
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Converting Analog Signal to Digital Signal cont.
(a) Two samples per day with four quantization levels (b) Nine samples per day with 25 quantization levels. Increasing both sampling time and resolution, the difference between the analog and the digital signals would become negligible 6 ©M S Ramaiah School of Advanced Studies - Bangalore
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Analog-to-Digital Converter Specifications And Terminology
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• Sampling Specs: – Conversion Time, Acquisition Time, Throughput Rate, Aperture Delay, – Aperture Jitter, Step Response • DC Specs: – Specifications derived from ADC tests using DC/low freq test signals • Gain Error, Offset Error, INL, DNL • AC Specs: – Specifications derived from ADC tests using sine wave test signals – SNR, SINAD, ENOB
7 ©M S Ramaiah School of Advanced Studies - Bangalore
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Sample-Hold Operation • All S/H’s require 4 main components: – Buffer Amp: buffers source & provides high current gain to charge the hold capacitor – Hold Capacitor: Retains the sampled voltage in Hold mode – Output Buffer: High impedance to keep held voltage from discharging – Switch & Control: Mechanism by which the hold capacitor is switched from track to hold
8 ©M S Ramaiah School of Advanced Studies - Bangalore
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Sample-Hold Specifications
• Errors in Sample-toHold – Aperture Jitter – Aperture Error • Errors in Hold-toSample – Acquisition time 9 ©M S Ramaiah School of Advanced Studies - Bangalore
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Sample-to-Hold Transition Errors Aperture Uncertainty (“Jitter”) • The RMS variation in time of the sampling instant – Caused by jitter in the Sample-Hold command signal • Places an upper limit on the input frequency to maintain system resolution for full scale input signals.
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Aperture Jitter For +/- 0.25 LSB Error
VSD2537
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Aperture Jitter Effects
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Comparison of different clock sources
Good clock source
Not so good clock source 12
©M S Ramaiah School of Advanced Studies - Bangalore
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Hold-to-Sample Transition Errors Acquisition Time – The length of time during which time the S/H must remain in the sample mode in order for the HOLD CAPACITOR to acquire a full scale step input (to some number of accuracy in LSBs)
13 ©M S Ramaiah School of Advanced Studies - Bangalore
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Digital to Analog Converter • An N-bit digital word is mapped into a single analog voltage. Typically, the output of the DAC is a voltage that is some fraction of a reference voltage (or current) Vout = FVREF Where, VOUT is the analog voltage output VREF is the reference volt F is the fraction defined by the input word, D, that is N bits wide
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Number of inputs • The number of input combinations represented by the input word D is related to the number of bits in the word by Number of input combinations = 2N Example: 4-bit DAC has a total of 24 or 16 total input values. • A converter with 4-bit resolution must be able to map a change in the analog output, which is equal to 1 part in 16. • The maximum analog output voltage for any DAC is limited by the value of VREF. • If the input is an N-bit word, then the value of the fraction, F, can be determined by,
F=
D N 2 15
©M S Ramaiah School of Advanced Studies - Bangalore
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Full Scale Range Example: A 3-bit DAC is being used, the input, D, is 100 = 410, and VREF is 5 V, then the value of F is
100 4 F= = 3 8 2 • The analog voltage that appears at the output is
VOUT =
100 4 = (5) = 2.5V 23 8
• The maximum analog output voltage that can be generated is known as Full-scale voltage, VFS, and can be generalized to any N-bit DAC as N −1
VFS =
2 V 2 N
REF
©M S Ramaiah School of Advanced Studies - Bangalore
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Least Significant Bit (LSB) • The Least Significant Bit (LSB) refers to the rightmost bit in the digital input word. The LSB defines the smallest possible change in the analog output voltage. The LSB will always be denoted as D0. One LSB can be defined as
1LSB =
V 2
REF N
• Example: Find the resolution for a DAC if the output voltage is desired to change in 1 mV increments while using a reference voltage of 5 V. The DAC must resolve
1mV = 0.0002 5V
• The accuracy required for 1 LSB change over a range of VREF is
1LSB
V
REF
=
1 N
2
= 0.0002
©M S Ramaiah School of Advanced Studies - Bangalore
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Least Significant Bit (LSB) Solving N for the resolution yields
5V = 12.29bits 2 1mV
N = Log
• which means that a 13-bit DAC will be needed to produce the accuracy capable of generating 1 mV changes in the output using a 5 V reference. Example: Find the number of input combinations, values for 1 LSB, the percentage accuracy, and the full-scale voltage generated for a 3-bit, 8-bit, and 16-bit DAC, assuming that VREF= 5 V
18 ©M S Ramaiah School of Advanced Studies - Bangalore
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D/A Specifications Cont… Ideal transfer curve for a 3-bit DAC
Differential Nonlinearity for 3 Bit DAC
DNLn = Actual increment height of transition n - Ideal increment height 19 ©M S Ramaiah School of Advanced Studies - Bangalore
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D/A Specifications Cont… • • • • • •
DNLn = Actual increment height of transition n - Ideal increment height DNL3 =1.5 LSB - 1 LSB = 0.5 LSB DNL4 = 0.5 LSB - 1 LSB = - 0.5 LSB DNL5 = 0.25 LSB - 1 LSB = - 0.75 LSB DNL6= 1.75 LSB - 1 LSB = 0.75 LSB DNL1, DNL2 and DNL7 = 1 LSB - 1 LSB =0
DNL curve for the nonideal 3-bit DAC 20 ©M S Ramaiah School of Advanced Studies - Bangalore
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D/A Specifications Cont… Integral Nonlinearity INLn = Output value for input code n - Output value of the reference line at that point
Measuring the INL for a DAC transfer curve
Example of integral nonlinearity for a DAC 21
©M S Ramaiah School of Advanced Studies - Bangalore
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DC Specifications: Offset Error Offset Error • The analog output should be 0 V for D = 0. However, an offset exists if the analog output voltage is not equal to zero
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DC Specifications: Gain Errors Gain Error • A gain error exists if the slope of the best-fit line through the transfer curve is different from the slope of the best-fit line for the ideal case Gain error = Ideal slope - Actual slope
23 ©M S Ramaiah School of Advanced Studies - Bangalore
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DC Specifications Latency • This specification defines the total time from the moment that the input digital word changes to the time the analog output value has settled to within a specified tolerance • Latency should not be confused with settling time, since latency includes the delay required to map the digital word to an analog value plus the settling time. • It should be noted that settling time considerations are just as important for a DAC as they are for a S/H or an operational amplifier.
24 ©M S Ramaiah School of Advanced Studies - Bangalore
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D/A Specifications Dynamic Range • Dynamic range is defined as the ratio of the largest output signal over the smallest output signal. For both DACs and ADCs, the dynamic range is related to the resolution of the converter. • For example, an N-bit DAC can produce a maximum output of 2N – 1 multiples of LSBs and a minimum value of 1 LSB. Therefore, the dynamic range in decibels is simply
n −1 = 6.02 N.dB DR = 20 log 2 1 • A 16-bit data converter has a dynamic range of 96.33 dB.
25 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC Evaluation System
Signal Source
ADC
Analysis Engine
The most common method for quantifying these dynamic errors is by applying a pure sine-wave signal to the ADC and performing an FFT on the output data. These tests yield spectral outputs from which we can calculate the S/N ratio, harmonic distortion and SINAD.
Evaluation Results 26
©M S Ramaiah School of Advanced Studies - Bangalore
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D/A Specifications Cont… Signal-to-Noise Ratio (SNR) • Signal-to-noise (SNR) is defined as the ratio of the signal power to the noise at the analog output • Signal-to-noise (SNR) ratios of ADCs represent the value of the largest RMS input signal into the converter over the RMS value of the noise. SNR = 6.02N+ 1.76 dB • For 16-bit data conversion, one must design a circuit that will have an SNR of (6.02)(16) +1.76 = 98.08 dB • Effective number of bits given a system with a known SNR or SNDR, For 16-bit ADC yielded an SNDR of 88 dB, then the effective resolution of the converter would be N = (88-1.76)/6.02 = 14.32 bits 27 ©M S Ramaiah School of Advanced Studies - Bangalore
VSD2537 AC Specs: Signal to Non-Harmonic Noise Ratio (SNR, or SNHR)
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| M 2|
RMS noise =
Fundamental
2nd Harm.
Σ Non Harmonic Bins
3rd Harm. 4th Harm.
5th Harm.
kHz 10
20
30
40
50
60
70
80
SNR (dB) = 20 LOG ( Fund. rms / rms noise) i.e. no Harmonics Included Indication of Converter Noise Floor NO Indication of Dynamic Range ©M S Ramaiah School of Advanced Studies - Bangalore
90
100
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AC Specs: Total Harmonic Distortion (THD) Distortion rms =Σ Harmonic Bins 2 to 10
Fundamental
2nd Harm. 3rd Harm. 4th Harm.
5th Harm.
kHz 10
20
30
40
50
60
70
80
90
100
THD (%) = (Harmonic RMS Noise / Fundamental RMS) x 100 i.e. - Contains only Harmonic Components THD is an indication of the ADC non-linearities
©M S Ramaiah School of Advanced Studies - Bangalore
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| M 2|
AC Specs: Signal to Noise + Distortion (SINAD)
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Noise + D = Σ of all bins except fundamental
Fundamental
2nd Harm. 3rd Harm. 4th Harm.
5th Harm.
kHz 10
20
30
40
50
60
70
80
90
100
SNR+D (dB) = 20 LOG ( Fundamental rms / (rms noise + harmonics)) i.e. - includes all error components Indication of Converter useful Dynamic Range
©M S Ramaiah School of Advanced Studies - Bangalore
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AC Specs: Spurious Free Dynamic Range (SFDR)
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• SFDR = Spurious Free Dynamic Range – Magnitude of the largest harmonic relative to the fundamental – In this case, about 50dB = 0.32%
31 ©M S Ramaiah School of Advanced Studies - Bangalore
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Frequency Dependent Errors ADS8344 (16-bit, 100kSPs)
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ADS8344 A/D Converter
Ideal 16-bit resolution= 98 dB SNR 32 ©M S Ramaiah School of Advanced Studies - Bangalore
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Effort Required to Achieve a Certain ENOB
33 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Block diagram of the analog-to-digital converter
Number of quantization levels = 2N
34 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Transfer Curve for an ideal ADC and its corresponding quantization error
1LSB =
V 2
REF N
©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Cont… Quantization Error • The analog input is an infinite valued quantity and the output is a discrete value, an error will be produced as a result of the quantization. This error, known as quantization error, Qe, is defined as the difference between the actual analog input and the value of the output (staircase) given in voltage. It is calculated as Qe = Vin-Vstaircase where the value of the staircase output, Vstaircase, can be calculated
VREF = D. = D . Vstaircase VLSB N 2
36 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Cont… Differential Nonlinearity • Differential nonlinearity for an ADC is similar to that defined for a DAC. However, for the ADC, DNL is the difference between the actual code width of a nonideal converter and the ideal case DNL = Actual step width - Ideal step width • Since the step widths can be converted to either volts for LSBs, DNL can be defined using either units. The value of the ideal step is 1/8. Converting to volts, this becomes Videalstepwidth= 1/8 * VREF = 0.625 V= 1 LSB
37 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Cont… DNL Example: Calculate the differential nonlinearity of the 3-bit ADC. Assume that VREF = 5V.
DNL2 = 1.5 LSB - 1 LSB = 0.5 LSB DNL3 = 0.5 LSB - 1 LSB = - 0.5 LSB DNL5 = -0.5 LSB DNL6 = 0.5 LSB
38 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Cont… Missing Codes • It is of interest to note the consequences of having a DNL that is equal to -1 LSB
• The total width of the step corresponding to 101 is completely missing; thus, the value of DNL5 is -1 LSB 39 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Cont… Integral Nonlinearity • Integral nonlinearity (INL) is defined similarly to that for a DAC. Again, a "best-fit“ straight line is drawn through the end points of the first and last code transition, with INL being defined as the difference between the data converter code transition points and the straight line with all other errors set to zero. INL0 = 0 INL1 = 0 INL2 = 0 INL4 = 0 INL5 = 0 INL7 =0 INL3= 3/8- 5/16 = 1/16 or 0.5 LSB INL6= - 0.5LSB 40 ©M S Ramaiah School of Advanced Studies - Bangalore
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ADC specifications Cont… Offset and Gain Error • Offset error occurs when there is a difference between the value of the first code transition and the ideal value of 1/2 LSBs • Offset error is a constant value. the quantization error becomes ideal after the initial offset voltage is overcome • Gain error or scale factor error, is the difference in the slope of a straight line drawn through the transfer characteristic and the slope of 1 of an ideal ADC. 41 ©M S Ramaiah School of Advanced Studies - Bangalore
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Distortion and Linearity • x (t ) = A sin(ωt )
Imperfect (non-linear) system
y (t ) = a1 x(t ) + a 2 x 2 (t ) + a3 x 3 (t )
A Linear System: – Sine wave in = Sine wave out
– Amplitude may be reduced – Phase shifted •
A non-linear system will distort a signal – Sine wave in = Sine wave out+Harmonics at integer multiples of the fundamental frequency
•
This THD (Total Harmonic Distortion) of the signal is a measure of the linearity of the system 42
©M S Ramaiah School of Advanced Studies - Bangalore
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Metrics for Distortion • •
THD = Total Harmonic Distortion Measure of the power of all harmonics relative to the fundamental (usually a full scale input signal)
THD =
THDdB
PHarmonics _ Total PFundamental
V 2 + V 2 + V 2 + ... h3 h4 = 10 log h 2 2 Vf 2
THD% = •
SFDR = Spurious Dynamic Range – Magnitude of the largest harmonic relative to the fundamental – In this case, about 50dB = 0.32%
•
2
2
Vh 2 + Vh 3 + Vh 4 + ... Vf
× 100
1241-2000 THD Spec: compute for first 9 harmonics (h2 through h10)
43 ©M S Ramaiah School of Advanced Studies - Bangalore
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Noise Sources • Interference noise – External sources, not easily controlled • Inherent noise – Many sources (1/f, Thermal Noise, OpAmp Noise, Quantization Noise, Aperture Noise…)
Noise depends on the bandwidth you’re working with.
Resistance noise Erms = 0.13 [R(f2-f1)] µV @ room temp R in MΩ (f2-f1) in Hz To illustrate this over a 50-kHz range, the noise generated by a 10kΩ resistor is around 2.9 µV. Reference voltage
1LSB
2.7v 41.2 µV
3.6v 54.9 µV
5v 76.3 µV
16- bit LSB resolution 44 ©M S Ramaiah School of Advanced Studies - Bangalore
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Total Noise The combined effect of several random noise sources is found by root sum of the squares addition of the rms values of the separate noise sources.
E
=
total
( E12 + E22 + E32 + ...)
The largest noise sources are dominant.
45 ©M S Ramaiah School of Advanced Studies - Bangalore
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System ‘Purity’ Summary • Linearity (THD or SFDR) – Is a measure of how much a system distorts a signal. • Dynamic Range or Resolution – is a measure of the largest signal a system can handle, to the smallest that can be discerned from noise, THD etc. • Both can be expressed in ‘bits’ – (i.e. how accurate would an A/D converter need to be to achieve the same linearity or resolution?) – 8 bit accuracy = 1 in 28 = 0.39% = -48dB – 12 bit accuracy = 1 in 212 = 0.024% = -72dB – 16 bit accuracy = 1 in 216 = 0.0015% = -96dB 46 ©M S Ramaiah School of Advanced Studies - Bangalore
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Analog/Digital Conversion Interface • In order to process an analog signal in the digital domain, we need to convert an analog signal to a digital signal via a process called analog-to-digital conversion, where sampling & quantization are the fundamental processes
• In order to reproduce an analog signal after processing, we use the reverse process of digital-to-analog conversion, where interpolation is the fundamental process
47 ©M S Ramaiah School of Advanced Studies - Bangalore
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Basic Analog-to-digital Conversion Blocks • Sampler – Samples the signal at discrete time intervals
• Quantizer – Approximates the sampled voltage with a level from a fixed set of 2n possible voltage levels via ROUNDING or TRUNCATION
• Encoder – Encodes the measurement in a convenient format for communication or processing
48 ©M S Ramaiah School of Advanced Studies - Bangalore
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Sampling Schemes • Impulse Sampling (Theoretical – not implemented in practice) • Natural Sampling (Theoretical - multiplier is a switch) • Zero-order hold Sampling (Ideal Sample/Hold - instantaneous acquisition time is impractical) • Track/Hold (Real Sample/Hold – Result is sampled and stored in a memory element)
49 ©M S Ramaiah School of Advanced Studies - Bangalore
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So..What Frequency Do I Sample At? •
Generally, faster is better, but ...
•
Limited by physical constraints – Switch resistance – Amplifier settling time – Required component values
Rule of thumb: sample at greater than 10X signal BW
minimises sampling effects (amplitude distortion)
eases the anti-aliasing filter requirements (reduced filter order) 50
©M S Ramaiah School of Advanced Studies - Bangalore
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Common Sampling Rates Which rates can represent the range of frequencies audible by (fresh) ears?
Sampling Rate
Uses
44.1 kHz (44100)
CD, DAT
48 kHz (48000)
DAT, DV, DVD-Video
96 kHz (96000)
DVD-Audio
22.05 kHz (22050)
Old samplers
Most software can handle all these rates.
51 ©M S Ramaiah School of Advanced Studies - Bangalore
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3-bit Quantization A 3-bit binary (base 2) number has 23 = 8 values. 7
Amplitude
6 5 4 3 2 1 0 Time — measure amp. at each tick of sample clock
A rough approximation ©M S Ramaiah School of Advanced Studies - Bangalore
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4-bit Quantization A 4-bit binary number has 24 = 16 values.
14 12 Amplitude
10 8 6 4 2 0 Time — measure amp. at each tick of sample clock A better approximation 53 ©M S Ramaiah School of Advanced Studies - Bangalore
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Quantization Noise Round-off error: difference between actual signal and quantization to integer values…
Random errors: sounds like low-amplitude noise 54 ©M S Ramaiah School of Advanced Studies - Bangalore
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Common Sampling Resolutions Word length
Uses
8-bit integer
Low-res web audio
16-bit integer
CD, DAT, DV, sound files
24-bit integer
DVD-Video, DVD-Audio
32-bit floating point
Software (usually only for internal representation)
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16-bit Sample Word Length A 16-bit integer can represent 216, or 65,536, values (amplitude points). Typically use signed 16-bit integers, and center the 65,536 values around 0.
32,767 0 -32,768
56 ©M S Ramaiah School of Advanced Studies - Bangalore
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Audio File Size CD characteristics… - Sampling rate: 44,100 samples per second (44.1 kHz) - Sample word length: 16 bits (i.e., 2 bytes) per sample - Number of channels: 2 (stereo)
How big is a 5-minute CD-quality sound file?
57 ©M S Ramaiah School of Advanced Studies - Bangalore
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Audio File Size How big is a 5-minute CD-quality sound file? 44,100 samples * 2 bytes per sample * 2 channels = 176,400 bytes per second 5 minutes * 60 seconds per minute = 300 seconds 300 seconds * 176,400 bytes per second = 52,920,000 bytes = c. 50.5 megabytes (MB)
58 ©M S Ramaiah School of Advanced Studies - Bangalore
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Quantization of Continuous Amplitude Signals • A digital signal is a sequence of numbers (samples) in which each number is represented by a finite number of digits (finite resolution) • The process of converting a discrete-time continuousamplitude signal into a digital signal is called quantization • The error introduced in representing the continuousvalued signal by a finite set of discrete values is called quantization error, or quantization noise 59 ©M S Ramaiah School of Advanced Studies - Bangalore
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Unipolar, Linear, Uniform Quantizer (& Binary Coder)
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• “Linear” progression of quantization steps of “Uniform” width • Max. input voltage = Vref • Quantizer step width, ∆, refers to the minimum change in input to change output code by 1, given by
∆=
Vref 2m
• ADC DC specs derived from non-ideal transfer function 60 ©M S Ramaiah School of Advanced Studies - Bangalore
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Effect of Amplitude Quantization •
Quantizer error signal depends on the input signal dynamic range and #quantization levels
•
With high #levels, the error signal is modeled as an additive noise signal with a uniform probability distribution
•
Quantization error signal power is given by it’s variance ∆/2
σe
2
∆/2
∆2 1 = ∫ e p(e)de = ∫ e de = 12 ∆ −∆ / 2 −∆ / 2 2
2
61 ©M S Ramaiah School of Advanced Studies - Bangalore
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SNRq: Quantizer Output Signal-to-Noise Ratio (Full Scale Sinusoidal Input)
• Input Signal: – Full Scale Sinusoid – Peak ampl=Vref/2 • Input signal power:
PAV
( V =
ref
/ 2)
2
2
∆2 2 2 m = 8
• Derivation of SNR
SNRq =
Pav
σ e2
3 2m = 2 2
• Derivation of SNR in deciBELs 3 SNRq (dB) = 10 log10 2 2 m 2 = (10 log10 3 − 10 log10 2) + 20m log10 2
• Quantization noise power:
= 1.76 + 6.02m
σ e2
∆2 = 12
• Real SNR affected by actual quantization noise PDF, as well as harmonics and aperture jitter 62
©M S Ramaiah School of Advanced Studies - Bangalore
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Real ADC Errors • Real ADCs have other errors in addition to the nominal quantization error discussed – Divided into the categories of STATIC & DYNAMIC, depending on the rate of change of the input signal at time of digitization • STATIC errors usually result from non-ideal spacing of code transition levels • DYNAMIC errors occur because of the additional sources of error induced by the time variation of the analog signal being sampled – Harmonic distortion from the S/H stage – Signal-dependent variations in the sample instant – Frequency-dependent variation in the spacing of the quantization levels
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Nyquist Rate Converters • Converters that generate a series of output values in which each value has a one-to-one correspondence with an input value • Note: These converters are seldom run at the Nyquist rate due to the difficulty in realizing practical anti-aliasing & reconstruction filters • In most cases, Nyquist rate converters operate at 1.5 to 10 times the Nyquist rate (i.e. 3 to 20 times the input signal’s bandwidth) • Examples: – Flash – Pipelined – Successive Approximation (SAR)
65 ©M S Ramaiah School of Advanced Studies - Bangalore
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Oversampling Converters • Converters that operate much faster than the input signal’s Nyquist rate (typically 20 to 512 times faster) • Increase the output SNR by digitally filtering out quantization noise that’s not in the signal’s bandwidth • Use noise shaping to place much of the quantization noise outside the input signal’s bandwidth • Example – Sigma-delta
66 ©M S Ramaiah School of Advanced Studies - Bangalore
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Nyquist vs. Oversampling • Major advantage of oversampling ADCs is that they allow the specifications of the input anti-aliasing filter to be relaxed – Lowers the implementation cost
67 ©M S Ramaiah School of Advanced Studies - Bangalore
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68 ©M S Ramaiah School of Advanced Studies - Bangalore
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Which ADC Architecture to Use?? •
Summary & Approximate Ranking:
Characteristic
Flash
Pipeline d
SAR
Sigma Delta
Throughput (samples/sec)
1
2
3
4
Resolution (ENOB)
4
3
2
1
Latency (Sample-to-Output)
1
3
2
4
Suitability for converting Multiple Signals per ADC
1
2
1
3
Capability to convert nonperiodic multiplexed signals
1
2
1
3
Simplified anti-aliasing filter requirements Power Consumption
** Constant
Constant
Scales with Sample Rate
Constant
69 ©M S Ramaiah School of Advanced Studies - Bangalore
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Summary Increasing both sampling time and resolution, the difference between the analog and the digital signals would become negligible • DC Specifications: – Specifications derived from ADC tests using DC/low freq test signals • Gain Error, Offset Error, INL, DNL
• AC Specifications: – Specifications derived from ADC tests using sine wave test signals – SNR, SINAD, ENOB
• In order to process an analog signal in the digital domain, we need to convert an analog signal to a digital signal via a process called analog-to-digital conversion, where sampling & quantization are the fundamental processes 70 ©M S Ramaiah School of Advanced Studies - Bangalore
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Summary Cont… • In order to reproduce an analog signal after processing, we use the reverse process of digital-to-analog conversion, where interpolation is the fundamental process • Sampler – Samples the signal at discrete time intervals
• Quantizer – Approximates the sampled voltage with a level from a fixed set of 2n possible voltage levels via ROUNDING or TRUNCATION
• Encoder – Encodes the measurement in a convenient format for communication or processing
71 ©M S Ramaiah School of Advanced Studies - Bangalore