Control Flow Processors do only one thing:
Interrupt and Exception
From startup to shutdown, a CPU simply reads and executes (interprets) a sequence of instructions, one at a time This sequence is the CPU’s control flow (or flow of control)
Physical control flow Abderazek Ben Abdallah E-mail:
[email protected]
Time
inst1 inst2 inst3 … instn
1
2
Altering the Control Flow
Exceptional Control Flow
Up to now: two mechanisms for changing control flow:
Exists at all levels of a computer system Low level mechanisms
Jumps and branches Call and return Both react to changes in program state
Exceptions change in control flow in response to a system event (i.e., change in system state) Combination of hardware and OS software
Insufficient for a useful system: Difficult to react to changes in system state
Higher level mechanisms
data arrives from a disk or a network adapter instruction divides by zero user hits Ctrl-C at the keyboard System timer expires
System needs mechanisms for “exceptional control flow”
3
Process context switch Signals Nonlocal jumps: setjmp()/longjmp() Implemented by either: OS software (context switch and signals) C language runtime library (nonlocal jumps)
4
1
Exceptions
Interrupt Vectors
An exception is a transfer of control to the OS in response to some event (i.e., change in processor state) User Process OS event
I_current I_next
Exception numbers code for exception handler 0 Exception Table
exception exception processing by exception handler
0 1 2
• return to I_current •return to I_next •abort
n-1
...
code for exception handler 1
code for exception handler 2
... code for exception handler n-1
Examples: div by 0, arithmetic overflow, page fault, I/O request completes, Ctrl-C
Each type of event has a unique exception number k k = index into exception table (a.k.a. interrupt vector) Handler k is called each time exception k occurs
5
Asynchronous Exceptions (Interrupts)
6
Synchronous Exceptions Caused by events that occur as a result of executing an instruction:
Caused by events external to the processor Indicated by setting the processor’s interrupt pin Handler returns to “next” instruction
Examples: I/O interrupts hitting Ctrl-C at the keyboard arrival of a packet from a network arrival of data from a disk Hard reset interrupt hitting the reset button Soft reset interrupt hitting Ctrl-Alt-Delete on a PC 7
Traps Intentional Examples: system calls, breakpoint traps, special instructions Returns control to “next” instruction Faults Unintentional but possibly recoverable Examples: page faults (recoverable), protection faults (unrecoverable), floating point exceptions Either re-executes faulting (“current”) instruction or aborts Aborts unintentional and unrecoverable Examples: parity error, machine check Aborts current program
8
2
Fault Example: Page Fault
Trap Example: Opening File User calls: open(filename, options) Function open executes system call instruction int 0804d070 : . . . 804d082: cd 80 804d084: 5b . . .
User Process
int pop
User writes to memory location That portion (page) of user’s memory is currently on disk 80483b7:
$0x80 %ebx
User Process OS movl
int pop
c7 05 10 9d 04 08 0d
int a[1000]; main () { a[500] = 13; }
movl
$0xd,0x8049d10
OS
exception: page fault
exception
returns
Create page and load into memory
open file returns
OS must find or create file, get it ready for reading or writing Returns integer file descriptor
9
Fault Example: Invalid Memory Reference
c7 05 60 e3 04 08 0d
User Process movl
movl
10
Exception Table IA32 (Excerpt)
int a[1000]; main () { a[5000] = 13; } 80483b7:
Page handler must load page into physical memory Returns to faulting instruction Successful on second try
$0xd,0x804e360
OS
exception: page fault
Exception Number
Description
Exception Class
0
Divide error
Fault
13
General protection fault
Fault
14
Page fault
Fault
18
Machine check
Abort
32-127
OS-defined
Interrupt or trap
128 (0x80)
System call
Trap
129-255
OS-defined
Interrupt or trap
detect invalid address signal process Check Table 6-1: http://download.intel.com/design/processor/manuals/253665.pdf
Page handler detects invalid address Sends SIGSEGV signal to user process User process exits with “segmentation fault”
11
12
3
The `Interrupt Controller’
Interrupt Hardware Legacy PC Design (for single-proc systems)
Ethernet
IRQs Slave PIC (8259)
SCSI Disk
Master PIC (8259)
INTR
x86 CPU
Real-Time Clock Keyboard Controller
Programmable Interval-Timer
I/O devices have (unique or shared) Interrupt Request Lines (IRQs) IRQs are mapped by special hardware to interrupt vectors, and passed to the CPU This hardware is called a Programmable Interrupt Controller (PIC)
Example: Interrupts on 80386 80386 core has one interrupt line, one interrupt acknowledge line Interrupt sequence: Interrupt controller raises INT line 80386 core pulses INTA line low, allowing INT to go low 80386 core pulses INTA line low again, signaling controller to put interrupt number on data bus
Multiple Logical Processors Multi-CORE CPU CPU 0
CPU 1
LOCAL APIC
LOCAL APIC
I/O APIC
Advanced Programmable Interrupt Controller is needed to perform ‘routing’ of I/O requests from peripherals to CPUs
INT: INTA: Data bus:
Responsible for telling the CPU when a specific external device wishes to ‘interrupt’ Needs to tell the CPU which one among several devices is the one needing service PIC translates IRQ to vector Raises interrupt to CPU Vector available in register Waits for ack from CPU Interrupts can have varying priorities PIC also needs to prioritize multiple requests Possible to “mask” (disable) interrupts at PIC or CPU Early systems cascaded two 8 input chips (8259A)
Interrupt #
(The legacy PICs are masked when the APICs are enabled)
4
APIC, IO-APIC, LAPIC
Hardware to Software
Advanced PIC (APIC) for SMP systems
Used in all modern systems Interrupts “routed” to CPU over system bus IPI: inter-processor interrupt
Memory Bus
IRQs 0 idtr
Local APIC (LAPIC) versus “frontend” IO-APIC
PIC
Devices connect to front-end IO-APIC IO-APIC communicates (over bus) with Local APIC
INTR
CPU
0
IDT
vector
Interrupt routing
N
Allows broadcast or selective routing of interrupts Ability to distribute interrupt handling load Routes to lowest priority process Special register: Task Priority Register (TPR) Arbitrates (round-robin) if equal priority
handler
Mask points 255
Assigning IRQs to Devices IRQ assignment is hardware-dependent Sometimes it’s hardwired, sometimes it’s set physically, sometimes it’s programmable PCI bus usually assigns IRQs at boot Some IRQs are fixed by the architecture IRQ0: Interval timer IRQ2: Cascade pin for 8259A Linux device drivers request IRQs when the device is opened Note: especially useful for dynamically-loaded drivers, such as for USB or PCMCIA devices Two devices that aren’t used at the same time can share an IRQ, even if the hardware doesn’t support simultaneous sharing
Assigning Vectors to IRQs Vector: index (0-255) into interrupt descriptor table Vectors usually IRQ# + 32
Below 32 reserved for non-maskable intr & exceptions Maskable interrupts can be assigned as needed Vector 128 used for syscall Vectors 251-255 used for IPI
5
Interrupt Descriptor Table
Interrupt Masking
The ‘entry-point’ to the interrupt-handler is located via the Interrupt Descriptor Table (IDT) IDT: “gate descriptors” Segment selector + offset for handler Descriptor Privilege Level (DPL) Gates (slightly different ways of entering kernel)
Two different types: global and per-IRQ Global — delays all interrupts Selective — individual IRQs can be masked selectively Selective masking is usually what’s needed — interference most common from two interrupts of the same type
Task gate: includes TSS to transfer to (not used by Linux) Interrupt gate: disables further interrupts Trap gate: further interrupts still allowed
Putting It All Together Memory Bus
IRQs 0 idtr
PIC
INTR
CPU
0
IDT
vector
N
handler
Mask points 255
6
