Integrated Results for Dual Low Voltage IC Based High and Low Side Gate Drive

Integrated Results for Dual Low Voltage IC Based High and Low Side Gate Drive Yan Yin and Regan Zane Colorado Power Electronics Center (CoPEC) Departm...
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Integrated Results for Dual Low Voltage IC Based High and Low Side Gate Drive Yan Yin and Regan Zane Colorado Power Electronics Center (CoPEC) Department of Electrical and Computer Engineering, UCB 425 University of Colorado at Boulder, Boulder, CO 80309-0425 [email protected] Abstmct- An IC design for high and low side gate drive is presented based on use of two identical low voltage ICs that provide a low cost alternative to existing high voltage IC drivers. The approach uses a single external coupiing capacitor between the two ICs with on-chip circuitry to provide charge pump power supply and d o f f signaling. Design details are given for each of the core blocks of a custom IC prototype fabricated in a 15 V, 0.8 km CMOS process. Experimental results are presented demonstrating successful drive of P 200 V half-bridge with an LCC electronic ballast and 32 W linear fluorescent lamp (LFL) load.

to drive a complementary half-bridge configuration together with a proposed approach for IC implementation in [9]. In this paper, we present design details and experimental results for a pair of low cost custom low voltage ICs (LVIC) that provide high and low side gate drive in high voltage applications, as shown in Figure 1. Only a single coupling capacitor is required between the two ICs to provide three functions: (1) high voltage isolation, (2) high and low side power suppIy, and (3) signaling to the high side for o d o f f control. Integrated switches are used on each IC to provide active current steering for charge-pump power supply operation and current sensing for signaling detection. The dual LVIC approach provides the benefits of minimal external component count, built-in power supply, low-cost IC fabrication, adaptive dead time control (when operating under ZVS), and high frequency operation. Due to the similarities between the two ICs, only a single LVIC that can be used as either high or low side gate drive was fabricated in a low-cost 15 V capable 0.8 pm CMOS process. The core concept for the dual LVIC gate drive approach was presented in [6], whereas this paper focuses on IC design details and experimental results with the fabricated LVIC.

Key words: high side, gate drive, floating drive, capacitive coupling, charge pump, integrated circuit, electronic ballast


High and low side gate drivers are required in most switching power converters to provide odoff control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the power MOSFET gates to meet timing requirements, provide a floating supply to the high side device, and to create a proper dead time between the switch on states to avoid simultaneous conduction and support zero-voltage switching (ZVS) operation for reduced losses. High voltage isolation may also be required, as is typical in half and full-bridge configurations.

High-side circuit

Many techniques are available for achieving a floating high side gate drive. The pulse transformer [1,2] is frequently used for isolation and can be used as a floating gate drive. However, in high frequency switching converters operating from hundreds of kHz to MHz, the advanced magnetics and additional passive components required for high efficiency operation become prohibitively expensive. High voltage IC (HVIC) technologies are also frequently used for gate drivers due to their ability to directly drive the floating high side through advanced processing for high voltage isolation [3,4]. Advantages of HVIC based drivers include a high level of integration with few external components and independent high and low side control. However, HVIC drivers suffer at high frequencies from significant heating due to static and dynamic losses of the level-shifting circuitry and dynamic losses of the. high side isolation well capacitance. Recent designs using discrete charge pump circuitry [5,6],PCB based transductor [7] and piezoelectric transformers [7] have also been presented. In [SI,a floating gate drive circuit is described


This work is co-sponsored by the National Science Foundation (under Grant No. 0348772), General Electric Global Research (through CoPEC) and the Department of Energy's National Energy Technology Laboratory (under Cooperative Agreement DE-FC26-OZNT4 1252).

~7803-8975-1/05/$20.00 Q2005 IEEE.


Figure 1. Dual-LVIC based gate drive concept applied to a half-bridge circuit. Switches SI & S3 provide charge pump and signaling, and switches S2& S4 provide gate bive.

We begin in Section I1 with a brief review of the dual LVIC concept. Design details are given for each of the core blocks of the custom IC prototype in Section 111, followed by experimental results demonstrating successfid drive of a 200 V half-bridge with an LCC eIectronic ballast and 32 W LFL load. Our conclusions are summarized in Section V. 11. DUAL LVIC GATEDRIVE CONCEPT Figure 1 shows a simplified diagram for the dual LVIC gate drive concept applied to a half-bridge switching network (could also be used in hli-bridge and other floating high side topologies). A capacitor is empIoyed to interface the high side and low side drivers. A single-pole double-throw (SPDT) switch is used in both low side (SI)and high side (S3) circuits (ICs) to switch the coupling capacitor between Vd and its referred ground to position the switches for charge-pump operation and to generate the signaling currents. Another SPDT switch (SZ & S$ is used to drive the gate of each power device. The operation of the gate driver can be described in four states for the half-bridge configuration based on the status of the midpoint voltage V, as shown in Fig. 2. The switch timing VLic



@) Rising transition VdC

Figure 3. Coupling capacitor current waveform for ZVS operation as a function of time. The switching instances for SI- S4 are designated and the current pulses are numbered according to the labeling in Fig. 2.

and resulting coupling capacitor current are key to understanding system operation. The capacitor current pulses associated with each state are labeled in Fig. 2 with numbers, 1-6, and Fig. 3 shows the capacitor current as a function of time for each o f the six current pulses together with the switching instances and operating states under ZVS conditions.

A . Low Side On State Under this state, the low side gate is on with SItied to Vu,, and the high side gate is off with S j tied to Vdd,,, as illustrated in Fig. 2(a). As the midpoint voltage V,,, is zero (constant), no current flows through the coupling capacitor C,.

B. Rising Transition State This state refers to the rising transition of V,,,. Following the command from the controller, SI is first switched from V,, to Yd., as shown in Fig. 2(b), which generates a pdse current (defined as “signaling current”) pumped up to the high side through C,, as shown in Fig. 3. The high side controller, after sensing this signaling current, switches S3 from Vdh to V,, to generate another pulse (defined as “handshaking current”) that also flows through C,.Following detection of the handshaking current, the low side controller switches S2to Vss,to turn off the law side gate immediately (or enters a fault condition if no handshaking current is received). In applications where the half-bridge is used to drive a resonant tank under ZVS, the midpoint voltage V,,, will then increase, charging the coupling capacitor C, as well as the low side energy storage capacitor C,. As a result, a large transition current flows through the coupling capacitor, which i s also shown in Fig. 3. After a fixed deadtime, the high side controller turns on the high side gate with soft switching by switching S4 from Vssh to V&. If the converter does not operate under ZVS, the high side gate will be forced to turn on after a fixed deadtime with hard switching, which will create a transition current with higher amplitude and shorter time through the coupling capacitor. C. High Side On State

This state comes right after the rising transition state. It is similar to the low side on state except the high side gate is on with SItied to V& and S3 tied to Vssh as shown in Fig. 2(c). V,,, is tied to the dc bus voltage and no current flows through C,. I

------ - - - - - - -

D.Falling Transifion State This state refers to the falling transition of V,,,. At the end of the switching period, the low side controller switches SI from

(d) Falling transition Figure 2. Four operation states for LVIC based gate driver.


Val to V,, according to the control command, generating a signaling current, which is opposite to the one in the rising transition. In a similar way to the rising transition, the high side detects this pulse and switches S3 from VSJb to V a , resulting in the handshaking current. The high side gate turns off, triggering the falling transition of V , if the converter operates under ZVS. The energy stored in the coupling capacitor is then transferred to the high side energy storage capacitor C,. The low side controller detects the handshaking current and waits for a deadtime, then tums on the low side gate to lead the system into the low-side-on state. If the converter does not operate under ZVS, the low side turn-on will be hard switching, which is similar to the high side turn-on in hard switching.

Figure 3 iIlustrates the waveform of the current flowing through the coupling capacitor, which is hdamental to the operation of the dual LVIC gate driver. The signaling and handshaking currents are used for communication between the low and high side ICs, and the transition currents supply energy to both ICs. It can also be seen that the coupling capacitor blocks dc bus voltage (up to several hundred volts) when the high side gate is on. Hence, this coupling capacitor implements three hctions: high voltage isolation, communication interface between the IOW and high side ICs, and charge pump power supply. Extensions for adaptive deadtime control are presented in [ 11] based on detection of the transition current, but were not included in the prototype IC. .

operation to sequence operation states a) through d) and recognizes reset and start-up commands from voltage regulator. The CMOS switches are only required to withstand the gate driving voltage, typically between 8 V and 15 V. This allows use of standard CMOS technologies to leverage high-volume processing for low-cost implementation, which is in contrast to the HVIC approach where the silicon must withstand up to 600 V and requires custom processing techniques. Each of the core IC blocks are described in more detail below. A . CMOS Switches The CMOS switches illustrated in Fig. 4 (MI-M4) are used to drive the power switch and the coupling capacitor, with the layout shown in Fig. 5. As these switches operate with high voltage (8 V 15 V), they are implemented with mid-oxide DMOS technology. The sizes of these switches are chosen based on the requirements for gate driving, capacitor switching, and current conduction. The gate drive switches M, and M4 must provide sufficient driving capability for fast switching of the power gates. The capacitor drive switches MI and M2

111. CUSTOM IC DESIGN A simplified block diagram of the custom IC is shown in Fig. 4. The high and low side gate drivers use identical hardware with a single selection pin to adjust digital statemachine selection and threshold parameters for proper operation. The core bIocks are the four main switches MI and Mz (implementing SI and S3 in Fig. 1) and M3 and M, (implementing S2 and S4 in Fig. l), bi-directional current mode detectors and comparators, and digital control logic. Additional supervisory functions and a voltage regulator are also included on the IC. The digital control logic performs state-machine



Figure 5. CAD layout of the primary nmos (MI& M,)and pmos (MI & M4) switches. Special care was taken to capture body diode current and cbannet all current directly to the power pads. Multiple guard rings and independent pad connections were used to reduce substrate and power supply noise on the mixed-signal IC.


--‘ d

-- ---

signaling current hndshaking current


Figure 6 Signalrng and handshaking current polarities in the LVlC and HVIC switches M Iand M2.

determine the on-resistances and parasitic capacitances of these devices, which affect the switching speed as well as the magnitude and width of the signaling and handshaking currents. Due to similar requirements €or both sets of switches, we chose to use the same nmodpmos pair for gate drive and capacitor drive. A primary chalIenge in the layout is that in both functions (gate and capacitor drive), significant current flows in both directions. This creates concems for system noise and body diode conduction effects on the remaining mixedsignal circuitry in the IC. For this design, the nmos is sized as 1.5 mm I 2 pm with Ron = 20 a, and the pmos is sized as 3 m m / 2 pm with R,,, = 25 Q, Special care was taken in the device layout to capture stray body diode currents and channel all currents directly to the power pads, as shown in Fig. 5. B. Current-Mode Detector & Comparator The current-mode detectot illustrated in Fig. 4 detects the signaling and handshaking currents during the rising and falling transitions. If adaptive deadtime controi is desired, the current detector also needs to detect the transition current. In this design, a fixed deadtime is used in order to first validate the core operating concepts and high risk components.

v, Figure 7. Schematic diagram of the bi-directional current detector for the nmos switch MI. A bias offset and voltage mirror circuit were used to sense and scale the large positive and negative currents in M Iwith less than 10 ns delay. A direct dual of this circuit was used for sensing bi-directional currents in the pmos device Mz.

vB across & to match the voltage vA, which equals the voltage across the primary device M Iplus a dc offset to accommodate negative input currents. The dc offset is created by Mj and a bias current lb.The output current of the detector is given by (for ii. >> I),I,)

= 1 / 300 and Ib = 100 pA in the IC design. The scale factor is achieved using matched devices with care taken in the layout for good matching and reduced noise.

where RI / Rt

The detector current Is then passed to a high-speed currentmode comparator [12], with the schematic shown in Fig. 8. The reference current in the comparator sets the current detection thresholds and is pre-programmed based on LVlC or HVIC operation. The thresholds correspond to input currents of +45 mA for LVIC mode and -15 mA for HVIC mode. The lower current threshold was required in HVIC mode to guarantee detection before body diode conduction clamps the detection point. The output of the comparator vd,, is input to the control logic to drive state transitions. The comparator operates on the intemal Vd5 supply from the voltage regulator to interface with the low voltage digital logic (5 V). The circuitry and operation of the pmos detector are a direct dual of the nmos detector described in Fig. 7.

The primary challenges in detecting currents in the capacitor switches include high speed requirements {order of 10 ns delay), bi-directional current detection, and the ability to withstand and quickly recover from large negative currents caused by mid-point transitions. Consider for example M, in Fig. 4. As a LSIC, the handshaking current flows positive from drain to source and the large transition current flows negative from source (ground) to drain, As a HSIC, the signaling current flows negative from source to drain. Thus to use the same hardware for both ICs, the circuit must be capable of detecting both positive and negative currents. The current polarities are shown for all switches in Fig. 6 (note that the HSIC detects signaling currents and the LSIC detects handshaking currents). A partial schematic of our solution is shown in Fig. 7 for detecting the signaling and handshaking currents flowing through the nmos switch (MI in Figs. 4 and 7). The basic concept is that MI, Msand Ms operate in the on-state (triode) when the detector is active and are modeled as resistors RI and R2 as shown in Ftg. 7. We then create an output current proportional to lhe sensed input current by forcing the voltage

C.Conwol Logic The control logic performs the state machine operation based on the control input and the outputs of the current detectors to generate the control signals for the switches. It also needs to handle fault conditions to avoid the simultaneous conduction of both power switches. The logic circuit is


Figure 8. Schematic diagram of the fast current-mode comparator circuit [12].Feedback is used to maintain a low impedance input node for high speed response with output buffers for sharp output edges.

initiated by the reset command from the voltage regulator under voltage lock out (UVLO) circuit. Since the current polarities and detection pulses are different for the LVIC and HVIC designs as shown in Fig. 6, separate state machines are used for each. The control Iogic are described in Verilog and then synthesized to the gate-level schematics through Cadence PKS (physically knowledgeable synthesis) and auto place and route. The LSIC state machine is shown in Fig. 9, where state transitions are edge triggered by the current comparator outputs vde1-" and vdelp We chose to use these asynchronous signals for state transitions due to the ns speed requirements associated with signahg detection and response. A traditional synchronous clock state machine design would require a very high frequency clock with significant power consumption and on-chip EMI. The statc transitions operate as discussed in Section 11, with selection pins used for pre-programmed parameters initial-time (at startup), fouIt-rime (time-out for expected transitions), musk-time (masking of known high noise periods during transitions to avoid fake detection) and deadtime (for gate drive). For the LSIC, the C Q output ~ is a direct logic inverse o f the gate drive control input. The HSIC state machine is shown in Fig. 10 with similar transition and parameter control as the LSIC, although the cap output is driven by the state machine in the HSIC.

cap = I

- J

Figure IO. State transition diagram for the HSlC

Figure 1I . Micro-photograph of custam IC fabricated in the AMS 0.8 pm CMOS process with core blocks labeled.

D.Auxiliav Circuits Auxiliary circuits necessary for IC implementation are also included. A level-shifter is required to convert the outputs of the control logic from 5 V to Y d (8 V 15 V) to drive the switches. A buffer made up of a chain of sized-up inverters is interfaced between the level-shifter and the gates of the switches to improve the driving capability. A linear voltage regulator is implemented on-chip to generate the 5 V supply for the digital logic and bandgap bias voltages and currents for the current detector. The voltage regulator also includes a poweron-reset module (UVLO), which creates a reset signal to initiate the state machine when the power supply is building up. A 20 MWz on-chip clock is implemented to generate the selectable timing constants.

A micro-photograph of the complete custom IC fabricated in the Austria-Microsystems (AMs) 0.8 pn CMOS process is shown in Fig. 11 with each core hnctional block labeled. Figure 9. State transition diagram for the LSIC



High Voltage DC!BUS

Figure 12. Experimental setup for demonstrating dual LVlC operation with a 200 V half-bridge circuit driving an LCC electronic ballast (L = 3.5 mH, C = 6.8 nF (both)) and 32 W LFL load. 15 V Zener diodes were used with 0.1 mF supply capacitors. Coupling capacitor (between the two ICs) values were successfully tested from 200 pF to 800 pF.

Iv. IZXPERIMENTAL RESULTS The experimental setup is shown in Fig. 12, where two identical LVICs are used to drive a 200 V half-bridge circuit. We chose to demonstrate the IC results in a resonant LCC electronic ballast application driving a 32 W, 40 kHz LFL load in order to validate the design in a dynamic environment with a nonlinear load and significant radiated EMI. Selection pins were used to designate LSIC and HSlC operation with timing parameters set to: initial-time: 1 ms, fault-rime: 20 ps, mask-time: 5 ps, and deadtime: 600 ns. Results demonstrating signaling and handshaking behavior between the two ICs are shown in Fig. 13. The two waveforms show the voltages 011 the two sides of the coupling capacitor.

The pulses in these voltages are proportional to the current pulses in the coupling capacitor as the current flows through the on-resistance of the on-chip devices. Figure 13 shows the results for the rising transition under ZVS conditions (reference Figs. 2(b) and Fig. 3). First, the LSIC switch SI goes high, which positions the LSIC charge pump and signals to the HSIC. Following detection of the current pulse, the HSIC switch S3 goes low, positing the HSIC charge pump and providing a handshaking pulse to the LSIC. The LSIC gate switch Sz then goes low, initiating a rise in the mid-point voltage V , (due to ZVS). After a deadtime, the HSIC gate switch S4 goes high (not shown on this time scale). Figure 14 demonstrates steady-state operation of the system driving the LFL at full power and Fig. 15 shows the lamp ignition sequence. Note in Fig. 15 that the dual LVIC design operates with continuous successful communication during the significant dynamics associated with lamp ignition, including hard switching for the first few switching cycles and significant radiated EMi during lamp ignition.

v. CONCLUSIONS We have presented design details and experimental results for a custom gate drive LVIC that has the potential of delivering a low-cost altemative to HVIC high and low side gate drives in high voltage applications. The approach is based on use of a single coupling capacitor to provide three key functions: high voltage isolation, high and low side power supply, and signaling to the high side for o d o f f control. The prototype IC was fabricated in a low-cost 15 V capable 0.8 pm CMOS process and includes all of the core blocks necessary for independent operation. The design offers the benefits of minimal external components, built-in power supply, low-cost IC fabrication and simple extensions for adaptive dead time control and high frequency operation. Experimental results demonstrate robust performance driving a 200 V half-bridge circuit with an LCC electronic ballast and 32 W LFL load. T&




. .

. .

Lamp Voltage


:. , , , 3 . . . i . , i , . , ; . . . iI 10.0 V


4 Chl



Figure 13. Experimental results showing the two sides of the coupling capacitor pin (LS and HS) during signaling associated with the rising transition. The voltage steps indicate the capacitor currents predicted in Fig. 3, with the LSiC signaling and the HSIC responding with a handshaking pulse. Following the handshaking response, the LSIC turns off, creating the rising waveform of the HS Cap Pin seen due to ZVS operation (with a 200 V

Figure 14. Experimental results demonstrating steady-state operation driving a 32 W electronic ballast with an LFL load. The LS Cap Pin (Ch. I) shows short spikes during each transition due to the charge pump supply current. Inductor current and midpoint voltage wavefoms show ZVS operation.

dc bus).


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D.Vasic, F. Costa, E.

Figure 15. Experimental results demonsbating successhl opeartion during the dynamics and EM1 associated with lamp ignition. The midpoint voltage (Ch. 2) operates without a glitch through the high voltage lamp ignition and transient response, demonstrating robust operation of the dual LVIC prototype in hard and soft switching. ACKNOWLEDGMENT

The authors thank Arseny Dolgov for his work as an

undergraduate research student on this project in designing the test boards and generating all experimental results.

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