INSTRUCTION ADDRESSING MODES

sc02.qxd 11/23/2002 12:11 PM Page 660 SUPPLEMENTARY CHAPTER 2 INSTRUCTION ADDRESSING MODES Irv Englander and Benjamin Reece sc02.qxd 11/23/20...
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SUPPLEMENTARY CHAPTER 2

INSTRUCTION ADDRESSING MODES

Irv Englander and Benjamin Reece

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S2.0 OVERVIEW Most of the instructions in a typical program will manipulate data. The data may be variable data, constants, addresses, or even arrays of data. The manipulations consist of movement from one location in the computer to another, calculations, shifts, and various other operations. The data may be stored in memory, or it may be located in various programmer-accessible registers. Much of the power of the instruction set in real computers comes from the ability to manipulate data quickly, flexibly, and efficiently. In the Little Man Computer, only a single method of addressing memory was provided, and only one register was available to the programmer. The method used in the Little Man Computer is known as direct, absolute addressing. In real computers, instructions address registers and memory locations in a variety of ways. Each of the terms used to describe the Little Man instruction, direct and absolute, has its own meaning. There are also alternatives to each term. The term direct refers to the fact that the data is reached directly from the address in the instruction. This might suggest to you that there could be an indirect mode of addressing— you would be correct in such an assumption. The term absolute means that the address given in the instruction field is the actual memory location being addressed. In other words, if the address in the instruction field is 49, then the data is located at memory location number 49. It would be possible to have an addressing mode in which an offset is added to the specified address, in which case the address specified would actually be relative to the offset. If the offset were 120, for example, and the address in the instruction field were 49, the actual address where the data is to be found would be 120 + 49, or 169. Although it is possible to program using only direct absolute addressing, it adds convenience and flexibility to have available other modes of addressing. You have already seen that one important reason to provide additional addressing modes is that to do so allows a much larger range of addressable memory while using a reasonable number of bits for the address field. Another important reason is that additional addressing modes also can make it much easier to write certain types of programs, such as loops that use an index to address different entries in a table or array. Finally, as noted before, most modern computers provide a number of programmer-accessible registers. These machines will usually contain instructions that move and manipulate data directly between registers. Register-based instructions execute faster because the time required to access data from memory is eliminated. For these reasons and others, most computers provide several different modes for addressing memory.

S2.1 REGISTER ADDRESSING Register addressing has the advantage that it is implemented directly as part of the CPU. As shown in Figure S2.1, the fetch-execute cycle for a register-to-register move

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instruction can be reduced to the four steps shown. The contents of the source register specified in the instruction can be moved directly to the destination register without a memory access. Since the step that adjusts the PC for the next instruction can be performed in parallel with earlier steps, only three time units are required for this instruction. Obviously, instructions that do not require a memory access can execute faster. This suggests that frequently used data could be loaded from memory into a register and left there. The programmer’s goal would be to minimize the use of memory referencing instructions and use registers alone for most operations. This technique can significantly speed up program execution. As noted earlier, RISC machines provide an instruction set made up almost entirely of register operation instructions in order to achieve high program execution speeds. For this purpose, RISC machines are equipped with a larger than usual number of registers.

S2.2 ALTERNATIVES TO ABSOLUTE ADDRESSING As previously stated, all the addressing in the Little Man Computer is absolute. The address specified in the instruction refers directly to the address of the data. Alternatives to absolute addressing are designed to allow the addressing of large amounts of memory while maintaining a reasonably sized instruction word address field. Most program code executes within a relatively small area of memory that changes as the program proceeds. This is true because well-written programs tend to be modular, with local variables. Loops and conditional branches are usually confined to a fairly small area of program code; therefore, most program jumps tend to be short. This suggests that a small address field would be adequate, provided that there is a way to move the entire area that the address field references at a given time. This concept is illustrated in Figure S2.2. There are several different ways of modifying the address in the address field to accomplish implementing a large memory address space with a small instruction address FIGURE S2.1

FIGURE S2.2

Fetch-Execute Cycle for Register-toRegister Move Instruction

Moving the Address Space to Address More Memory

PC MAR MDR IR contents(IR[add1]) contents(IR[add2]) PC + 1 PC

Program example .. .. . Procedure. first .. ..

(Active area during procedure first) (Active area during procedure second)

Procedure. second .. .. Procedure third .. .. .

(Active area during procedure third—notice that overlap is possible) Addressable memory

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field. The most common ways are known as base offset addressing, or base register addressing, and relative addressing. Effectively, each of these methods works by providing a starting address and an offset, or displacement, from the starting point. The starting address could be stored in a register and the address field of the instruction then becomes the offset. (Note, incidentally, that a different way to look at absolute addressing is to recognize it as just the case where the starting address is fixed at zero.) There is a programming advantage to using one of these movable starting address methods. If all of a program’s memory referencing instructions will be specified as displacements rather than as absolute addresses, it will be possible to move the entire program to a different location in memory without changing any of the instructions. This means that a program can be loaded into any part of memory that is convenient. As you will understand when we explore the operating system in Part IV of this book, this feature, known as relocatability, is important to the efficient use of the computer. Base offset addressing is illustrated in Figure S2.3. A base register is used to set an initial address value. The final address for each instruction is established by adding the address field of the instruction to the base address. A new block of addresses can be established at any time simply by loading a new value into the base register. On some machines, the base register may be a special, separate register reserved for the purpose of base offset addressing; on others, the general purpose registers can be assigned for this purpose. In either case, the base register is generally quite large, which provides the capability of a large memory space. It is not uncommon to provide memory capacities of several gigabytes using this technique.

EXAMPLE

The IBM zSystem allows use of its 16 64-bit general-purpose registers as base registers. The number of the selected base register is contained in the instruction word along with a 12-bit displacement value. The 12-bit displacement allows a range of 4096 locations from the base value. The displacement value is added to the value in the base register to determine the absolute address of the data. The format used for a load instruction is shown in Figure S2.4.

FIGURE S2.3 Base Register Address Creation Base register

1375

1 20 1375

+

Instruction

20

= 1395 actual location

FIGURE S2.4 Load Instruction Format op code reg # index base # displacement bit 0 7 8 11 12 15 16 19 20 31

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In this format the register number is the number of the general-purpose register where the data from memory is to go, and the base number is the number of a different generalpurpose register that holds the base address value. For now, we’ll ignore the index field and assume that the index value is 0; we’ll deal with indexing in the next section of this chapter. Suppose that general-purpose register 3 is being used as the base value register and that data is to be loaded from memory into register 6. Then if register 3 has the value 1 C 2 5 E 016 and if the displacement for this instruction is 3 7 A16, the absolute address of the data to be loaded will be 1 C 2 5 E 016 + 3 7 A16 = 1 C 2 9 5 A16 The instruction word for this example will be Op code 58

6

Base register 0

3 37A

Destination register

Displacement

The Intel X86 architecture offers several different types of base register addressing. One method uses two registers, BX and BP, as base registers. A second method was used in early models of X86 architecture to handle the limitations of a 16-bit address space. This method is still provided in later models of the X86 series, and is now known as real mode addressing. Real mode addressing defines a 64KB region of memory as a paragraph. The value stored in a 16-bit segment register is shifted left 4 bits and added to the address, providing a 20-bit address. With this method, the programmer can address 1MB of memory, 64K at a time. X86 addressing methods are discussed further in Chapter 12. Another method for constructing a block of addresses is to create addresses relative to the current instruction being executed. The desired address consists of the value in the address field added to the value in the program counter. This technique is known as relative addressing. As an example, suppose the computer is presently executing the instruction in memory location 46 (i.e., the program counter is set to 46). If the address in the instruction address field is 03, the data would be found 3 locations up from 46 in memory location 49. You might be interested in noticing that relative addressing is similar to base offset addressing with the program counter being used as base register. Notice that in relative addressing the address field must be capable of both positive and negative numbers; otherwise, it would be impossible to jump backward in loops. Thus, the address field must be capable of storing and manipulating complementary numbers. Notice also that the block of addresses created using relative addressing moves with each instruction that is executed, because the program counter changes. When the program counter is 50, the same LOAD RELATIVE 3 instruction now refers to location 53. Both techniques allow the addressing of more memory with a given address field size than would be possible with absolute addressing. The trade-off is the inability to reach data at distant locations outside the range of the address without modifying the base location or using some alternative to direct addressing. In relative addressing, the

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base is implied by the location of the instruction itself, and other techniques must be used to extend the range of addressing when the data is outside the range for a particular instruction. Indirect addressing, which is discussed in the next section, is useful for this purpose. The fetch-execute cycle for each of these address modification techniques is similar. The relative addressed ADD instruction in Figure S2.5 is typical. The only change from the fetch-execute cycles that you have previously seen is the addition of the program counter in step 3. For base displacement addressing, the value in a base register would be used in step 3 of the cycle instead of the value in the program counter.

S2.3 ALTERNATIVES TO DIRECT ADDRESSING Any of the techniques used to determine the absolute address that we have discussed can be used with direct addressing. With direct addressing the absolute address, as established, becomes the address where the data is to be found. There are also useful alternatives to direct addressing. Before we explore alternatives to direct addressing, let us consider the features and advantages of direct addressing itself. One important feature and advantage of direct addressing is that it separates the data into a location different from the location of the instruction itself. This provides two major benefits to the programmer: 1. The data can be changed without affecting the instruction itself. This is important since most program data actually represents data variables, which of course change as the program progresses. 2. The data is available to be used by different instructions. This would not be the case if the data were located within the instruction word itself. These benefits mean that a variable can be assigned to a particular location in memory independent of the various instructions that refer to that data. You should be particularly aware of an important conceptual difference between the alternatives used to determine an absolute address discussed in the previous section and the address modification operations that will be discussed in this section. Although both groups of addressing techniques alter the final address where data is to be found, the primary objective of alternative techniques that are used to build the absolute address is to allow access to a large memory space in an efficient manner. The operations discussed in this section start from the absolute address previously obtained and modify that address to allow the programmer to improve the efficiency of common programming operations, such as programming loops. While the different types of absolute addressing operations are used generally, and are applied to most instructions, the FIGURE S2.5 techniques discussed here are usually applied to a smaller number of individual instructions. Thus, the different addressing modes available to a Fetch-Execute Cycle for programmer are usually variations on direct addressing and its alternatives. Relative Addressing PC MAR MDR IR IR[Address] + PC MDR + A A PC + 1 PC

Immediate Addressing MAR

On occasion, it would be acceptable and convenient to store the data within the instruction itself. This would be the case if the data is a constant. This technique is called immediate addressing.

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Figure S2.6 is an example of a LOAD instruction with immediate addressing in a modified Little Man Computer. The modified computer uses a four-digit instruction; the additional digit is used to indicate the addressing mode being used. You could consider the addressing mode as part of the op code, but most computer vendors separate the addressing mode from the op code. In the figure, we have used addressing mode 1 to indicate immediate addressing. Notice that the size of the constant is limited to the size of the address field, in this case, two digits. In this example, the number 005 will be loaded into the calculator. It is usually desirable to provide for negative numbers as well as positive numbers, so the range of values is necessarily limited even more. Complementary representation is used for this purpose. Since the data is located in the address field of the instruction, the additional memory access for obtaining the data is not required. Thus, this instruction executes faster, which may be useful if the instruction is within a loop that will be executed many times in a program. The fetch-execute cycle is simplified to the steps shown in Figure S2.7. Compare these steps with the steps used for direct addressing, described in Section 7.4. An instruction with immediate addressing is capable only of manipulating constant numbers unless the instruction itself is changed. Since it is usually undesirable to change an instruction during the execution of a program (if one forgets to change it back, the program will execute differently the next time it is executed), immediate addressing is of limited use. It could be used for adding a constant to an expression, however. Notice that if the computer provides a variety of addressing modes, the instruction word must include extra bits so that the computer can identify the addressing mode to be performed. In some computers 1 or 2 additional bits is sufficient to indicate the addressing mode, but in other computers 3 or 4, or even more, bits are required for this purpose. FIGURE S2.6 Example of LMC Immediate Addressing op code

addressing mode 1 (LOAD)

FIGURE S2.7 Fetch-Execute Cycle with Immediate Addressing PC MAR MDR IR IR[Address] A PC + 1 PC

1

address field

05 (the number 005)

Indirect Addressing As we previously indicated, direct addressing separates the location of the data from the location of the instruction. On many occasions it is desirable to go one step farther, to separate the address of the data from the instruction. This will be the case when the address of the data itself varies during the execution of the program. The most obvious example is the use of subscripts to describe a data table. Each subscript value points to a different data value. In this case, the address field of the instruction will contain the address of the address of the data. The address of the data can change to reflect the current subscript, without having to modify the address that is part of the instruction word. Figure S2.8 shows a typical table of data as stored in memory. You can see that to address the various elements of the table, it will be necessary to change the address that loads the data.

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FIGURE S2.8 Storage of a Typical Table of Data Memory address 77 78 79

Data 136 554 302 . .

EXAMPLE

Table subscript TABLE(1) TABLE(2) TABLE(3)

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Figure S2.9 illustrates the steps used by the Little Man to find the address with indirect addressing. When the Little Man first reads the instruction (Figure S2.9a), he realizes that he must go to the address in the instruction to find the address of the data. Next (Figure S2.9b) he retrieves the address of the data. Had this been a direct addressing instruction, this location would have contained the data, but since it is an indirect instruction, the Little Man knows that he must go one more step removed. In Figure S2.9c, the Little Man has gone to the address indicated, and he can now retrieve the data. Note that if we have the Little Man execute the exact same instruction, but change the address pointer in step (b), that he will retrieve a different set of data. This is shown in Figure S2.9d.

Suppose the modified Little Man is to execute the indirect

ADD

instruction

3245 where the addressing mode digit value of “2” stands for indirect and 45 is the usual absolute Little Man address. Assume the following data prior to execution of the instruction. Which values will change and what will be the new values after the instruction is executed? Aold ➝ 357 mailbox 45 ➝ 079 mailbox 79 ➝ 210 A normal, direct addressed instruction would expect to find the data in mailbox 45 as specified in the address field of the instruction. In this case, however, the instruction calls for an indirect address. Thus, the value in mailbox 45 is actually the address of the data, which is 79. Looking at mailbox 79, the data value is 210. Adding 210 to the previous value in A gives a new value Anew ➝ 567 No other value is changed by this instruction.

As previously mentioned, one important application for indirect addressing is the indexing of subscripted tables. Observe from the previous example that incrementing the “data” value in mailbox 45 would mean that the next time the ADD instruction is executed, it would get its data from mailbox 80 instead of from mailbox 79. Can you see that this technique could be used easily to add a column of subscripted numbers? It would be possible to address a table of values using direct addressing, but to do so would require modification of the address field in the instruction. Since the computer does not distinguish between an instruction and data, it is possible to treat the instruction as data, and thereby modify its address field. This is illustrated by the program segment with comments shown in Figure S2.10. This program segment adds 20 numbers, stored in mailboxes 60–79, and then outputs the result. This segment is an example of the steps required to add the data in a table, using direct addressing. Trace this segment carefully. Notice in steps 09–11 that the instruction in location 07 is treated as data, incremented, and replaced to its original location.

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FIGURE S2.9 Little Man Indirect Addressing

3245

25 3245

45 79

a. The Little Man reads the instruction

79 210

25 25 3245 79

b. ... he finds the address of the data

45 79

79 210

210

25 3245

45 79

25

c. ... from that address he retrieves the data

79 210

25

80/559

25 3245

45 80

d. ... with a different address in location 45, he retrieves different data

79 210 80 559 25

We briefly mentioned the technique of modifying instructions “on the fly” when we discussed immediate addressing. This technique of programming is known as impure coding. It has two major disadvantages. First, since the instruction must be changed during execution of the program, it is not possible to store this program in read-only memory. Second, special care must be taken to assure that the instruction is restored to its original value before the program is executed again. This is a potential problem if the program might be interrupted in the midst

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FIGURE S2.10 A Totalizer Loop with Direct Addressing Mailbox 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 90 91 92 93 98 99

Instruction

Comments

LOAD 90 STORE 07 LOAD 91 STORE 99 LOAD 92 STORE 98 LOAD 99 0 STORE 99 LOAD 07 ADD 93 STORE 07 LOAD 98 SUB 93 BRP 05 LOAD 99 OUT COFFEE BREAK ADD 60 0 19 1

/this actually loads “ADD 60”.. /..into mailbox 07 /initialize the totalizer /initialize the counter to 19 /load the total / [ADD 60, ADD 61, etc.] /and store the new total /modify the instruction in 07.. /..by adding 1 as though the.. /..instruction were data /decrement the counter /loop back if not done /done.. /..output the result /initial data for location 07

/used to hold the current count /used to hold the current total

of execution. Proper initialization is the purpose of instructions 00–01 in the figure. Programs that modify themselves during execution are considered risky. Pure code is defined as program code that does not modify itself during execution. The same program segment is shown using indirect addressing with a modified Little Man instruction set in Figure S2.11. We have used an asterisk to indicate that the instruction code includes indirect addressing. No asterisk means that the instruction is a normal, direct addressing instruction. (Obviously, this is not a representation we could really use in an LMC.) Notice that in this example, the instruction is never modified. The address, which is incremented each time, is stored in the separate data region. This has an important secondary advantage: the instructions for the program could, if desirable, be stored in ROM, with RAM used for the address of the data and for the data itself. You should study these examples carefully to understand how indirect addressing is used in this application.

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FIGURE S2.11 The Same Totalizer Loop with Indirect Addressing Mailbox 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 90 91 92 93 97 98 99

Instruction

Comments

LOAD 90 STORE 97 LOAD 91 STORE 99 LOAD 92 STORE 98 LOAD 99 ADD *97 STORE 99 LOAD 97 ADD 93 STORE 97 LOAD 98 SUB 93 BRP 05 LOAD 99 OUT COFFEE BREAK 60 0 19 1

/this time just the initial /..address is saved /as... / ... /...before / this is the indirect instruction /modify the address in 97 (this is direct) /..by adding 1 to it ... /as... / ...

/...before /now this is the initial address

/used to hold the address of the data /used to hold the current count /used to hold the current total

A parenthetical note: If you have been exposed to the concept of pointers in Pascal or C, you have probably recognized the fundamental similarity between indirect addressing and the use of pointers. There is one other important application for indirect addressing that should be mentioned. When an instruction requires data from outside the current range of one of the absolute addressing methods, or when a long jump is required, the indirect addressing technique can be used to reach the desired address. As an example, suppose the modified Little Man Computer uses a base register system to address 10 paragraphs of 100 locations each. A JUMP INDIRECT instruction would be able to jump to any location in any paragraph. To see this, suppose that the base register has the value 00, and the programmer wants the Little Man to jump to location 575 for the next instruction. The following two instructions will accomplish this:

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JUMP *99 . . . 99 575 .

Register Indirect Addressing Register deferred or register indirect addressing is a very powerful addressing technique used by the Intel X86 series CPUs, HP VAX CPUs, Motorola 680X0 CPUs, and others. (Some vendors call this addressing mode “register deferred addressing.”) This addressing mode is similar to indirect addressing with one difference: instead of using a memory location as a pointer to the address of the data, that address pointer is stored in a general-purpose register. The instruction goes to the general-purpose register to find the address of the data. This is illustrated in Figure S2.12. Register indirect addressing is very efficient. Once the pointer address has been loaded into the register (which of course requires a separate instruction), data can be accessed in the same number of fetch-execute steps as direct addressing, since the register may be reached immediately from its field in the instruction register. Yet, the size of the address field required is small: usually only 3 or 4 bits to specify the particular register, and some method of indicating the addressing mode. Thus, this is an excellent method for addressing a large memory space with a small instruction word. A variation on this idea even increments or decrements the address pointer that is stored in the register. This method is known as autoincrementing or autodecrementing. If you are familiar with the “C” programming language, you might be interested to know that this addressing mode is a direct implementation of the “++” and “––” operations. This feature is provided because indexing through an array is such a common programming operation. FIGURE S2.12 Typically these instructions increment or Obtaining the Data with Register Indirect Addressing decrement the register each time the instruction is executed, in addition to the “Address” field 3 Instruction normal function of the instruction. The (indicates GP register #3) instruction itself might be a LOAD or a STORE Op code and mode or an ADD or some other similar operation. (indicate register Thus, each execution of the instruction will indirect addressing) access the subsequent memory location in GP register #3 2157 the array. This feature simplifies the writing of program loops by combining two operations into a single instruction, replacing, for 2156 2157 7654 example, instructions 7, 9, 10, and 11 in 2158 Figure S2.11. Some CPUs also provide an addressing Address Contents mode that treats the memory location Memory reached as another address pointer and thus The data to 7654 provide true indirection from that point. be used

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EXAMPLE

The Motorola 68000 CPU MOVE instruction demonstrates the efficiency possible using addressing based on registers. The 68000 CPU has 16 general-purpose registers, 8 intended for data and 8 for addresses. A single MOVE instruction fulfills both LOAD and STORE functions; it can move data from register to register, from register to memory, from memory to register, and even from memory to memory. The format for a move instruction is shown in Figure S2.13. There is a 4-bit op code for this instruction. Six bits are used for the source address, and 6 bits are used for the destination address. Thus, only 16 bits is required for the basic MOVE instruction. The two 6-bit addresses use 3 bits to specify a register; the other 3 bits are used to indicate an addressing mode. The addressing modes include register direct (i.e., the register itself), register indirect, register indirect with postincrement of the address, and register indirect with predecrement of the address. (There are also several other addressing modes that use the memory location following the instruction as an extension to the instruction to provide absolute addressing, immediate addressing, and memory indirect addressing.) Since the general-purpose registers hold 32 bits, a 16-bit move instruction is capable of reaching 4 billion different memory addresses.

Indexed Addressing The example in Figure S2.11 shows that we can address a table of data by modifying the address of the data and using that address indirectly to obtain the data. An alternative approach uses the address in the instruction, as in direct addressing, but modifies this address by adding in a value from another register. The register used for this purpose can be another general-purpose register, or it may be a special index register. This technique is known as indexing the address. The technique is shown diagrammatically in Figure S2.14. Indexing is similar conceptually to base offset addressing. Both offset the address by an amount stored in another register. The difference, philosophically, is that the base FIGURE S2.13

FIGURE S2.14

68000

Modifying an Address with an Index Register

MOVE

Instruction Format

op code register mode mode register Destination Source Op codes: 0001 move byte 0010 move longword 0011 move word

Instruction

Address field

258

Op code and mode (indicate indexed addressing)

10

Index register

+

267 268 5299 269

Address

Contents

Memory 5299

The data to be used

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address is intended primarily to locate a block of addressing as a way of expanding the addressing range for a given address field size, whereas the index register is used primarily as a table offset for handling subscripting. Thus, the value in a base address register is likely to be large, and rarely changed during execution of a program; the value in an index register is most likely small, and frequently changing. The flow diagram in Figure S2.15 illustrates an example that uses both base offset and indexed addressing. Some computers provide instructions that autoindex. Autoindexing is similar to autoincrementing, except that it is the index register that is incremented. If the value in the index register is 0, indexed addressing reduces to direct addressing. Figure S2.16 shows the totalizer loop program yet one final time, this time using indexed addressing. The “@” symbol is used to indicate that the instruction is indexed. The index register in this example is called the X FIGURE S2.15 register, and it is loaded in a manner similar to Indexing a Base Offset Address the A register, using a LOAD X (mnemonic LDX) instruction. LDA is used as the mnemonic for Address field 258 Instruction the LOAD A instruction to distinguish the two different instructions. It is also common to Op code and mode 10 Index register (indicate indexed provide a DECrement or INCrement instruction addressing) for the X register, since this is the most com3000 + mon use for the register, and also CONDITIONAL Base offset BRANCH instructions similar to those provided register for the A register. This particular program adds in reverse order. In this way, X can be used both 3267 3268 9874 as an offset for addressing the table and as a 3269 counter, resulting in more efficient code. Notice how much shorter the program is this time. Address Contents It should be noted that some systems allow Memory the index to be multiplied by a scaling factor of The data to 9874 2n (i.e., 2, 4, 8, …) before it is added to the be used

FIGURE S2.16 A Totalizer Loop with Indexed Addressing Mailbox 00 01 02 03 04 05 06 91 92

Instruction

Comments

LDA 91 LDX 92 ADD @60 DEC X BRPX 02 OUT COFFEE BREAK 0 19

/total is kept in A. This sets A to 0. (not indexed) /initialize the counter to 19 /ADD 79, ADD 78, etc. as X is decremented /Decrement the index—19, 18, etc. /text if done (when X decrements from 0 to –1) /done, ..output the result from A

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address. (The index register is simply shifted left, of course!) This allows the index to work easily on arrays regardless of the number of bytes required for elements of the particular data type, as long as each element occupies a 2n number of bytes.

Indirect Indexed and Indexed Indirect Addressing It is possible in some computers to have both indirect and indexed addressing in use at the same time, although this ability is of limited use. (It could be used to find a row of data in a two-dimensional table stored by columns, for example). The order in which the two address modes are applied is significant. The resulting address will not be the same in both cases. The following example shows the application of both modes of addressing. We suggest careful study of this example. Understanding this example will clarify and differentiate for you the concepts of both indirect and indexed addressing.

EXAMPLE

Assume the following values for X and various memory locations: Location 40 60 70 80 X

Contents 50 80 185 323 20

The instruction LDA @*40 (indexed, then indirect) will proceed as follows. Indexing 40 leaves an indexed address of 60. Since memory location 60 contains the final address (because indirection must still take place), the final address of the data is 80. Therefore, the value 323 is loaded into the accumulator. Now assume instead that the instruction is LDA *@40 (indirect, then indexed) Performing the indirect from address 40 yields the preindexed address 50. Indexing 50 by the value 20 in the index register results in the final address of 70. Therefore, the value 185 is loaded into the accumulator.

Obviously, there are many variations on addressing, and we can’t (or wouldn’t want to!) discuss them all. Hopefully, this brief introduction provided you with a flavor of the possibilities.

SUMMARY AND REVIEW In this supplementary chapter we have considered different techniques for addressing memory. The Little Man Computer is limited to direct, absolute addressing. Register addressing is a fast alternative when the number of registers is sufficient to reduce the number of memory accesses required. Immediate addressing can also reduce the number of memory accesses. Alternatives to absolute addressing include base offset addressing and

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relative addressing. Alternatives to direct addressing include indirect addressing, indexed addressing, and combinations of the two. Register deferred addressing is particularly effective at reducing instruction size.

KEY CONCEPTS AND TERMS absolute addressing addressing modes autodecrementing autoincrementing base register addressing direct addressing

immediate addressing impure coding indexed addressing indirect addressing real mode addressing register addressing

register deferred addressing register indirect addressing relative addressing relocatability

EXERCISES S2.1 S2.2

S2.3 S2.4 S2.5 S2.6

S2.7

Determine the fetch-execute cycle for a Little Man LOAD instruction in a machine that uses relative addressing. It is common in programming to write a single instruction infinite loop into the program, which simply sits and waits for some interruption to come into the computer from outside. An example of this is the “>” prompt in MS-DOS. After the prompt is printed, the program waits for the user to type something from the keyboard. Such a loop can be created by using the jump instruction, and jumping to the current location, that is the instruction being executed. This will cause the JUMP instruction to be executed over and over again. Assume that the JUMP instruction will be located at memory location 34. a. What instruction will be found in that location if the machine uses absolute addressing? b. What instruction will be found if the machine uses relative addressing? c. Suppose the JUMP instruction is to be located at memory location 77. How will your answer in (b) change? Immediate addressing cannot be applied to the store instruction. Why not? Show the fetch-execute cycle for a STORE instruction with indirect absolute addressing. Show the fetch-execute cycle for an ADD instruction with both indirect and indexed addressing modes in use. Assume that the indexed mode is applied first. To create a larger data space for an immediate instruction, some vendors use a variant known as extended immediate addressing. In this mode, the data to be used is stored at the memory location following the instruction. Thus, the immediate data can be the size of a full memory word. Show the fetch-execute cycle for a LOAD EXTENDED IMMEDIATE instruction. Assume a modified LMC that supports indexed addressing. Rewrite the program loader (see Exercise 6.14) with indexed addressing, and no impure code.

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S2.8

The Little Man Computer Corporation has recently announced the new improved Little Woman Computer (LWC), which features a new, increased mailbox address space, plus indexed addressing for convenient table handling capability. The new machine has an additional three-digit calculator, called the indexer. The machine also has a new instruction 0XX, to support the new index register. The 0XX instruction works as follows: 000 The Little Woman sets the indexer to 0. 00X The Little Woman adds, using immediate mode, the value X to whatever is already in the indexer. 0XX (where XX is in the range 10–99) The Little Woman adds the contents of mailbox XX, using direct addressing to whatever is already in the indexer. The following instructions are modified to use indexed addressing. The address contents of the indexer are always added to XX to determine the final address: LOAD (5XX) STORE (3XX) ADD (1XX) SUBTRACT (2XX)

The HALT instruction is reassigned code 900. There is an additional BRANCH ON instruction, 9xx (excluding 900, 901, and 902) which causes a branch to location xx if the value in the index register matches that in the A register. a. Describe the steps the Little Woman goes through to perform an ADD instruction. b. Write an LWC program that accepts a series of input numbers and stores them, one to a mailbox. The number of values to be accepted is provided as the first input entry. Then, the program adds the stored numbers and prints out the total. c. What is the total possible address space for the LWC? What are the means used to expand the space? (worded differently, how does one get data from outside the usual 0–99 range?) d. Suppose we don’t want to use indexed addressing. What can we do to make the four indexed instructions look just like they did in the original machine? The Little Prince Computer (introduced in Chapter 7, Exercise 7.12) MOVE instruction can be extended as follows. The MOVE instruction is a two-word instruction

MATCH

S2.9

0XX NYY

stored in consecutive mailboxes. N will represent the addressing mode. If N is 0, addressing is direct, as before. If N is 1, both XX and YY are indexed, based on the value in the calculator (A). a. Show the modified fetch-execute cycle for this instruction with indexing. b. Use this instruction to write an LPC program that moves a group of data stored at 20–30 to location 60. S2.10 The Obliter-8 Computer uses relative addressing. The machine has two registers, A, the accumulator, and X, the index register. The machine supports direct, indirect,

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and indexed relative addressing. Each instruction uses two consecutive memory locations, call them PC and PC+1. The first is the op code; the second contains an address relative to its location (i.e., relative to PC+1). Given the data that follows, what will be the result of a. an ADD indirect at location 1278? (Note: The indirect address is absolute, not relative.) b. an ADD indexed at location 1278? 1278 1279 . . 1288 1289 1290 1291 1292 . 1298 1299 1300 1301 1302 1303

ADD 10

1323 1299 1322 1300 10 1300 1320 1323 1322 1291 25

1320 1321 1322 1323 1324

510 1322 16 8 124

7 8 9 10 11 12

4 1289 116 1298 1321 1324

A X

2111 12

S2.11 Yet another modified LMC has come forth. This one extends the memory space of the machine by adding base register addressing. The LMC III has a three-digit base register. The value stored in this register is added to all addresses when addressing memory. The base register value is added to the final value of all addresses; that is, it is added last if multiple addressing modes are used. Note, too, that the value in the base register is added to everything, including the PC. Thus, if the PC says 55, and the BR contains 400, the next instruction is fetched from location 455. If that instruction is LOAD 99, the data is found in location 499. a. For a fixed value in the base register, how much memory can a programmer access? b. What is the total range of memory? c. Show the fetch-execute cycle for an add instruction with indirect addressing in this machine. d. Consider the following set of values for various registers and memory locations. What value ultimately ends up in A? A ➝ 60 BR ➝ 220 PC ➝ 40 40 ➝ ADD (indirect) 85 260 ➝ ADD (indirect) 85

85 ➝ 92 92 ➝ 333 166 ➝ 77 305 ➝ 166 386 ➝ 4 390 ➝ 211

S2.12 As do other computer companies, the LMC Corporation has discovered it can be profitable to introduce a new machine every few months. This is known in the

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industry as “progress” or, sometimes, as “planned obsolescence.” The latest product from the LMC Corporation, the LLC (Little Lulu Computer), uses direct relative addressing for the LOAD, STORE, ADD, SUBTRACT, and all BRANCH instructions. All other instructions are unchanged. The XX field in the relative instructions represents a 10’s complement relative address (-50 to +49). a. Write a program in LLC code that inputs three numbers and outputs them, largest number first. b. Show the fetch-execute cycle for a STORE instruction in the LLC. You may assume that the sign handling for the relative address is handled automatically. c. Suppose the location counter reset button jammed, so that instead of resetting to 0 when pushed, it resets to 35. Rather than fix the button, we’ll load the program starting at location 35 instead of at mailbox 0. (This technique, known as relocation, is required for systems where multiple programs must reside in memory simultaneously.) What changes must be made to your program to make it work in this case? S2.13 The Pomegranate Seedless instruction set supports several different addressing modes, including both indexed and indirect, either individually or together in either order. The format for a store-in-memory instruction looks like this 5 bits

1

1

1

Op code

8 bits

16 bits

Index value

Address

0 no indirect 0 no index 0 for indirect first 1 indirect 1 index 1 for indexed first (ignored unless both previous bits are 1)

The following mnemonic example gives the idea: SIM 1, 1, 0, 220, 1696

and says to store the accumulator at a location indirect from 1696 (decimal), then indexed by 220 (decimal). For the following three cases, and the given data, show the sequence of values to be found in the memory address register. Your last value will obviously be the location where the data will be stored. a. SIM 1, 0, 0, 125, 1623 b. SIM 1, 1, 0, 125, 1623 c. SIM 1, 1, 1, 125, 1623

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Memory data (values in decimal) is 1621 1622 1623 1624 1625 1626

1628 1745 1749 1748 1621 1722

1745 1746 1747 1748 1749

1539 1628 1849 1776 (a good year!) 1902 (not bad either!)

S2.14 The text discusses one method of branching to subroutines, using stacks. An alternative method for a CALL instruction is to store the return address in the first location of the subroutine and then JUMP to the next location of the subroutine. To return, the program simply does an indirect jump through the first location of the subroutine. a. Can you see any disadvantage to this method as opposed to the stack method? (Hint: Consider the traditional recursive program that performs factorials or any other recursive program with which you are familiar.) b. Here is the fetch-execute cycle for a CALL instruction. Study it carefully. PC ➝ MAR MDR ➝ IR IR[ADD] ➝ MAR PC +1 ➝ MDR (write) IR[ADD] + 1 ➝ PC

Write the equivalent fetch-execute cycle for the RETURN instruction. Location 20 has a CALL 40 instruction in it. What is stored in location 40? Where does the subroutine actually begin? Describe exactly the steps that take place when this instruction is executed, and when the subroutine RETURN is executed. S2.15 Assume that you wish to build a stack on a Little Man Computer that is standard except for the addition of indirect addressing capability. The stack will be located starting at mailbox 70. A current stack pointer is stored in location 90. a. Write a Little Man code segment that will add a value to the stack. The value will come from the calculator. Make sure that your code leaves everything ready for the next push or pop action. b. Write a code segment that will pop a value from the stack to the calculator. c. Even without indirect addressing, it is possible to implement push and pop instructions using Little Man code, but the task is more difficult. Describe carefully the steps that you must take to simulate a PUSH instruction in this case. c.

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