I nternational Journal Of Computational Engineering Research (ijceronline.com) Vol. 3 Issue. 1

Implementation of SP I Protocol in FPGA Veda Patil1, Vijay Dahake 2, Dharmesh Verma 3 , Elton Pinto 4 1,2

3,4

(Electronics & Teleco mmunicat ion, Rama rao Adik Institute of technology/ Mumbai, India) (Electronics & Teleco mmunication, Society of Applied Micro wave Electronics Engineering & Research/Mumbai, India)

Abstract: In this paper, Serial Peripheral Interface (SPI) protocol is implemented in Field Programmab le Gate Array (FPGA). Both the components SPI Master and SPI Slave are imp lemented using state machine diagram. The coding is done in Very hig h speed integrated circuits Hardware Descriptive Language (VHDL). The simulated data is shown and Received data is analyzed by receiving an acknowledgment. Keywords: Clock Phase, Clock Polarity, FPGA, M ISO, M OSI, SPI master, SPI Slave, VHDL.

1. Introduction Serial co mmunication is the process of sending data one bit at a time, sequentially, over a communicat ion channel. Serial co mmunicat ion is used for all long-haul co mmunicat ion and most computer networks, where the cost of cabling and synchronization difficult ies makes parallel co mmunication impract ical. A serial connection requires fewer interconnecting cables (e.g., wires/fibers) and hence occupies less space. The ext ra space allo ws for better isolation of the channel from its surroundings. Serial buses are becoming more co mmon even at shorter distances, as improved signal integrity and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simp licit y and to outstrip its disadvantages. Serial links can be clocked considerably faster than parallel links in order to achie ve a higher data rate. Crosstalk is less of an issue, because there are fewer conductors in proximity. In many cases, serial is a better option because it is cheaper to imp lement. Many Integrated Circuits have serial interfaces, as opposed to parallel ones , so that they have fewer p ins and are therefore less expensive. 2. Serial Peripheral Interface (SPI) Protocol The SPI bus is a synchronous serial data link standard, named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device init iates the clock and data frame. Multip le slave devices are allo wed with individual slave select (chip select) lines. SPI is often referred to as SSI (Synchronous Serial Interface). The SPI bus interface consists four logic signals namely Serial Clock (SCLK), Master Output Slave In (MOSI), Master In Slave out (MISO) and Slave Select (SS).

Figure1. SPI Protocol Interface To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximu m frequency the slave device supports. Such frequencies are commonly in the range of 1–100 M Hz the master then transmits the appropriate chip select bit for the desired chip to logic 0. Logic 0 is transmitted because the chip s elect line is active low, mean ing its off state is logic 1; on is asserted with logic 0. If a wait ing period is required then the master must wait for at least that period of time before starting to issue clock cycles. Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out w ith the most significant bit first, while shifting a new least significant bit into the same reg ister. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and is written to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave.

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I nternational Journal Of Computational Engineering Research (ijceronline.com) Vol. 3 Issue. 1

Figure 2. SPI Timing diagram

3. Clock Polarity and Phase In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. The timing applies to both the master and the slave to communicate articu lately. The co mbinations of Clock polarit y (CPOL) and Clock Phase (CPHA) g ive rise to different modes. Table 1.Different modes of clock Mode

CPOL

CPHA

0

0

0

1

0

1

2

1

0

3

1

1

Mode 0: CPOL=0 i.e. SCLK is normally lo w and the first clock edge is a rising edge & CPHA=0, the data is captured on the clock's rising edge (low to high transition) and data is received on the clock‟s falling edge (high to low clock transition) Mode 1: CPOL=0 i.e. SCLK is normally low and the first clock edge is a rising edge & CPHA=1, data is captured on the clock's falling edge and data is propagated on a rising edge. Mode 2: CPOL=1 i.e. SCLK is normally high and the first clock edge is a falling edge & CPHA=0, data is captured on clock's falling edge and data is received on a rising edge. Mode 3: CPOL=1 i.e. SCLK is normally h igh and the first clock edge is a falling edge & CPHA=1, data is captured on clock's risin g edge and data is received on a falling edge. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active. The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. This adds mo re flexib ility to the commun ication channel between the master and slave.

Figure 3. Timing diagram showing clock polarity and clock phase. ||Issn 2250-3005(online)||

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4. VHDL Coding And Result 4.1. SPI Master The number of slaves is declared in the ENTITY by the GENERIC parameter as slaves and the transmit and receive data bus widths are declared by GENERIC parameter d_width. Table below shows different input - output ports which are defined in the code. In the table M specifies the data width and N specifics the number of slaves. The clock and clk_div inputs define the frequency of SCLK (i.e. the SPI data rate). Clock is the system clock used to operate the synchronous logic inside the component. The clk_div integer input allows the user to set the relative speed at which the current transaction occurs. Clk_div is the number of clock periods between SCLK transitions. The enable pin latches in the standard logic values of clk_div, cpol and cpha at the start of each transaction. This allows communication with individual slaves using independent SPI speeds & modes. A low logic level on the busy output port indicates that the component is ready to accept a command. The component latches the settings, address, and data for a transaction on the first rising edge of clock where the enable input is asserted. On the following clock, the co mponent asserts the busy signal and begins performing the transaction. Once co mplete, the component outputs the received data on the rx_data port. This data remains on the port until the component receives new data from a subsequent transaction. The component sets busy low to notify the user when the data is available, and the component is immed iately ready for another instruction .The transition timing diagram is obtained by the simu lator is given in the table 2. This SPI master is instantiated with one slaves and eight bit data width. It transmits the data”10110010” to slave 2, which operates in mode 3 (CPOL=‟1‟and CPHA=‟1‟).The master receives the”00000000” data. Table 2. Po rt descriptions of SPI Master entity Port

Width

Mode

Data Type

Interface

Descripti on

clock

1

in

standard logic

user logic

System clock.

reset_n

1

in

standard logic

user logic

Asynchronous active low reset.

enable

1

in

standard logic

user logic

H: latches in settings, address, and data to initiate a transaction, L: no transaction is initiated.

cpol

1

in

standard logic

user logic

SPI clock polarity setting.

cpha

1

in

standard logic

user logic

SPI clock phase setting.

cont

1

in

standard logic

user logic

Continuous mode flag.

clk_div

32

in

integer

user logic

Speed setting. The integer input is the number of system clocks per 1/2 period of sclk.

addr

32

in

integer

user logic

Address of target slave. The slaves are assigned addresses starting with 0.

tx_data

M*

in

standard logic vector

user logic

Data to transmit.

miso

1

in

standard logic

slave devices

Master in, slave out data line.

sclk

1

buffer

standard logic

slave devices

SPI clock.

ss_n

N^

buffer

standard logic vector

slave devices

Slave select signals.

mosi

1

out

standard logic

slave devices

Master out, slave in data line.

busy

1

out

standard logic

user logic

Busy / data ready signal.

rx_data

M*

out

standard logic vector

user logic

Data received fro m target slave.

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Figure 4. Simulated results of SPI Master 4.2. SPI Slave The mode that the slave operates in is defined by the GENERIC parameters cpol and cpha. The transmit and receive data bus width are declared by the GENERIC parameter d_width. Each transaction between the SPI slave component and the SPI master must consist of an 8-bit command, followed by a N-bit data transfer. The size N of the data transfer is determined by the GENERIC d_width parameter in the VHDL entity and is set by the user. The receive register is a buffer that holds data received fro m the master over the MOSI line. For the user logic to access the resulting data, the user must pulse the rx_req input when the component is not performing a transaction. The slave then outputs the receive register contents on the rx_data port. The transmit reg ister is a buffer that holds the data intended to be transmitted by the slave to the master over the MISO lin e. The user logic fills this register by presenting the data on the tx_load_data port and pulsing the tx_load_en input when the component is not performing a t ransaction. The status register contains three status bits. The master can read, set, or clear these bits with transactions addressed to this register. During a transaction that reads or writes the status register, the first three data bits sent correspond to trdy, rrdy, and roe, respectively. The slave co mponent ignores the remaining bits sent or received d urin g the transaction. The user logic has access to these bits via the ports bearing their names. The user logic can also set or clear these bits by presenting the desired values on the st_load_trdy, st_load_rrdy, and st_load_roe inputs and pulsing the st_load_en input when the component is not performing a transaction (i.e. the busy output is low). The reset_n input port must have logic high for the SPI slave component to operate. A low signal on this port asynchronously resets the component. During reset, the miso output assumes a high impedance state, and the rx_data output port clears. The transmit, receive, transmit ready, receive ready, and receive overrun error reg isters all clear. Figure 5 illustrates a transaction with cpol = 0, cpha = 0, and d_width = 8. The slave is configured to operate in mode 0. While the slave is not busy, the user logic pulses the tx_load_en input while presenting the data “10101010” on the tx_load_data bus. The trdy signal immediately goes high to indicate that new data exists to transmit. The master then initiates the transaction wit h the command “00000000”, instructing the slave to load the subsequent MOSI data into the receive register and output the transmit register‟s contents to MISO. Once the last data bit is sent, the trdy signal goes low to indicate that the transmit register‟s current value has been sent to the master. Likewise, when the slave reads the last data bit into the receive register, the rrdy signal asserts to indicate that new data has been received. The user logic then pulses the rx_req input, and the slave responds by outputting the received data “10110001” on the rx_data bus. The rrdy output then deasserts to indicate that the data contained in the receive reg ister has already been read by th e user logic.

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Table 3. Po rt descriptions of SPI Slave entity Port

Width

Mode

Data Type

Interface

Description

sclk

1

in

standard logic

master device

SPI clock.

mosi

1

in

standard logic

master device

Master out, slave in data line.

miso

1

out

standard logic

master device

Master in, slave out data line.

ss_n

1

in

standard logic

master device

Active low slave select signal.

busy

1

out

standard logic

user logic

„1‟ during transactions with the master device, „0‟ when available to user logic

reset_n

1

in

standard logic

user logic

Active low asynchronous reset.

tx_load_en

1

in

standard logic

user logic

Latches tx_load_data into the transmit register (the slave must not be busy).

tx_load_data M*

in

standard logic vector

user logic

Data to be latched into the transmit register.

rx_req

1

in

standard logic

user logic

Requests the last received data from the master (the slave must not be busy).

rx_data

M*

out

standard logic vector

user logic

Presents the last received data from the master when requested.

trdy

1

buffer

standard logic

user logic, master device

Transmit Ready. „1‟ when the slave has loaded data into the transmit register, but it has not yet been sent.

rrdy

1

buffer

standard logic

user logic, master device

Receive Ready. „1‟ when the slave has received data from the master, but it has not yet been requested.

roe

1

buffer

standard logic

user logic, master device

Receive Overrun Error. „1‟ when data received from the master is overwritten by new data from the master before it has been accessed by the user logic.

st_load_en

1

in

standard logic

user logic

Status Load Enable. Latches data into the trdy, rrdy, and roe registers from the user logic (the slave must not be busy).

st_load_trdy

1

in

standard logic

user logic

The trdy value that is latched in by st_load_en.

st_load_rrdy 1

in

standard logic

user logic

The rrdy value that is latched in by st_load_en.

st_load_roe

in

standard logic

user logic

The roe value that is latched in by st_load_en.

1

Figure 4. Simulated results of SPI Slave ||Issn 2250-3005(online)||

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5. Conclusion In this paper SPI Master and SPI Slave protocol has been implemented in VHDL. Th is SPI Master is a flexible programmab le logic co mponent that accommodates communication with a variety of slaves via single parallel interface. It allo ws commun ication with user specified nu mber of slaves, wh ich may require independent SPI modes, data widths, and serial clock speeds. The VHDL SPI slave offers a user definable mode and data width. It includes status signals for transmit ready, receive ready, and receive overrun error. References [1] Motorola MMC 2001 Reference Manual. [2] Motorola SPI Block Gu ide V03.06, 2003. [3] Microchip M CP2510 Applicat ion Note AN215.

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