Migration from AT89C51RD2/ED2/ID2 to AT89C51RE2 This application note is a guide to assist current AT89C51RD2/ED2/ID2 users in converting existing designs to the AT89C51RE2 device. Check the product datasheet for detailed information. To permit an easy migration, this applic ation note compares the features , memory organization/accesses, SFRs and bootloader functionality.
8051 Microcontrollers Application Note
Feature Comparison Description Program Memory
In-System Programming (ISP)
XRAM Stack depth On-Chip EEPROM data UART Internal Interrupt sources
Packages
Pinout
AT89C51xD2
AT89C51RE2
Full 64K bytes program/code memory
Full 128K bytes program/code memory
UART bootloader
UART bootloader based on a new protocol to speed up the download time
1792 bytes
8192 bytes
256 bytes
512 bytes
2048 bytes byte write (ED2 only) 1
No 2
9/10(1)
10
PLCC44 VQFP44 PLCC68 VQFP64 PDIL40
PLCC44 VQFP44 VQFP64
AT89C51RD2/ED2 and AT89C51RE2 are pinout compatible.
Rev. 7667B–8051–03/07
1
Memory Organization Code Memory Organization
While the AT89C51xD2 implements 64K bytes of on-c hip program/c ode memory , the AT89C51RE2 implements 128K bytes on-chip program/code memory.
Figure 1. AT89C51xD2 Code Memory Organization FFFFh 2K bytes ROM Bootloader
F800h
64K Bytes Flash Memory User Space
0000h
Figure 2. AT89C51RE2 Code Memory Organization Logical MCU Address
Physical Flash Address
Logical MCU Address
Physical Flash Address
Logical MCU Address
Physical Flash Address
Logical MCU Address
0FFFFh
FFFFh
17FFFh
FFFFh
1FFFFh
FFFFh
8000h
08000h
8000h
10000h
8000h
18000h
8000h
7FFFh
07FFFh
FFFFh
upper 32K Bank 0
upper 32K Bank 1
upper 32K Bank 3 Optionnal External Memory
upper 32K Bank 2
32K Common
0000h
00000h
On-Chip flash code memory External code memory
The way to make a project using the banking methode is describe in the application note: • “AT89C51RE2 Code Banking and Bank Switching with Keil µVision ® ”
2
Migration from AT89C51xD2 to AT89C51RE2 7667B–8051–03/07
Migration from AT89C51xD2 to AT89C51RE2 On-chip RAM/XRAM Memory
Both AT89C51 x D2 and AT89C51RE2 have 256 bytes o f s cratc h pa d RAM. The AT89C51RE2 has 8192 bytes of internal XRAM, whereas the AT89C51xD2 has only 1792 bytes. By default AT89C51RE2 has the maximum of on-chip XRAM size (8192) s elected after reset contrarily to AT89C51xD2 which has 768 bytes selected.
Stack Pointer
On the AT89C51xD2 product, the Stack area is loc ated only in the RAM as most C51 controllers. Due to the XRAM size and the code size, the AT89C51RE2 has the posibity to extend the Stack area to the 256 first bytes of the XRAM. By default AT89C51RE2 has the extended mode disable to ens ure compatibility with AT89C51xD2. The AT89C51RE2 has an Extended stack mode. In this mode the stack is located in the lower 512 bytes part of the XRAM. By default the extended stack mode is disabled for AT89C51xD2.
3 7667B–8051–03/07
SFR Mapping
Table 2 contains an SFR comparison between AT89C51xD2 and AT89C51RE2.
Table 1. SFR Mapping Bit addressable
Non Bit addressable
0/8
1/9
4/C
5/D
6/E
F8h
P6 XXXX XX11
CH 0000 0000
CCAP0H CCAP1H XXXX XXXX XXXX XXXX
CCAP2H XXXX XXXX
CCAP3H XXXX XXXX
CCAP4H XXXX XXXX
FFh
F0h
B 0000 0000 CL 0000 0000
CCAP0L CCAP1L XXXX XXXX XXXX XXXX
CCAP2L XXXX XXXX
CCAP3L XXXX XXXX
CCAP4L XXXX XXXX
EFh
CCAPM3 X000 0000
CCAPM4 X000 0000
E8h
P5 1111 1111
2/A
3/B
D8h
CCON 00X0 0000
CMOD 00XX X000
CCAPM0 X000 0000
CCAPM1 X000 0000
CCAPM2 X000 0000
D0h
PSW 0000 0000
FCON 0000 0000
EECON 0000 0000
FSTA xxxx x000
EESTA xxxx x000
C8h
T2CON 0000 0000
T2MOD XXXX XX00
E7h
RCAP2L 0000 0000
RCAP2H 0000 0000
TL2 0000 0000
TH2 0000 0000
SPCON 0001 0100
SPSCR 0000 0000 (SPSTA on xD2)
SPDAT XXXX XXXX
SADEN_0 0000 0000
SADEN_1 0000 0000
BRL_1 0000 0000
BDRCON_1 XXX0 0000
B0h
P3 1111 1111
IEN1 XXXX 0000
IPL1 XXXX 0000
IPH1 XXXX 0000
A8h
IEN0 0000 0000
SADDR_0 0000 0000
SADDR_1 0000 0000
A0h
P2 1111 1111
SCON_1 0000 0000
U2(AUXR1.5) =1
P4 1111 1111
B8h
SBUF_1 0000 0000
SBUF_0 XXXX XXXX
CFh
C7h
BFh
AUXR1 000x 11x0
WDTRST XXXX XXXX
98h
SCON_0 0000 0000
90h
P1 1111 1111
88h
TCON 0000 0000
TMOD 0000 0000
TL0 0000 0000
TL1 0000 0000
80h
P0 1111 1111
SP 0000 0111
DPL 0000 0000
DPH 0000 0000
0/8
1/9
2/A
3/B
DFh
D7h
IPL0 X000 000
U2(AUXR1.5) =0 C0h
7/F
F7h
E0h
ACC 0000 0000
IPH0 X000 0000
B7h
CKCON1 XXXX XXX0
AFh
WDTPRG XXXX X000
A7h
BRL_0 0000 0000
BDRCON_0 XXX0 0000
KBLS 0000 0000
KBE 0000 0000
KBF 0000 0000
BMSEL 0000 0YYY
SSCON 0000 0000
SSCS 1111 1000
SSDAT 1111 1111
SSADR 1111 1110
CKRL 1111 1111
97h
TH0 0000 0000
TH1 0000 0000
AUXR XX00 1000
CKCON0 0000 0000
8Fh
PCON 00X1 0000
87h
4/C
5/D
6/E
9Fh
7/F
Modified Registers New Registers 4
Migration from AT89C51xD2 to AT89C51RE2 7667B–8051–03/07
Migration from AT89C51xD2 to AT89C51RE2 Modified Registers Table 2. AUXR1 Register AUXR1 Register (SFR:A2h) AUXR1 AT89C51xD2 Reset value: xxxx x0x0b AT89C51RE2 Reset value: xxxx x0x0b
7
6
5
-
-
ENBOOT
-
GF3
0
-
DPS
ESS
SP9
U2
4
-
GF3
3
2
0
1
-
DPS
0
The bits to manage the extended stack ESS and SP9 are located in this regis ter. the ENBOOT has been removed, because it is no longer possible to jump in the bootloader. The ENBOOT is replaced by the bit U2 which allows to map P4 or SCON_1 in the bit addressable C0h. Table 3. IEN1 Register IEN1 Register (SFR:B1h) IEN0 AT89C51xD2 Reset value: 0000 0000b AT89C51RE2 Reset value: 0000 0000b
7
2
1
-
-
-
-
-
ESPI
ETWI
EKBD
-
6
-
5
-
4
-
ES_1
3
ESPI
-
EKBD
0
AT89C51RE2 introduces new bits, that enable the second UART interrupt. Table 4. IPH1 Register IPH1 Register (SFR:B3h) IPH1 AT89C51xD2 Reset value: 0000 0000b AT89C51RE2 Reset value: 0000 0000b
7
2
1
-
-
-
-
-
SPIH
TWIH
KBDH
-
6
-
5
-
4
-
PSH_1
3
SPIH
-
KBDH
0
AT89C51RE2 introduces new bits, PSH_1 to select High bit of interrupt priority for the second UART. Table 5. IPL1 Register IPL1 Register (SFR:B2h) IPL1 AT89C51xD2 Reset value: 0000 0000b AT89C51RE2 Reset value: 0000 0000b
7
2
1
-
-
-
-
-
SPIL
TWIL
KBDL
-
6
-
5
-
4
-
PSL_1
3
SPIL
-
KBDL
0
AT89C51RE2 introduces new bit, PSL_1 to select Low bit of interrupt priority for the second UART.
5 7667B–8051–03/07
Table 6. SPSCR Register SPSCR Register (SFR:C4h) SPSCR AT89C51xD2 Reset value: 0000 0000b SPSTA AT89C51RE2 Reset value: 00x0 xxxxb
7
6
5
4
SPIF
WCOL
SSER
MODF
-
SPIF
-
OVR
MODF
SPTE
3
2
1
0
UARTM
SPTEIE
MODFIE
The SPCON register in the AT89C51xD2 is renamed to SPSCR in the AT89C51RE2. For more details, see datasheet. Table 7. FCON Register FCON Register (SFR:D1h) FCON
7
3
2
1
AT89C51xD2
FPL3
FPL1
FPL1
FPL0
FPS
FMOD1
FMOD0
FBUSY
SPSTA AT89C51RE2 Reset value: 00x0 xxxxb
FPL3
FPL1
6
FPL1
5
FPL0
4
FPS
FMOD2
FMOD1
FMOD0
0
New Registers
The AT89C51RE2,includes new registers. they are all loc ated in SFR addresses not used in AT89C51xD2. Thus migrating from AT89C51xD2 to the new AT89C51RE2 does not require code modification for these SFR addresses.
UART1 Interface
The second UART uses registers: SCON_1 (SFR:C0h), SBUF_1 (SFR:C1h), SADEN_1 (SFR:BAh), SADDR_1 (SFR:AAh), BDRCON_1 (SFR: BCh), BRL_1 (SFR: BBh). This UART1 hav e exactly the same behavior than the UART0. The only differenc e is that the SMOD bits are located in register BDRCON_1 whereas they are located in PCON register for the UART0.
Flash Interface
The Flash interface uses the registers: FCON (SFR:D1h), FSTA (SFR:D3h). On the AT89C51xD2, the Flash access were made only us ing the bootloader. On the AT89C51RE2, the application can read and write on the flash memory.
P6 Register
6
The P6 register is available at address F8h.
Migration from AT89C51xD2 to AT89C51RE2 7667B–8051–03/07
Bootloader Behavior Bootloader strategy is different between the two produc ts, due to flash technology and the code banking capability. • the BLJB (1 fuse bit) is replace by BRV (3 fuses bits) that allows to start on any bank selected by BRV after a reset. No more BSB and SBV byte on AT89C51RE2 New UART protocol to handle the 128Kbyte Flash capability As the application can perform flash operation, there is no more bootloader access from the application.
• • •
Note:
7
See datasheet for more detail
Migration from AT89C51xD2 to AT89C51RE2 7667B–8051–03/07
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