ICE Emulator for Z80 and Z180 TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ......................................................................................................................
ICE In-Circuit Emulator .................................................................................................................
ICE Target Guides ......................................................................................................................
ICE Emulator for Z80 and Z180 ..............................................................................................
1
WARNING ..............................................................................................................................
4
Quick Start ............................................................................................................................
5
Troubleshooting ...................................................................................................................
8
Hang-Up
8
Dual-Port Errors
8
FAQ ........................................................................................................................................
9
Basics ....................................................................................................................................
11
Peripherals Window
11
Z80182 Emulation hints
11
Probe Configuration
12
Emulation Modes
17
SYStem.Clock
Clock generation
18
MCU operation modes
18
Dual-port access
19
General Settings and Restrictions ......................................................................................
20
SYStem.CPU SYStem.Access
Restrictions
20
SYStem.Line BusReq
Bus access control
20
SYStem.Option REFresh
Trace option
21
SYStem.Option
Wait options
21
SYStem.Option OMCR
OMCR register
21
Bus control for daisy chain
22
SYStem.Option IO8
Size of I/O space
22
SYStem.Option V33
Voltage sense
22
Exception Control ................................................................................................................
23
SYStem.Option DOut
Schematics
24
RESET
24
BUSREQ Line
25
Interrupt Control
26 ©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
1
eXception.Activate
Force exception
26
eXception.Enable
Enable exception
27
eXception.Trigger
Trigger on exception
28
Stimulate exception
29
Define vector
29
DMA area
30
EEPROM Management .........................................................................................................
31
Using the MMU for Banked Target Systems ......................................................................
32
eXception.Pulse eXception.Vector MAP.DMA
SYStem.BankFile
Select banking file
32
SYStem.Bank
Select bank mode
33
Internal Bank
33
External Bank
34
Extended
35
Parameters for Banking Program
36
Memory and IO Access Routines
37
Using the MMU for Z180
37
Memory Classes ................................................................................................................... State Analyzer ....................................................................................................................... Keywords for the Trigger Unit
40 42 42
General Keywords for the Trigger Unit
42
Z80/ED/FD/CB Keywords for the Trigger Unit
44
Z180 Keywords for the Trigger Unit
44
8085 Keywords for the Trigger Unit
44
Keywords for the Display
45
Port Analyzer ........................................................................................................................
46
Keywords for the Port Analyzer (Z180,84C15)
46
Keywords for the Port Analyzer (Z181)
47
Additional Trace Channels ..................................................................................................
49
Compilers ..............................................................................................................................
53
3rd Party Tool Integration ....................................................................................................
54
Realtime Operation Systems ...............................................................................................
55
Emulation Frequency ...........................................................................................................
56
Emulation Modules ..............................................................................................................
57
Module Overview
57
Order Information
57
Physical Dimensions ...........................................................................................................
59
Adapter ..................................................................................................................................
68
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
2
ICE Emulator for Z80 and Z180 Version 26-Oct-2016
P:000D75 E::w.d.l addr/line P:000D70 P:000D71 P:000D73
\\IARZ80\iarz80\sieve+97
code AF ED42 381E
........... MIX
label
mnemonic xor a sbc hl,bc jr c,0D93
A
comment
; c,?0176
{ 491 P:000D75 0E00 P:000D77 2111C2 P:000D7A DD5EFC
?0178:
ld ld ld
E::w.v.f /l /c j = 15 {
flags[ k ] = FALSE; c,0 ; c,0 hl,0C211 ; hl,flags e,(ix-4) ; e,(ix-4) E::w.r CY _ N N P/V _ Hc _ Zr _ Sig _ IFF _ Tsk
sieve(); -000 sieve() i = 0 primz = 3 k = 15 anzahl = 0
A F B C D E I
0 2 80 0F 0C4 0C 0
BC 800F DE 0C40C HL 3 IX 0C40F IY 2D8 SP 0C407 PC 0D75 AF' 0
SP >0000 -06 0003 -04 000F -02 0000 FP >C41F +02 0CDC +04 000F +06 0000
For general informations about the In-Circuit Debugger refer to the “ICE User’s Guide” (ice_user.pdf). All general commands are described in “IDE Reference Guide” (ide_ref.pdf) and “General Commands and Functions”.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
3
WARNING
NOTE:
Do not connect or remove probe from target while target power is ON. Power up: Switch on emulator first, then target Power down: Switch off target first, then emulator
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
4
WARNING
Quick Start Before debugging can be started, the emulator must be configured by software: Ready to run setup files for most standard compilers can be found on the software CD in the directory ../ Demo/Z80/Compiler. All setup files are designed to run the emulator stand alone without target hardware. The following description should make the initial setup (to run the emulator together with the target hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the programming language PRACTICE to create a batch file, which includes all necessary setup commands. PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT ) or with any other text editor. A basic setup file includes the following parts: 1.
Set cpu-type and -mode
2.
Set system options
3.
Select dualport mode (optional)
4.
Set mapper (optional)
5.
Select frequency (optional)
6.
Activate the emulator
7.
Load application file (optional)
8.
Set breakpoints (optional)
9.
Start application
10.
Stop application (optional)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
5
Quick Start
Here a typical example, how to setup the system: 1.
Set cpu-type The command sys.cpu is used to select one derivative within a cpu-family and to set its operation mode. system.down system.cpu Z182
2.
; switch the system down ; select derivative Zilog Z182
Set system options The system window controls the CPU specific setup. Please check this window very carefully and set the appropriate options. Use the ? button in the main tool bar and click to the option check box (Command: HELP.PICK) to get online help in a pop up window. system.option IO8 on
3.
; inform the ICE that you are using only ; 8 bit addresses
Select dualport mode (optional) Dualport allows access to emulation RAM, while emulation is running. This is necessary to display variables, set breakpoints or display the flag listings while the emulation is running. System.Access selects how dualport access is done. system.access denied
4.
; dualport is disabled
Set mapper (optional) The mapper controls the memory access of the CPU. This means the use of internal or external memory, the protection of a memory bank etc. Address ranges must be defined by using memory classes. map.reset map.ram P:0x0--0x0ffff map.ram D:0--0x0FFFF
; ; ; ; ; ;
map.intern P:0x0--0x0ffff map.extern D:
reset mapper (all external) emulation RAM: 64KB (e.g. for program) emulation RAM: 64KB (e.g. for data) map program memory internal map data memory external
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
6
Quick Start
5.
Select frequency (optional) The CPU can be clocked by an internal (emulator) or external (target) clock source. If the internal clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is done by the “vco” command. The current CPU frequency can be displayed in the counter window. vco.clock 20.
6.
; input clock to the EXTAL pin of the ; cpu is set to 20 MHz (only necessary ; if internal clock is used)
Activate the emulator When the emulator is activated a debug-monitor program is loaded into a hidden emulator memory. Afterwards, a bondout reset-signal is inactivated and the monitor program starts. This program allows access to user memory (data.dump, data.list) and cpu-registers, and gives control to start and stop the emulation. system.mode emulint
7.
; system works with internal target clock
Load application file (optional) Application can be loaded by various file formats. UBROF format is often used to load code and symbol information. For information about the load command for your compiler see Compiler. d.load.u iarz180.dbg
8.
;load application file
Set breakpoints (optional) There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed using the Break.List command. breakpoint.set main /program breakpoint.set flags /write
9.
; ; ; ;
set program break on function main set write break on variable ’flags’
Start application Application can be started with giving a break address. For example “go main” starts the application and stops at symbol main. go
; run application
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
7
Quick Start
Troubleshooting
Hang-Up If you are not able to stop the emulation, there may be some typically reasons: Clock Error
The clock lines between the target and the oscillator of the MCU are very short. Therefore normally no problems should occur when using an external crystal. The clock line for all Z80 type processors is very critical.
Analyzer Function
If you switch off the analyzer and the CPU has stopped operation, an invalid display occurs. Make a SYStem.Up command to see the true trace information.
Dual-Port Errors To realize the dual-port access (emulation memory) the BUSREQ-line of the CPU is used. Dual-port accesses are allowed only while no external request to the bus occurs and the CPU cycle is completed. If the emulation CPU is in RESET state of the CPU the system controller may always access the emulation memory. Dual-port errors may occur by the following conditions: 1.
The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is generated.
2.
External DMA requests (single cycles) are too long.
To solve problems with dualport error first increase the SYStem.TimeReq value. Be sure that the SYStem.TimeOut value is bigger than the access time limit. If it is not possible to solve the problem by changing the values, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The internal dual-port access can increase the reaction time for external DMA requests. The performance reduction by the dual-port access is typically 1% with some data windows (dualported) on the screen and may be at max. 5% when using dynamic emulation memory.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
8
Troubleshooting
FAQ
Debugging via VPN Ref: 0307
The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance? The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited: in practice scripts, use "SCREEN.OFF" at the beginning of the script and "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates. Please note that if your program stops (e.g. on error) without executing "SCREEN.OFF", some windows will not be updated. "SYStem.POLLING SLOW" will set a lower frequency for target state checks (e.g. power, reset, jtag state). It will take longer for the debugger to recognize that the core stopped on a breakpoint. "SETUP.URATE 1.s" will set the default update frequency of Data.List/ Data.dump/Variable windows to 1 second (the slowest possible setting). prevent unneeded memory accesses using "MAP.UPDATEONCE [address-range]" for RAM and "MAP.CONST [address--range]" for ROM/ FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified address range only once after the core stopped at a breakpoint or manual break. "MAP.CONST" will read the specified address range only once per SYStem.Mode command (e.g. SYStem.Up).
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
9
FAQ
Target Power Supply Switch Ref: 0103
Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off? Follow the sequence below. If you own an output probe COUT8, connect it to the STROBE output connector. Type PULSE2. and press F1. You will get the pin out of the output probe COUT8. Pin 13 (OUT6) delivers +5 V after the emulator has finished its initialization and 0 V if the emulator is powered off. This can be used to drive a relay via a transistor to switch the target power on and off automatically if the Pulse Generator is not used for other purposes. The schematic of the switching unit can be found in the file TARGETC.CMM. Additionally Pin 13 (OUT6) can be controlled by ICE commands.
Target power supply off. "PULSE2.P +" Target power supply on. "PULSE2.P -" The following Practice command file creates 3 buttons in the Toolbox for:
Target power on Target power off Target power off and QUIT. Adding that file to T32.cmm loads the buttons automatically after startup. _wwwlinkfaq/targetc.cmm Wrong Location after Break Ref: 0030
Z80C15 Z84C11/C13/ C15 Emulation Ref: 0047
Why is the location after break wrong? Most emulators use some bytes of user stack for the break system. Therefore it is necessary to have valid stack, if single step or breakpoints are used. How must a Z84C15 target be prepared for the emulation, using a Z80 emulator? To run the emulation mode on the target CPU, the EV pin must be tied to "high". The TRACE32 Z80 emulation probes of the Z84C11/C13/15 emulators, drive the EV pin with a 100 Ohm resistor. On the target, it is recommended to connect the EV pin via a 1 kOhm resistor to ground.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
10
FAQ
Basics The ICE-80 emulation head supports all Z80 derivatives from Zilog, Renesas and Toshiba and further the 8085 from Intel or NEC. The adaption to different probes is done by changing modules. Modules support both DIL and PLCC versions, if available. The maximum frequency of the base module is 20 MHz. The modules are delivered with the fastest available chip. The emulation probes support all modes of the CPUs, some modes without dual-port access capability. The 8085, Z80 and TMPZ84Cxx probes support 256 banks with 64K each. The Z180 like probes may run with 16 banks of 1 MByte each. An additional slot in the base module offers upgrading with the Port-Analyzer to get timing and state trace features for all MCU I/O ports.
Peripherals Window After the internal IO base address has changed (Z180,Z181,Z182), the Peripherals Windows must be reprogrammed. Use the PER.RP command, otherwise the windows has a wrong content.
Z80182 Emulation hints IMPORTANT: For emulation without a target or for emulation of a target but without a CPU on it, put a Z80182 CPU into the socket at the Z182 adapter. For emulation of a target with a CPU on it, remove the Z80182 CPU from the Z182 adapter. In order to emulate a Z80182 target, the CPU on the target (if there is one) must stay in the special mode (Mode1). This mode is selected if pin EV1 is connected to VCC, and pin EV2 is connected to GND. It cannot be accomplished through any emulator instruction. The user must cater for the correct signal levels by himself. For a normal operation without an emulator (Mode0), it is recommended to connect both pins to the appropriate level via 2 high-resistive resistors. The Z80182 probe is able to drive these pins via 100 Ohm resistors to Mode1. Bear in mind, that the Z80182 is emulated with a Z180 CPU. The internal peripherals should only be moved to the IO base addresses xx00,xx40 or xx80. The additional internal peripherals (start at IO:xxD8) can only be accessed if the emulator is in mode Emulation External or Emulation Internal.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
11
Basics
Probe Configuration Z80 : = Jumper open
I = Jumper closed
Z80-DIL Z84C00-DIL
Z84C00 20MHz
I : I :
.................
Z80-PLCC Z84C00-PLCC
Z84C00 20MHz
: I I :
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
12
Basics
Z84C01
..
I : Z84C01 10MHz : I
Z84C50 with XTAL
.. Z84C50
I : Z84C01 10MHz : I
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
13
Basics
Z84C50 without XTAL (CLK in) Only external Clock
.. Z84C50
: I Z84C01 10MHz I :
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
14
Basics
HD64180
HD64180
I
HD64180
Z180
:
Z180MPU 10..15MHz
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
15
Basics
84C11/13/15
Z84C11/15
Z84C00 20MHz 1 : I I : II:II
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
16
Basics
Emulation Modes E::w.sys system Down Up RESet cpu-type Z180
BankMode OFF INTern EXTern Extended
Mode RESet Analyzer Monitor ResetDown ResetUp NoProbe AloneInt AloneExt EmulInt EmulExt
Clock VCO Low Mid High
TimeReq 1.000ms TimeOut 50.000us Line BusReq
Access Nodelay REFresh Request Denied
CPU Mode0 Mode1 Mode2 Mode3 EXTern
Option REFresh RamWait FAST DOut OMCR FF
BankFile G:\LOT\BNK80.BNK
The emulation head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode command.
Format:
SYStem.Mode
:
ResetDown ResetUp AloneInt AloneExt EmulInt EmulExt
Reset Down
Target is down, all drivers are in tristate mode.
Reset Up
Target has power, drivers are logically in inactive state, but not tristate.
Alone Internal
Probe is running with internal clock, driver inactive, the dual-chip target CPU is not activated.
Alone External
Probe is running with external clock, driver inactive, the dual.chip target CPU is not activated.
Emulation Internal
Probe is running with internal clock, strobes to target are generated.
Emulation External
Probe is running with external clock, strobes to target are activated.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor. ©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
17
Basics
SYStem.Clock
Clock generation
Format:
SYStem.Clock
:
VCO High Mid Low
VCO
Variable frequency 1 … 35 MHz.
Low, Mid, High
2.5, 5.0 or 10.0 MHz.
SYStem.CPU
MCU operation modes
Format:
SYStem.CPU
:
M0…M3, EXTERN
This command selects the operation mode of the CPU (only Z84C01, HD647180). The command may only be executed when the system is down and must be set to the correct operation mode. External mode pins from the target system are not sensed.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
18
Basics
SYStem.Access
Dual-port access
Format:
SYStem.Access
:
Nodelay REFresh Request Denied
Nodelay
The dual-port access is made between two bus cycles. The max. frequency is 8 MHz on Z80 and Z180 probes.
REFresh
The dual-port access is made on CPU refresh cycles. On Z180 probes the refresh function must be switched on. Z80 probes run till 10 MHz and Z180 probes with max. speed if 2 waits for the refresh is specified. 8085 probes do not support this operation mode.
Request
This operation allows operation up to the max. speed of the CPU, it runs only on processors with open BUSREQ/BUSACK lines (Not HD647180, HD648180). The CPU speed is slowed down about 1% by dual-port accesses or 5% by refreshing DRAMs as emulation memory.
Denied
This mode is available for all types of CPUs. No dual-port access is possible on realtime emulation.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
19
Basics
General Settings and Restrictions
Restrictions NMI Routines
NMI routines use the IFF1 and IFF2 register. On breakpoint execution there is no distinction between IFF1 and IFF2 register. So the next RETN instruction may set the interrupt flag incorrectly. Running with realtime NMI routines are executed correctly.
Power Down Modes
All power down modes which stop the clock generator make fatal emulator errors. On emulation change to an other operation mode.
HALT
Realtime emulation may not be stopped if the CPU is in the HALT state. The command Break.Halt activates the breakpoint logic and forces a NMI signal to recover from HALT state.
Trace Internal Registers
Write cycles to internal registers are always traced correctly. On read cycles data may be invalid on Z180 and HD64180 probes. The Z181 CPU and the HD647180 enable trace on internal read cycles. On Z181 the ROM emulator mode bit (0ED.1) must be set.
8 Bit I/O
When 8-Bit I/O addressing is active (System.Option IO8) it is not possible to map attributes (e.g. intern/extern, wait states) to single I/ O locations.
SYStem.Line BusReq
Format:
Bus access control
SYStem.Line BusReq [ON | OFF] (Z80) SYStem.Line HOLD [ON | OFF] (8085)
This option allows DMA access without running realtime emulation. External DMA circuits are not stopped on breakpoints.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
20
General Settings and Restrictions
SYStem.Option REFresh
Format:
Trace option
SYStem.Option REFresh [ON | OFF]
Normally refresh cycles are not traced by the analyzer. On high speed operation with Z80 probes (f > 12.5 MHz) no trace on refresh cycles is allowed as the cycle time of the analyzer must be 150 ns at minimum (ECC8). If activated, the refresh cycles can cause the data selectors to be triggered by refresh cycles, even if the address is not hit by the cycle. To prevent occasionally triggers, address selectors of the trigger unit should be combined with the condition 'N:REFRESH'.
SYStem.Option
Wait options
Format:
SYStem.Option
:
FAST [ON | OFF] RamWait [ON | OFF] Polarity [ON | OFF]
FAST
Must be set to ON with emulation frequency higher than 12 MHz (Z80, Z180).
RamWait
This signal generates 1 wait state for all bus cycles that sense the wait input line. As the generation of the wait signal is sometimes very critical in high-speed Z80 systems, this option may help to solve problems with external wait state generators.
PullWait
An additional pull-up resistor on the WAIT input line is switched on. Normally needed in standalone mode (Z84C50, Z84C11, Z84C15).
SYStem.Option OMCR
OMCR register
Format:
SYStem.Option OMCR
:
0..0FF
The Z180 and Z181 probes must be switched to different internal modes resulting from different bus signals and timings if the OMCR register is changed. The value in this field must be the same value as set by the target software. The CPU is automatically programmed to this pattern on activating the emulation system (SYStem.Up). ©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
21
General Settings and Restrictions
SYStem.Option DOut
Format:
Bus control for daisy chain
SYStem.Option DOut [ON | OFF]
One big problem in Z80 systems is handling the RETI instruction. This command must be read by the peripherals together with the M1 signal to clear the interrupt daisy chain. No problem occurs if the program is running from the target memory as the data flow is the same like in the system running without emulator. If the program is mapped to internal the peripherals may see other code than the emulation CPU. In small target systems (no data buffer between CPU and peripherals) the internal code may be send to the data system if DOUT is on. The memory is accessed internal and no memory on the target should block the bus (remove EPROMs). If a data buffer between CPU and peripherals exists in the target, there are also some possible solutions: 1.
Replace the EPROM by a RAM and load the code to the target.
2.
Program the RETI instruction to a fixed address in the EPROM on the target and exit every interrupt routine at this location.
3.
Use an EPROM simulator to load your program.
4.
Some systems use special boot modes to change the data bus direction.
SYStem.Option IO8
Format:
Size of I/O space
SYStem.Option IO8 [ON | OFF]
This option must be set when only 8-bit I/O addresses are used. The option must be set before any memory is mapped or breakpoints are set. Memory attributes, like wait states or protection, are not handled for 8-bit I/ O address.
SYStem.Option V33
Format:
Voltage sense
SYStemOption V33 [ON | OFF]
The threshold level for the power-down sense is reduced to 2.8 V for operation with 3.3 V targets.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
22
General Settings and Restrictions
Exception Control
E::w.x exception OFF ON RESet
Activate OFF RESet BusReq
Enable OFF ON RESet BusReq NMI Int0 Int1 Int2
Trigger OFF ON RESet BusReq NMI DREQ1 PULS
Puls OFF RESet Int0 Int1 Int2 NMI BusReq
Puls Single Width 1.000us PERiod 0.000 Vector 00 (000.)
The exception control system varies between different processors. The window shown here is for the HD64180 processor.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
23
Exception Control
Schematics RESET RESET (Z80, Z180, Z181) VCC +1
TRACE
22k RESETTarget +1 -Enable
-Puls -Activate
&1
RESET CPU
1mA ResetOut RESET (8085) VCC +1
TRACE
22k RESETINTarget +1 -Enable
-Puls -Activate
&1
RESETIN- CPU
RESOUT CPU +1
RESOUT Target
ResetOut
Format:
eXception.Enable RESet [ON | OFF]
Format:
eXception.Activate RESet [ON | OFF]
Format:
SYStem.M1Out
Format:
SYStem.RESetOut
M1Out
Z80 PIO may be reset by sending a M1 signal without MRQ/IORQ signals.
RESet
Activates RESET line. Enables RESET line.
RESetOUT
Forces RESET to target. ©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
24
Exception Control
BUSREQ Line VCC +1
TRACE
22k BUSREQTarget +1 -Enable M -Line U RUN----> X
-Puls -Activate
Format:
eXception.Enable BusReq [ON | OFF]
Format:
eXception.Activate BusReq [ON | OFF]
Format:
SYStem.Line BusReq [ON | OFF]
Format:
eXception.Enable HOLD [ON | OFF]
Format:
eXception.Activate HOLD [ON | OFF]
Format:
SYStem.Line HOLD [ON | OFF]
BusReq, HOLD
Enables BR line from target. Activates BR, HOLD line.
&1
BUSREQ CPU
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
25
Exception Control
Interrupt Control Interrupts may be enabled separately for every interrupt input. INT0,INT1,INT2,NMI input
VCC +1
TRACE
R1 INTxTarget +1 -Enable
&1
INTx CPU
-Puls
R1 = 22K
eXception.Activate
Force exception
Format:
eXception.Activate HOLD [ON | OFF]
Format:
eXception.Activate RESET [ON | OFF]
Format:
eXception.Activate OFF
HOLD
Activates the HOLD line.
RESET
Activates the $A01$ line.
OFF
No activation of any exception line.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
26
Exception Control
eXception.Enable
Enable exception
Format:
Exception.Enable NMI [ON | OFF]
Format:
Exception.Enable TRAP [ON | OFF]
Format:
Exception.Enable Int0 [ON | OFF]
Format:
Exception.Enable Int1 [ON | OFF]
Format:
Exception.Enable Int2 [ON | OFF]
Format:
Exception.Enable RST55 [ON | OFF]
Format:
Exception.Enable RST65 [ON | OFF]
Format:
Exception.Enable RST75 [ON | OFF]
NMI, TRAP, INTR
Enables NMI from target.
Int0, Int1, Int2
Enables interrupt line from target.
RST55, RST65, RST75
Enables trap line.
Int0, Int1, Int2, INTR, NMI, RST55, RST65
Forces pulse generator to interrupt.
The NMI line is not traced directly. A special circuit samples only the falling edge and makes it visible in the next cycles. This allows correct trigger only to edges and not to static levels. The pulse width of the exception generator defines the length of the interrupt request. As the NMI signal is edge sensitive, only one interrupt is executed. On INT0 a pulse executes only one interrupt, but if there is no bus cycle within the pulse active time, no interrupt is generated. Exception vectors are all even values from 0 to 254 (0 to 7 for the 8085). On interrupt stimulation no INTA cycles are made to the target. Therefore stimulated interrupts may run in parallel to interrupts generated by peripherals on the target system. ©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
27
Exception Control
eXception.Trigger
Trigger on exception
Format:
eXception.Trigger BR [ON | OFF]
Format:
eXception.Trigger DREQ1 [ON | OFF]
Format:
eXception.Trigger HOLD [ON | OFF]
Format:
eXception.Trigger NMI [ON | OFF]
Format:
eXception.Trigger Pulse [ON | OFF]
Format:
eXception.Trigger RES
Format:
eXception.Trigger TRAP [ON | OFF]
Format:
eXception.Trigger OFF
Format:
eXception.Trigger ON
BR
Trigger on BR line.
DREQ1
Trigger on DREQ1 line.
HOLD
Trigger on HOLD line.
NMI
Trigger on NMI line.
Pulse
Trigger on Pulse line.
RES
Trigger on RES line.
TRAP
Trigger on TRAP line.
ON
Trigger on all exception lines.
OFF
No trigger on any exception lines.
[ON | OFF]
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
28
Exception Control
eXception.Pulse
Stimulate exception
Format:
eXception.Pulse BR
Format:
eXception.Pulse HOLD
Format:
eXception.Pulse INTR
Format:
eXception.Pulse NMI
Format:
eXception.Pulse RES
Format:
eXception.Pulse OFF
BR
Stimulate BR line.
HOLD
Stimulate HOLD line.
INTR
Stimulate INTR line.
NMI
Stimulate NMI line.
RES
Stimulate RES line.
OFF
No stimulation on any exception line.
eXception.Vector
Define vector
Format:
Exception.Vector 0..0FE (Z80)
Vector
Defines vector for interrupt simulation.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
29
Exception Control
MAP.DMA
DMA area
Format:
MAP.DMA
Format:
MAP.NODMA
If using the DMA and switching of the M1 signal the emulator cannot distinguish between opfetch cycles and dma read cycles. This may result in fatal errors executing breakpoints. As usually the DMA doesn't access the program area the data area can be marked for the emulator by the mapper. Only DMA memory read areas should be mapped.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
30
Exception Control
EEPROM Management The EEPROM of the HD648180 may be initialized with standard set or load commands using the storage class EEPROM: d.s EEPROM:0B600 2 3 4 5
; setting bytes
d.s EEPROM:0B600++0x1ff 0x0ff
; clear EEPROM
d.load.b epromdata EEPROM:B600
; loading data
This function is only available on probes with internal EEPROM.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
31
EEPROM Management
Using the MMU for Banked Target Systems Banking as described in this chapter refers to address extension of Z80/8085 processors, not the internal MMU of the Z180 family. In banked systems the upper address lines are either supplied internally or by the external bank probe. 8 additional lines offer 256 different memory banks. Accessing the different pages is done by extending all memory and pc addresses to 24 bit. The address bits A16 to A23 select the memory bank. Every command which makes a memory access first calls a special bank driver subroutine to select the temporary memory bank. On realtime emulation the bank number is traced on the upper 8 bits of the address bus. The breakpoints function stores the bank address back to the MSB of the program counter.
SYStem.BankFile
Format:
Select banking file
SYStem.BankFile
This command loads the bank driver. The bank driver is a special subroutine to select the actual bank. Loading a special bank driver gives a maximum of flexibility to the user. A bank address delivered by the emulator may be used to set microcontroller ports or external MMUs in the target system. The bank file consists of a code number defining the bank operation mode and a code area which consists of a subroutine to set the correct bank state. Writes to internal CPU ports may be executed directly, while ports in target systems must be accessed by a special system call (see end of this chapter). The internal bank address is placed in accu A when calling the subroutine. One return the function must clear A when working on a Z180 with external banking. The write function to the target system needs the address in BC and the data in accu A. The BNK register holds the physical bank number. The PP (Program Pointer) register hold the logical 24-bit PC address. The translation between logical bank and physical bank (also for the common areas and I/O space) is done by the MMU command.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
32
Using the MMU for Banked Target Systems
SYStem.Bank
Select bank mode
Format:
SYStem.Bank
:
OFF INTernal EXTernal Extended
Internal Bank Internal bank to support paged EPROMs. The internal bank register is set by writing to an address range selected by the command MAP.Bank. ; This example uses a common program area on 0--3fffh ; a banked area from 4000--7fff with 4 banks map.res map.mirror p:0x0--0x03fff p:0x10000 map.mirror p:0x0--0x03fff p:0x20000 map.mirror p:0x0--0x03fff p:0x30000 map.mirror io:0x0--0xffff io:0x10000 map.mirror io:0x0--0xffff io:0x20000 map.mirror io:0x0--0xffff io:0x30000 map.bank 0x4000--0x7fff mmu.on system.bankfile banksel.bnk system.up
; reset mapper ; mirror for common area
; ; ; ;
set area of banked eprom activate translation for addresses load bank file
Bank drivers are special subroutines (max. length 256 bytes) to set the bank or an external MMU: org 17FFH db
1
bank:
; select internal mode ; accu a is bank address
org 1800h
; destination area in system memory
ld e,0 ld hl,1800h call 100h
; ; ; ; ; ; ;
ret
physical bank 0 set hl to banked area subroutine to write byte to target system setting the page register in the EPROM hl is address, A is date return
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
33
Using the MMU for Banked Target Systems
External Bank External banked systems use a register or output pins of the CPU to generate the upper memory addresses. These lines must be feedback to the emulator with the bank probe. Unused inputs of the bank probe must be grounded (or jumpered to ground pin). ; This example uses a common program area on 0--3fffh ; a banked area from 4000--7fff with 4 banks map.res map.mirror p:0x0--0x3fff p:0x10000 map.mirror p:0x0--0x3fff p:0x20000 map.mirror p:0x0--0x3fff p:0x30000 map.mirror io:0x0--0xffff io:0x10000 map.mirror io:0x0--0xffff io:0x20000 map.mirror io:0x0--0xffff io:0x30000 mmu.on system.bankfile banksel.bnk system.up
; reset mapper ; mirror for common area
; activate translation for ; addresses ; load bank file
This example selects the bank by internal port 45H bit 6 and 7: org 17FFH db
2
; select external mode
bank:
; accu a is bank address org 1800h push ld in and ld pop rrca rrca or out ret
; destination area in system memory
af bc,45h a,(c) 03fh e,a af
e (c),a
Now the bank select is done by an external register selected at A0h: org 17FFH db
2
;select external mode
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
34
Using the MMU for Banked Target Systems
bank:
; accu a is bank address org 1800h
; destination area in system memory
ld bc,0a0h call 110H
; ; ; ; ; ;
xor a ret
set BC to banked area subroutine to write byte to emulation ram setting bank register BC is address, A is date clear BANK (only required for Z180) return
Extended Extended is used to extend the address space of Z180 CPUs. Up to 16 banks of 1MByte can be used. The bank select routines gets A16..A23 in A and returns the remaining A16..A19 for the CPU address in A. The upper 4 bits are used to specify the 16 banks. org 17FFH db
4
bank:
; select extended mode ; accu a is bank address * 16
org 1800h
; destination area in system memory
push af sra a sra a sra a sra a ld bc,0a0h call 110H pop af and 0fh ret
; ; ; ; ; ;
shift right set BC to banked area subroutine to write byte to emulation ram setting bank register A16..A19 will be set by the CPU return
The next examples shows the map and load commands with MMU translation for common ares: ; This example uses a common program area on 0--7fffh ; and a banked area from 8000--ffff with 2 banks ; I/O is not banked and uses 8-bit addressing system.option io8 on system.bankfile banksel.bnk system.mode ai
;load bank file (uses physical ; banks)
map.res map.mirror p:0x0--0x7fff p:0x10000 map.mirror io:0x0--0x7fff io:0x10000
; reset mapper ; mirror for common area ; mirror for I/O accesses
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
35
Using the MMU for Banked Target Systems
map.ram p:0--0ffff map.ram p:18000--1ffff map.intern
; map memory in banks and common
symbol.reset mmu.reset mmu.create p:00000--07fff mmu.create p:08000--0ffff mmu.create p:00000--07fff mmu.create p:18000--1ffff mmu.on
p:00000--07fff p:08000--0ffff p:10000--17fff p:18000--1ffff
d.load.u applic.dbg /nc
; load file from ICCZ80 (IAR)
Parameters for Banking Program The following parameters are passed to the banking program: D
Reason for call 0 = Init 1 = Read Memory 2 = Write Memory 3 = Go 4 = Break
A
Bank Number
HL
Address (PC for Go and Break)
IX
Pointer to registers (only Go and Break) IX+28 = Bank
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
36
Using the MMU for Banked Target Systems
Memory and IO Access Routines The following routines are available in the emulation control monitor to access external memory or i/o: Addr
Function
Address
Data
Result
100H
MemWrite
E-HL
A
110H
IOWrite
BC
A
120H
MemRead
E-HL
-
A
130H
IORead
BC
-
A
Using the MMU for Z180 This command and the commands MMU support the built-in MMU of the Z180 processors. The analyzer and all memory systems and breakpoints are based on the physical address. The display in the analyzer can be both physical or logical addresses. A logical address can have two formats: smaller than 64K or larger. Smaller addresses are assumed to be an logical address as seen by the CPU in the current
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
37
Using the MMU for Banked Target Systems
MMU configuration. If an address is larger than 64K, the address bits A16 to A23 define the bank base address used for the BBR or CBR register. Logical above 64K addresses should only be used, if the MMU registers were already setup. The following schematic shows these relations for some examples: preset: CBAR=84, BBR=10, CBR=20 logical address:
5
0
CBR/BBR = 50 -->
logical address:
0
0
0
0
1
physical address:
0
(Hex)
1567
4
(Hex)
MMU Bank Area physical address: 04567 +BBR 10--=14567
d e f 16 bit current-mmu logical CPU address --> -->
(Hex)
physical address: 54567
5 6 7 16 bit current-mmu logical CPU address --> -->
logical address:
5 6 7 16 bit logical CPU address
5 6 7 16 bit current-mmu logical CPU address -->
logical address:
4
0
c
(Hex)
COMMON1 Area physical address: 0cdef +CBR +20--=2cdef
To activate the correct address translation for breakpoints, the MMU command must be activated. The following example loads a banked application: mmu.off map.ram 0x0--0x0fffff map.i mmu.on d.load.u iarz180.dbg
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
38
Using the MMU for Banked Target Systems
The next example loads a banked application in two logical units: ;CBAR=84, CBR=0, BBR=10 or 20 mmu.reset symbol.reset map.ram 0x0--0x0fffff map.i mmu.create 0x104000--0x107fff mmu.create 0x204000--0x207fff mmu.on d.load.b bank1.cod 0x104000 /nosymbol d.load.b bank2.cod 0x204000 /nosymbol d.load.b common.cod 0x0 /nosymbol d.load.sym bank1.sym /noclear symbol.reloc p:0x100000 0x4000--0x4fff d.load.sym bank2.sym /noclear symbol.reloc p:0x200000 0x4000--0x4fff d.load.sym common.sym /noclear
The MMU translation table is used for translating physical addresses (analyzer, trigger) to logical addresses and logical addresses to physical addresses. The logical to physical translation is done by reading the MMU registers of the CPU and calculating the physical address.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
39
Using the MMU for Banked Target Systems
Memory Classes
Access Class
Description
C: D: P: AD: AP: IO:
Specify the same address-area (CPU-access) on Z80 family
Absolute (physical) addressing for 64180 IO access
E: ED: EP: EAD: EAP: EIO:
Emulation memory access
EEPROM:
EEPROM write (HD648180)
Absolute (physical) addressed emulation memory
C:, P: and D: This storage classes operate on the same physically memory. They are only used to be compatible with other emulation probes. CPU internal registers and memory may not be accessed dual-ported, by mapping memory to the same address range data written to the internal memory are also present in the emulation memory. IO: The IO address is normally 16 bit. The commands Data.Out and Data.In uses this storage classes on default. d.i 0x34 3
; read 3 bytes from address 34H
d.o 0x34 55 66
; sends 2 bytes to address 34H
EEPROM: This storage class is used to program the internal EEPROM. On read cycles there is no difference to the access mode with C: or D:. On write cycles the monitor program executes an EEPROM write protocol. d.s EEPROM:0E00 " Test " d.load.b test.bin EEPROM:0e00
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
40
Memory Classes
A:, AD:, AP: The absolute access storage classes can be used if access to a physical memory location is required. The storage class is only useful on Z180/HD64180 devices.
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
41
Memory Classes
State Analyzer
Keywords for the Trigger Unit General Keywords for the Trigger Unit Input Event
Meaning
Analyzer Hardware ECC8
HAC
HA120
SA120
DATAREAD, MEMRD
Data read access (MEMRDD or MEMRDN)
X
X
X
X
DATAWRITE, MEMWR
Data write access (MEMWRD or MEMWRN)
X
X
X
X
DMA
DMA cycle (IORDD or IOWRD or MEMRDD or MEMWRD)
X
X
X
X
FETCH
Program fetch cycle (SFETCH or OPFETCH)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HALT IN, IORD
IORDD or IORDN
INTACK IO
IORD or IOWR
X
X
X
X
IOE, IORQ
IO or INTACK
X
X
X
X
IORD, IN
IORDD or IORDN
X
X
X
X
IORDD
I/O read by DMA
X
X
X
X
IORDN
I/O read by CPU
X
X
X
X
IORQ, IOE
IO or INTACK
X
X
X
X
IOWR, OUT
IOWRD + IOWRN
X
X
X
X
IOWRD
I/O write by DMA
X
X
X
X
IOWRN
I/O write by CPU
X
X
X
X
LIR, M1
FETCH or INTACK
X
X
X
X
M1, LIR
FETCH or INTACK
X
X
X
X
ME, MREQ
OPMEM or REF
X
X
X
X
MEM
MEMRD or MEMWR
X
X
X
X
MEMIO
MEM or IO
X
X
X
X
MEMRD
Data access read (MEMRDD or MEMRDN)
X
X
X
X
MEMRDD
memory read by DMA
X
X
X
X
MEMRDN
memory read by CPU
X
X
X
X
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
42
State Analyzer
MEMWR
Data access write (MEMWRD or MEMWRN)
X
X
X
X
MEMWRD
memory write by DMA
X
X
X
X
MEMWRN
memory write by CPU
X
X
X
X
MREQ, ME
OPMEM or REF
X
X
X
X
OPFetch
M1 cycle
X
X
X
X
OPMEM
FETCH or MEM
X
X
X
X
OPMEMIO
IO or OPMEM
X
X
X
X
OUT, IOWR
IOWRD or IOWRN
X
X
X
X
PORT
Input line from port analyzer
X
X
Read
FETCH or IORD or MEMRD
X
X
X
X
REF
REFESH cycle
X
X
X
X
Wait0..Wait6
Waitstates 0..6
X
X
WaitX
Waitstates greater 6
X
X
Write
IOWR or MEMWR
X
X
X
X
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
43
State Analyzer
Z80/ED/FD/CB Keywords for the Trigger Unit Input Event
Meaning
Analyzer ECC8
SFETCH
hardware HAC
second M1 after switch
HA120
SA120
X
X
Z180 Keywords for the Trigger Unit Input Event
Meaning
Analyzer ECC8
hardware HAC
HA120
SA120
DREQ1
X
X
INT, INT0
X
X
INT0..INT2
X
X
NMI
X
X
TEND1
X
X
TOUT
X
X
8085 Keywords for the Trigger Unit Input Event
Meaning
Analyzer ECC8
hardware HAC
HA120
SA120
INTR
X
X
RST55
X
X
RST65
X
X
RST75
X
X
TRAP
NMI signal edge
X
X
TRAPIN
NMI signal
X
X
For not CPU-specific keywords, see non-declarable input variables in “ICE/FIRE Analyzer Trigger Unit Programming Guide” (analyzer_prog.pdf).
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
44
State Analyzer
Keywords for the Display NMI
NMI interrupt (Z80,Z180)
Int0
INT interrupt (Z80,Z180)
Int1
Interrupts (Z180)
Int2 TRAP
Interrupt lines (8085)
INTR RST55,RST65,RST75 TRAPIN
DREQ1
DMA-lines Z180
TEND1 TOUT
timer (Z180)
RES ALE
ALE signal (8085)
BR, BA
BUS interface lines (Z80,Z180)
HOLD, HLDA
BUS interface lines (8085)
SOD, SID
(8085)
CKA0
(Z180)
CKA1 CKS EC
'E' Clock (Z180)
SLEEP
sleep occurred before this cycle (Z180)
TXS, RXS
Serial interface lines (Z180)
TXA0, RXA0 RTS0, CTS0 TXA1, RXA1
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
45
State Analyzer
Port Analyzer
Keywords for the Port Analyzer (Z180,84C15) A0 .. A7
Port A
B0 .. B7
Port B
C0 .. C7
Port C
D0 .. D7
Port D
E0 .. E7
Port E
NMI
NMI interrupt
Int0
INT interrupt
Int1
Interrupts
Int2 DREQ1
DMA-lines
TEND1 TOUT
timer
RES BR, BA
BUS interface lines
CKA0 CKA1 CKS EC
'E' Clock
SLEEP
sleep line
TXS, RXS
Serial interface lines
TXA0, RXA0 RTS0, CTS0 TXA1, RXA1
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
46
Port Analyzer
Keywords for the Port Analyzer (Z181) PIA10 .. PIA17
Port 1
PIA20 .. PIA27
Port 2
D6 .. D7
Port D
E0 .. E7
Port E
W
W line
SYNC
SYNC line
RXD, TXD
Communication controller
TRXC, RTXC DTR, RTS CTS, DCD CSRAM, CSROM
Chip selects
IEI, IEO
Interrupt daisy chain
NMI
NMI interrupt
Int0
INT interrupt
Int1
Interrupts
Int2 DREQ1
DMA-lines
TEND1 TOUT
timer
RES ALE
ALE signal (8085)
BR, BA
BUS interface lines
CKA0 CKA1 CKS EC
'E' Clock
SLEEP
sleep line
TXS, RXS
Serial interface lines
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
47
Port Analyzer
TXA0, RXA0 RTS0, CTS0 TXA1, RXA1
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
48
Port Analyzer
Additional Trace Channels Not used trace channels on Port-Analyzer are connected to pins placed on the emulation modul. Module Z80/Z84C00/Z84C01/Z84C50 Module Z180
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
49
Additional Trace Channels
Module 8085 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 40 39 38 37 36 35 34 33
Port.A0 Port.A1 Port.A2 Port.A3 Port.A4 Port.A5 Port.A6 Port.A7
32 31 30 29 28 27 26 25
Port.B0 Port.B1 Port.B2 Port.B3 Port.B4 Port.B5 Port.B6 Port.B7
24 23 22 21 20 19 18 17
Port.C0 Port.C1 Port.C2 Port.C3 Port.C4 Port.C5 Port.C6 Port.C7
16 15 14 13 12 11 10 9
Port.D0 Port.D1 Port.D2 Port.D3 Port.D4 Port.D5 Port.D6 Port.D7
8 7 6 5 4 3 2 1
Port.E0 Port.E1 Port.E2 Port.E3 Port.E4 Port.E5 Port.E6 Port.E7
7 8
5 6
3 4
1 2
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
50
Additional Trace Channels
Module Z181 Module Z84C11 Module Z84C13 Module Z84C15 9 10
1 2 3 4 5 6 7 8 9 10
7 8
5 6
3 4
1 2
Port.A0 Port.A1 Port.A2 Port.A3 Port.A4 Port.A5 Port.A6 Port.A7 GND GND
Module Z80182 15 13 11 9 16 14 12 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
7 8
5 6
3 4
1 2
Port.A00 Port.A01 Port.A02 Port.A03 Port.A04 Port.A05 Port.A06 Port.A07 GND GND A18 GND A18TO +5V GND GND
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
51
Additional Trace Channels
Module HD648180 15 13 11 9 16 14 12 10
7 8
1 2 3 4 5 6 7 8
Port.A0 Port.A1 Port.A2 Port.A3 Port.A4 Port.A5 Port.A6 Port.A7
9 10 11 12 13 14 15 16
Port.B0 Port.B1 Port.B2 Port.B3 Port.B4 Port.B5 Port.B6 Port.B7
5 6
3 4
1 2
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
52
Additional Trace Channels
Compilers
Language
Compiler
Company
Option
Comment
ASM
HP-64000-ASM
HP
HP
ASM
MI-C
ROSE
SYM
Source level debugging Source level debugging
ASM C
AS ICCZ80
SDSI IAR Systems AB
SDS UBROF
C
MCCZ80
IEEE
C
HT-Z80
C C C PLM
MI-C UNIWARE-C CC ISIS-PL/M
Mentor Graphics Corporation Microchip Technology Inc. ROSE SDSI Softools Inc. Intel Corporation
Z180 and banking sup. no banking support
HITECH SYM/LOC SDS UBROF SYM/LOC
No type information
no type/local info
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
53
Compilers
3rd Party Tool Integration
CPU
Tool
Company
ALL ALL ALL
ADENEO X-TOOLS / X32 CODEWRIGHT
ALL
CODE CONFIDENCE TOOLS CODE CONFIDENCE TOOLS EASYCODE ECLIPSE RHAPSODY IN MICROC RHAPSODY IN C++ CHRONVIEW LDRA TOOL SUITE UML DEBUGGER
Adeneo Embedded blue river software GmbH Borland Software Corporation Code Confidence Ltd
ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL
ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL
ATTOL TOOLS VISUAL BASIC INTERFACE LABVIEW
CODE::BLOCKS C++TEST RAPITIME DA-C TRACEANALYZER SIMULINK TA INSPECTOR UNDODB VECTORCAST UNIT TESTING VECTORCAST CODE COVERAGE WINDOWS CE PLATF. BUILDER
Host Windows Windows Windows
Code Confidence Ltd
Linux
EASYCODE GmbH Eclipse Foundation, Inc IBM Corp. IBM Corp. Inchron GmbH LDRA Technology, Inc. LieberLieber Software GmbH MicroMax Inc. Microsoft Corporation
Windows Windows Windows Windows Windows Windows Windows Windows Windows
NATIONAL INSTRUMENTS Corporation Open Source Parasoft Rapita Systems Ltd. RistanCASE Symtavision GmbH The MathWorks Inc. Timing Architects GmbH Undo Software Vector Software
Windows
Windows Windows Windows Windows Windows Windows Linux Windows
Vector Software
Windows
Windows
Windows
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
54
3rd Party Tool Integration
Realtime Operation Systems
Name
Company
Comment
CMX-RTX VRTX80
CMX Systems Inc. Mentor Graphics Corporation
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
55
Realtime Operation Systems
Emulation Frequency The emulation probe is designed for running with CPUs up to 20 MHz. The max. speed is limited by the memory speed and the wait states used for memory access. The CPU type (Z80 or Z180) and some operation options (e.g. Refresh, dual-port access) also affect the max. frequency.
Module
CPU
F-W015
F-W035
S-W015
S-W035
S-W115
S-W135
DRAM
LA-6665 LA-6665 LA-6667 LA-6691 LA-6661 LA-6661 LA-6661 LA-6665 LA-6668 LA-6665 LA-6661 LA-6661 LA-6661 LA-6661 LA-6661 LA-6661 LA-6661 LA-6661 LA-6665
HD64180R1 HD64180Z HD647180X0 HD648180W TMP8085 TMPZ84C00 TMPZ84C013 TMPZ84C015 Z80180 Z80181 Z80182 Z8400 Z84013 Z84015 Z84C00 Z84C01 Z84C13 Z84C15 Z84C50 Z8S180
10.0+ 15.0+ 8.0+ 6.0+ 5.0+ 8.0+ 10.0+ 10.0+ 15.0+ 12.5+ 10.0+ 8.0+ 10.0+ 10.0+ 20.0 10.0+ 10.0+ 10.0+ 10.0+ 20.0
10.0+ 15.0 8.0+ 6.0+ 5.0+ 8.0+ 10.0+ 10.0+ 15.0 12.5+ 10.0+ 8.0+ 10.0+ 10.0+ 13.3 10.0+ 10.0+ 10.0+ 10.0+ 15.0
10.0+ 15.0+ 8.0+ 6.0+ 5.0+ 8.0+ 10.0+ 10.0+ 15.0+ 12.5+ 10.0+ 8.0+ 10.0+ 10.0+ 14.5 10.0+ 10.0+ 10.0+ 10.0+ 16.0
10.0+ 12.6 8.0+ 6.0+ 5.0+ 8.0+ 10.0+ 10.0+ 12.6 12.5+ 10.0+ 8.0+ 10.0+ 10.0+ 10.7 10.0+ 10.0+ 10.0+ 10.0+ 12.6
10.0+ 15.0+ 8.0+ 6.0+ 5.0+ 8.0+ 10.0+ 10.0+ 15.0+ 12.5+ 10.0+ 8.0+ 10.0+ 10.0+ 20.0+ 10.0+ 10.0+ 10.0+ 10.0+ 20.0+
10.0+ 15.0+ 8.0+ 6.0+ 5.0+ 8.0+ 10.0+ 10.0+ 15.0+ 12.5+ 10.0+ 8.0+ 10.0+ 10.0+ 20.0+ 10.0+ 10.0+ 10.0+ 10.0+ 20.0+
10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
56
Emulation Frequency
Emulation Modules
Module Overview LA-6660
HD647180X0
PLCC84
TMPZ84C00 TMPZ84C00
DIL40 PLCC44
Z8400 Z8400
DIL40 PLCC44
Z84C00 Z84C00
DIL40 PLCC44
Z84C01
PLCC44
Z84C50
PLCC44
TMPZ84C013
PLCC84
Z84013
PLCC84
Z84C13
PLCC84
TMPZ84C015
ET100-QF06
Z84015
ET100-QF06
Z84C15
ET100-QF06
HD64180R1
PLCC68
HD64180Z HD64180Z
DIL64S PLCC68
Z80180 Z80180
DIL40 PLCC44
Z8S180
PLCC68
Z80182
ET100-QF06
LA-6667
HD648180W
PLCC84
LA-6668
Z80181
ET100-QF06
LA-6691
TMP8085
DIL40
LA-6661 LA-6663
LA-6664
LA-6665 LA-6669
3.0..5.5V
Order Information
Order No.
Code
Text
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
57
Emulation Modules
Order No.
Code
Text
LA-6945 LA-6660 LA-6661 LA-6662 LA-6663 LA-6664 LA-6665 LA-6667 LA-6668 LA-6669 LA-6691
TC-ICE-M-Z80-F ICE-Z80 M-Z80 A-Z84C11 A-Z84C13 A-Z84C15 M-HD64180 M-HD648180 M-Z181 A-Z182 M-8085
TRACE32 Compact ICE/MPC for Z80 family Fast ICE-Z80 Base Module Module Z80 Adapter Z84C11 Adapter Z84C13 Adapter Z80-Z84C15 Module HD64180-DIL/PLCC Module for HD648180-PLCC Module Z181 Adapter Z182 Module 8085
Additional Options ET-1032 ET100-CET-QF06 TO-1260 ET100-ETO-QF06 YA-1031 ET100-EYA-QF06 ET-1030 ET100-SET-QF06 TO-1261 ET100-STO-QF06 LA-7518 MON-Z80 LA-6450 PA64 LA-1921 PLCC-BLOCK-44 LA-1924 PLCC-BLOCK-84 LA-1925 PLCC-TEST-ADAPTER-44 LA-1927 PLCC-TEST-ADAPTER-84
Clip-Over Adapter for ET100-QF06 Emul. Adapter for TO socket ET100-QF06 Emul. Adapter for YAMAICHI socket ET100-QF06 Surface Mountable Adapter for ET100 to QF06 Emul. Adapter TO-surface mount. ET100-QF06 ROM Monitor for Z80 on ESI Port Analyzer PLCC Block 44 Pins PLCC Block 84 Pins PLCC Test Adapter 44 Pins PLCC Test Adapter 84 Pins
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
58
Emulation Modules
Physical Dimensions
Dimension LA-6661
M-Z80 cable (400) 66 37 13 13
26
19 97 100 103 SIDE VIEW
9
8
1
67
1
9 21
TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
59
Physical Dimensions
Dimension LA-6662
A-Z84C11
10 7
102 105 SIDE VIEW
PIN 1
Female Connector
67
9 14 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
60
Physical Dimensions
Dimension LA-6663
A-Z84C13
10 9
26
102 105 SIDE VIEW
1 67
13 35 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
61
Physical Dimensions
Dimension LA-6664
A-Z84C15
10 7
102 105 SIDE VIEW
Female Connector
67
PIN 1 14 20 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
62
Physical Dimensions
Dimension LA-6665
M-HD64180
cable (400) 66 37 13 26
9
64 97 99 103 SIDE VIEW
7
1 66
8 7 18 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
63
Physical Dimensions
Dimension LA-6667
M-HD648180
cable (400) 78 37 13 26
9
112 116 SIDE VIEW
1
67
16 10 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
64
Physical Dimensions
Dimension LA-6668
M-Z181
cable (400) 68 37 13 7
102 106 SIDE VIEW
67
10 15 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
65
Physical Dimensions
Dimension LA-6669
A-Z182
13 7
97 SIDE VIEW
66 PIN 1 21 13 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
66
Physical Dimensions
Dimension LA-6691
M-8085
cable (350) 58 37 13
20 92 99 SIDE VIEW
67
8 2 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
67
Physical Dimensions
Adapter
Socket CPU
Adapter
ET100-QF06
ET-1030 ET100-SET-QF06 Surface Mountable Adapter for ET100 to QF06
TMPZ84C015 Z80181 Z80182 Z84015 Z84C15
32
SIDE VIEW
:: :: :: :: :: :: ::
:::::::::::::: :: :: :::::: :: :: :: :: ::::::
:: :: :: :::::::::::::: 43 52
TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
68
Adapter
Socket CPU
Adapter
ET100-QF06
YA-1031 ET100-EYA-QF06 Emul. Adapter for YAMAICHI socket ET100-QF06
TMPZ84C015 Z80181 Z80182 Z84015 Z84C15
8 6
54 SIDE VIEW
1
56
9
11 TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
69
Adapter
Socket CPU
Adapter
ET100-QF06
ET-1032 ET100-CET-QF06 Clip-Over Adapter for ET100-QF06
TMPZ84C015 Z84015 Z84C15 32
SIDE VIEW
:: :: :: :: :: :: ::
:::::::::::::: :: :: :::::: :: :: :: :: ::::::
:: :: :: :::::::::::::: 52
TOP VIEW (all dimensions in mm)
©1989-2016 Lauterbach GmbH
ICE Emulator for Z80 and Z180
70
Adapter
