High resolution time & frequency counters E. Rubiola FEMTO-ST Institute, CNRS and Université de Franche Comté May 2012
Outline • Introduction • Basic counters (RF & microwave) • The trigger • Clock interpolation techniques • Basic statistics • Advanced statistics
home page http://rubiola.org
start stop
Counter – main purposes
2
Counter
Experiment
Tx (⌧ ) start
stop detector
Frequency, Period or Time-Interval (TI)
TDC
physical events
t = ta input triggers
data
stop
t = tb
data process
detector
start display
⌫c
External frequency reference
• Compare a physical quantity (frequency, period, time interval) to a frequency reference • Exploit the full accuracy and precision of the reference, with no degradation
digital output
Digital hardware The AND gate
3
Basic flip-flops Set-Reset (SR) flip-flop
D-type flip-flop (digital sampler)
4
Binary counter
Disambiguation: the word “counter” – is used for both • the binary / BCD counter – the digital circuit • the time / frequency counter – the instrument
5
6
1 – Basic counters
Time Interval (TI) counter arming pulse
Tx
start
D Q
S Q
Tx
trigger
gate pulse
+ quant. error A B
+ quant. err.
1/⌫c
binary counter
C
T = Tx
R
stop
Nc = ⌫ c Tx
T = Tx
+ quant. error
gate control FF
arming FF
⌫c
gate pulse
clock
t = ta
t = tb
start
t
stop
t
arming pulse
t
gate pulse
1/⌫c t
clock
t
C
Nc clock cycles
The resolution is set by the clock period 1/νc
7
The gate-control FF is not shown
The (old) frequency counter 1/⌫x
⌫x A B
⌫x Nx = ⌫ x T = Nc ⌫c binary counter
C
trigger
⌫c
T = Nc /⌫c ⌧ =T
÷ Nc
clock
A
divider
8
The gate-control FF is not shown
gate pulse
1/⌫x
B
T = Nx /⌫x
C 0/–1 count
Nx = T ⌫x counts
The resolution is set by the input period 1/νx, which can be poor
Classical reciprocal counter Nc = ⌫ c T T = Nx /⌫x
1/⌫c
gate pulse A
⌫x
B
÷ Nx
= Nx ⌫c /⌫x binary counter
C
divider trigger
⌫c clock
gate pulse
T = Nx /⌫x ⌧ =T
Tx = 1/⌫x input
t
nominal gate
t Tw
actual gate A
t T = Nx /⌫x (exact)
clock B
1/⌫c
t t
C
Nc clock cycles
• Use the highest clock frequency permitted by the hardware • The measurement time is a multiple of the input period
9
10
Prescaler Nx = Nx(p) Nx(rc) input
GaAs prescaler
classical reciprocal counter T = Nx /⌫x
1/⌫c
gate pulse A
⌫x
front end
level translat.
÷ Nx(p) divider
Nc = ⌫ c T
B
binary counter
C
÷ Nx(rc) divider
clock
⌫c
= Nx ⌫c /⌫x
gate pulse
T = Nx /⌫x ⌧ =T
frequency reference
• The prescaler is a n-bit binary divider ÷ 2n • GaAs dividers work up to at least 20 GHz • Reciprocal counter => there is no resolution reduction • Most microwave counters use the prescaler
Transfer-oscillator counter transfer oscillator input
⌫x
harmonic mixer front end
⌫x
N ⌫vco
IF amplifier
1 N
⌫vco = ⌫x ⌫ref in
⌫vco
⌫IF
VCO in
control
⌫x
⌫ref
metrix N ⌫vco = ⌫ref
identify N
N
classical reciprocal counter
⇥M frequency reference
⌫c
• The transfer oscillator is a PLL • Harmonics generation takes place inside the mixer • Harmonics locking condition: N νvco = νx • Frequency modulation Δf is used to identify N (a rather complex scheme, ×N => Δν –> NΔν )
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12
Heterodyne counter input
⌫out = ⌫x N ⌫c
heterodyne down-converter
⌫x
sampling mixer
⌫x
front end
N ⌫c
in
N ⌫c harmonic selection
filter control
N
classical reciprocal counter
comb generator
frequency reference
⌫c
• Down-conversion: fb = | νx – N νc | • νb is in the range of a classical counter (100–200 MHz max) • no resolution reduction in the case of a classical frequency counter (no need of reciprocal counter) • Old scheme, nowadays used only in some special cases (frequency metrology)
13
Coarse counting active edge
Tc = 1/⌫c t
clock
GTc gate pulse
G = 1/24
Tx = (N + F )Tc (N = 3, and F = 11/24)
Nc = 3
G = 4/24
Nc = 3
G = 7/24
Nc = 3
G = 10/24
Nc = 3
G = 13/24
Nc = 3
G = 16/24
Nc = 4
G = 19/24
Nc = 4
G = 22/24
Nc = 4
The integer number Nc of clock cycles that falls in the gate pulse Tx is either N or N+1, depending on the the fractional part FTc and on the delay GTc
14
2 – Trigger
15
Trigger hysteresis in
Slope +
vout
out
Slope –
vout
hysteresis
hysteresis
H
H vin
L
vin
L
vout
VT VT H
vin threshold
VT L
hysteresis
vin
hysteresis
VT L VT
VT t t
vout
VT H threshold
VT t t
Hysteresis is necessary to avoid chatter in the presence of noise
Threshold fluctuation ‘stop’
‘start’ start
( V )b x= Sb
systematic
2 x
random
=
(
2 V )a Sa2
( V )a Sa +
(
2 V )b Sb2
S Q
Tx
trigger
R
stop
vin threshold error V
actual threshold nominal threshold
slope S = dv/dt
t error x =
V /S
vout t
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17
noise can cause early triggering only.
18
Trigger noise – oversimplified
Noise can occur on either the Start or Stop pulse or b quently the measurement may be either too long or to twice the error shown in the example.
( V )b systematic x = Sb =
( V )a Sa +
( V2 )b Sb2
a.
1 0 Noise
Volts
random
2 x
( V2 )a Sa2
‘start’
1
b.
0
start
S Q
Tx stop
trigger
1
c.
R 0
Noise
!t
2. Distortion on Input Signal
Time
Agilent, Application Note 200-3, 1997
‘stop’
F E b i
• The effect of noise is often explained with a plot like this Figure 26 shows how harmonically related noise as w • Yet, the formula holds in the absence of spikes!!! nonharmonically related noise moves the trigger poin Also shown is thelooks effect ofsimple noise on a signal. • To the general practitioner, this explanation
Effect of (too) wide-band noise When the rms slope of noise is higher than the signal slope: • the trigger leads • systematic error
E. Rubiola & al., Proc. 46 FCS pp. 265-269, May 1992
19
Trigger behavior vs. bandwidth Noise rms slope Sn2 Sn2
= 4⇡
2
4⇡ = 3
2
Z
B 2
f SV (f ) df 0
= 2.0 Hz, Noise = 10.0 mVrms 1.0 B E. Rubiola, 18 oct 2011
= 64.0 Hz, Noise = 10.0 mVrms 1.0 B E. Rubiola, 18 oct 2011
= 2048.0 Hz, Noise = 10.0 mVrms 1.0 B E. Rubiola, 18 oct 2011
0.5
0.5
0.5
0.0
threshold
0.0 0.5
0.5
1.0
1.0
1.0
time 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.2
time 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.2
B = 1.0 Hz, Noise = 10.0 mVrms E. Rubiola, 18 oct 2011
threshold
0.0
0.1
0.1
0.1
0.49
0.50
0.51
0.52
time 0.53
0.2 0.47 0.2
B = 8.0 Hz, Noise = 10.0 mVrms E. Rubiola, 18 oct 2011
Ss2
4⇡ = 3
2
B2
Signal slope equals rms noise slope
0.50
0.51
0.52
time 0.53
0.2 0.47 0.2
B = 16.0 Hz, Noise = 10.0 mVrms threshold
0.1
0.1
0.1
0.2
0.48
0.49
0.50
0.51
0.2 0.47 0.2
B = 64.0 Hz, Noise = 10.0 mVrms
0.48
0.49
0.50
0.51
time 0.52 0.53
0.2
B = 128.0 Hz, Noise = 10.0 mVrms threshold
0.0
0.1
0.1
0.1
0.2
0.49
0.50
0.51
0.52
time 0.53
0.2 0.47 0.2
B = 512.0 Hz, Noise = 10.0 mVrms E. Rubiola, 18 oct 2011
0.48
0.49
0.50
0.51
0.52
time 0.53
0.2
B = 1024.0 Hz, Noise = 10.0 mVrms threshold
0.0
0.1
0.1
0.1
0.49
0.50
0.51
0.52
time 0.53
0.48
0.49
0.50
0.51
0.52
time 0.53
0.52
time 0.53
B = 2048.0 Hz, Noise = 10.0 mVrms threshold
0.0
0.48
0.51
0.1
0.0
0.2 0.47
0.50
E. Rubiola, 18 oct 2011
0.1 threshold
0.49
B = 256.0 Hz, Noise = 10.0 mVrms
0.2 0.47
E. Rubiola, 18 oct 2011
0.1
0.48
time 0.52 0.53
threshold
0.0
0.48
time 0.53
0.1
0.0
0.2 0.47
0.52
E. Rubiola, 18 oct 2011
0.1 threshold
0.51
B = 32.0 Hz, Noise = 10.0 mVrms
0.2 0.47
E. Rubiola, 18 oct 2011
0.1
0.50
threshold
0.0
time 0.52 0.53
0.49
E. Rubiola, 18 oct 2011
0.0
0.2 0.47
0.48
0.1
0.0
E. Rubiola, 18 oct 2011
2 V
0.49
0.1 threshold
4⇡ = SV B 3 3
0.48
E. Rubiola, 18 oct 2011
0.1
Ss2
threshold
0.0
0.2
2
0.1
0.0
0.48
B = 4.0 Hz, Noise = 10.0 mVrms E. Rubiola, 18 oct 2011
0.1
0.2 0.47
Critical slope
0.2
B = 2.0 Hz, Noise = 10.0 mVrms
threshold
time 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
E. Rubiola, 18 oct 2011
0.1
B2
0.0
0.5
threshold
2 V
threshold
20
0.2 0.47
0.48
0.49
0.50
0.51
0.52
time 0.53
0.2 0.47
0.48
0.49
0.50
0.51
• When the noise slope exceeds the clean-signal slope, the total slope changes sign • There result spikes, and systematic lead error
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3 – Interpolation schemes
Clock interpolation – Main idea Tx t
gate
Tc = 1/⌫c
t
clock
Ta
counted edge
N c Tc
not-counted edge
Tx = Nc Tc + Ta Ta+ = Ta + Tc
Tb
Tb Tb+ = Tb + Tc
Too short Ta and Tb are difficult to measure, so we add one Tc to each
Interpolation is made possible by the fact that
the clock frequency is constant and accurately known
22
The frequency Vernier
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Pierre Vernier, French mathematician Ornans (Besancon), 1580–1637 t
gate
vernier clock
Note that Na = Na0
Tc0 = 1/⌫c0
⌫c0
n = ⌫c n+1
Na0 Tc0 Tc = 1/⌫c
main clock
N a Tc Ta + Na Tc = Na0 Tc0 = Na Tc0
Ta early (0→1) ➔ coincidence
late
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The key elements Synchronized oscillator gate pulse
gate pulse
A
A
t
C
B
t
C
delay
idle
run
Coincidence detector sync clock
coicidence
D Q
vernier clock
t
main clock
t
main clock 1
1
1
1
1
1
0
0
0
0
t
coicidence early
late
Example: Hewlett Packard 5370A
25
26
The Nutt dual-slope interpolator Na0 = Ta0 /Tc0
Ta0
Vx
C
main clock
⌫c
R
I2
I1
integrator
S Q
logic
Ta
enable
comp
BCD counter
⌫c0
reset
gate pulse
+ –
I
aux clock
cnt-Nanofast
gate pulse
t Tc = 1/⌫c
clock
t
Q
t I1 + I2
I
I2
Actual timing gate
t
clock
Ta0 =
((I1 + I2 )/I1 )Ta
Ta+ = Ta + Tc
t t
enable
Tc0 = 1/⌫c0 Ta0 = Na0 Tc0 (+0/ Tc0 )
t
Ta
discharge
ch
Vx
ar
ge
Ta
Ta0+
Vx t
charge smooth start
discharge
Example: Nanofast 536 B Smithsonian Astrophysical Laboratory
27
28
The ramp interpolator ⌫c
S Q
main clock
R
VC
reset
gate pulse
I
S Q
Vx
ADC
I0 sample & hold
C
R
Vˆx
aux clock
integrator gate pulse
t Tc
clock
I0
I
Actual timing
t gate
t
clock
ge
Ta ar ch
VC
t Vx
hold
ar ch
t charge
ge
Ta Vx
Ta+ = Ta + Tc
t
smooth start
hold
Example: Stanford SR 620
29
30
Thermometer-code interpolator Q0
Q2
Q1
Q3
Q4
Q5
Q6
Q7
gate pulse
DQ main clock
DQ
DQ
DQ
DQ
DQ
DQ
DQ
etc.
⌫c ✓
✓
C0
C1
✓
C2
✓
C3
✓
C4
✓
✓
C5
C7
C6
gate pulse
t
C0
clock phases
C1 C2 C3 C4 C5 C6 C7
t 1
0 0
t 1
0
t 1
0
t 0
0
t 0
1
t 0
1
t 0
1
word 0000 0111 indicates delay 5✓
t 0
word 1110 0000 indicates delay 3✓
Also called Multi-tapped delay-line interpolator Review article: J. Kalisz, Metrologia 41 (2004) 17–32
31
Vernier thermometer-code interpolator
gate pulse
main clock
✓1
✓1
✓1
✓1
✓1
DQ
DQ
DQ
DQ
DQ
DQ
etc.
⌫c
✓2
✓2
✓2
✓2
✓2
θeq = θ2 – θ1 Owing to physical size, both θ1 and θ2 are always present
Figure from J. Kalisz, Metrologia 41 (2004) 17–32
Ring Oscillator
32
Also used in PLL circuits for clock-frequency multiplication
SAW delay-line interpolator A – Block diagram
B – Pulse waveforms
• Dispersion stretches the input pulse • Sub-sampling and identification of the alias P. Panek, I. Prochazka, Rev. Sci. Instrum. 78(9):094701, 2007
33
Sigma Time STX301 counter
34
• Gossips report that this is none of the above methods • No information at all, I’m unable to reverse-engineer
35
4 – Basic statistics – after all, not that basic! –
36
Old Hewlett Packard application notes
Quantization uncertainty p(x) 2
1/Tc
=
Tc 1/ 12 = 0.29
Example: 100 MHz clock Tx = 10 ns σ = 2.9 ns
2 Tc
12
37
38
Classical (Π) reciprocal counter x0 x1 x2 x3
phase time x (i.e., time jitter)
xN time t
v(t)
weight
t0 t1 t2 t3 t4 t5 t6 wΠ
tN 1/τ
period T00 0
measurement time τ = NT
the measure is a scalar product
E{ν} =
!
+∞
ν(t)wΠ (t) dt
Π estimator
−∞
" 1/τ 0 < t < τ wΠ (t) = 0 elsewhere ! +∞ wΠ (t) dt = 1
weight normalization
−∞
variance
2 2σ σy2 = 2x τ
classical variance
From Π to Λ – key concept
39
40 36
Enhanced-resolution (Λ) counter x0 x1 x2 x3
phase time x (i.e., time jitter)
xN
v(t)
time t t0 t1 t2 t3 t4 t5 t6
weight
1/τ
0
i=0 i=1 i=2
Λ estimator " +∞ E{ν} = ν(t)wΛ (t) dt −∞
wi wn−1
i = n−1 delay τ0 = DT measurement time τ = NT = nDT
weight
ν i = N/τi
tN−D tN tN+D meas. no.
w0 w1 w2
n−1 1! E{ν} = νi n i=0
wΛ
1 nτ
n−1 1 n−1 nτ τ nτ
2 nτ
2 nτ
weight t/τ wΛ (t) = 2 − t/τ 0
0 νI !
41
Understanding technical data 2 2σ σy2 = 2x τ
classical reciprocal counter enhancedresolution counter low frequency: full speed
classical variance
2 2σ 1 x σy2 = n τ2
classical variance
τ0 = T
n = ν00 τ
=⇒
2 1 2σ x σy2 = ν00 τ 3
high frequency: housekeeping takes time
classical variance
τ0 = DT with D>1 2 1 2σ x σy2 = νI τ 3
=⇒
n = ν00 τ
classical variance
the slope of the classical variance tells the whole story
1/τ 2
=⇒
Π estimator (classical reciprocal)
1/τ 3
=⇒
Λ estimator (enhanced-resolution)
look for formulae and plots in the instruction manual
42
Stanford SRS-620
Examples !
RMS resolution (in Hz)
"
N
gate time
RMS resolution frequency gate time !
RMS resolution
Agilent 53132A
=
# &' ( ' ()2 & )2 $ $ short term × gate trigger 2+ (25 ps) + 2× % stability time jitter frequency
"
=
tres = 225 ps tjitter = 3 ps
#
$
frequency or period
σν = ν00 σy ν00 τ
' & 4× (tres )2 + 2 × (trigger error)2 tjitter √ × + (gate time) × no. of samples gate time %
( (gate time) × (frequency) for f < 200 kHz number of samples = (gate time) × 2×105 for f ≥ 200 kHz RMS resolution frequency period gate time no. of samples
σν = ν00 σy or σT = T00 σy ν00 T00 τ ( ν00 τ ν00 < 200 kHz n= τ × 2×105 ν00 ≥ 200 kHz
43
Linear-regression counter T0
v(t) ✓(t)
Tn
Ti input signal
t r(t) pace
t
picket fence
⌧0
⌧ = n⌧0 measurement time
✓n
✓i ✓0
✓n tn
ˆ= ! ⌫ˆ = t0
ti
✓0 t0 1 ! ˆ 2⇡
tn
t
Linear regression on a sequence of time stamps provides accurate estimation of frequency
44
45
Linear regression vs. Λ estimator y
n = 10, τ = 100 µs n = 100, τ = 1 ms n = 1000, τ = 10 ms std dev of Λ n=1
Parameters trigger noise time stamping
std dev of LR–Λ
0, τ = 100 µs n=1 00, τ =1m s n=1 000, τ= 10 m s
= 1 ns ⌧0 = 10 µs x
Frequency, Hz
The linear regression estimator is asymptotically equivalent to the Λ estimator
46
5 – Advanced statistics
Decimation of Λ estimates How to combine contiguous Λ measures in a way that makes sense (B) optimally overlapped, the average converges to a Π estimate
(A) optimally overlapped, recursive decimation
⌧B
⌧B
time series
t
2⌧B
(C) separated measures, multi-triangle average
2⌧B
time series
t
2⌧B
t
⌧ = ⌧B
t
2⌧B
w(1)
w(1)
time series
w(1)
t
⌧ = ⌧B
t
2⌧B
2/4 1/4
1/4
1/2
w
1/2
t
(2)
t ⌧ = 2⌧B
1/2
w
(2)
1/2
t
t
4⌧B
t
w
t
⌧ = 2⌧B
(2)
4/16 1/16
2/16
3/16
3/16
2/16
w ⌧ = 4⌧B
(4)
1/4
1/16
t t
1/4
1/4
w(4) ⌧ = 4⌧B
1/4
1/4
t t
1/4
1/4
1/4
t t
w(4) 8⌧B
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48
Allan variance ! " $ # 2 1 2 σy (τ ) = E y k+1 − y k 2
definition
% ! " # $ # 2 (k+2)τ (k+1)τ 1 1 1 σy2 (τ ) = E y(t) dt − y(t) dt 2 τ (k+1)τ τ kτ
wavelet-like variance
σy2 (τ ) = E
! "#
y(t) wA (t) dt
−∞
wA =
1 − √2τ √1 2τ
energy
+∞
E{wA } =
0
!
0