High Frequency Characterization of Transistors J. Prasad
[email protected]
J. Prasad
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Process Engineer
VP Engineering
This process change should have improved Ft and Fmax !
I didn’t see any change. Actually Fmax was lower!
VP Technology
J. Prasad
Microwave Test Engineer
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1.1THz Test System from Cascade Microtech/Keysight
International Microwave Symposium, San Francisco, May 22-27, 2016 J. Prasad
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What is High Frequency Characterization?
Large Signal Characterization
Small Signal Characterization
This talk
Pin vs Pout PAE P1dB OIP3 IIP3 Load Pull Source Pull
fT fmax NFmin Rn Zs opt GA Re Rb Rs Rd
Non-Linear Measurements
Linear Measurements
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OUTLINE • • • • • • • • • • • • •
J. Prasad
Introduction S-parameters Smith Chart Vector Network Analyzer Calibration De-embedding Examples of measured data Gain and Stability Ft and Fmax from S-parameters Mason’s Gain Transistor Specmanship Parameter extraction/wafer maps Conclusion
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BIPOLAR FIGURES OF MERIT Approximate
gm fT 2 C C W2 C C jE g m 2 Dn
Exact
N AB WEW W 2 W WDC reC jE re ree rc C jC 2 fT N DE 2 Dn 2 Dn vm 2vsat ---------------- ------------ -----1
e
b
thermionic emission velocity
C C jC
f max
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fT 8 rbb 'C
c kT 5 106 cm/sec for Si. 2 m * saturation velocity vm
vsat 107 cm/sec for Si.
f max
fT 8 rbb 'C
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Ft VARIATION WITH FREQUENCY (Bipolar)
h21( BJT )
1 j
Microwave Engineers find Ft by plotting h21 vs frequency!
f fT
DC 100 fT 50 GHz
20log(h21)
h21 BJT angle
h21 (BJT) 0
50
-10 -20
h21 BJT angle (deg)
h21 BJT (dB)
40
30
20dB/dec 20
-30 -40 -50 -60 -70
10
-80
0 0.01
0.1
1 Freq (GHz)
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10
50
100
-90 0.01
0.1
1
10
100
Freq (GHz)
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MOS FIGURES OF MERIT Exact
Approximate
fT
gm 2 Cgs Cgb Cgd
fT
gm 2 Cgs
fT
gm R RS 2 (Cgs Cgd ) 1 D ro
C g ( R R ) C gd m D S p C p : parasitic cap
Cgd & Cgb are small in sat
f max
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fT 8 RG Cgd
f max
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fT 2 g ds ( RG RS ) 2 fT RG Cgd
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Ft VARIATION WITH FREQUENCY (MOS)
1 f j fT
h21( MOS ) Note that this goes to infinity!
fT 50 GHz
Phase is constant
h21 MOS
h21 MOS angle
80
0
70 -20
50
H21 MOS angle
h21 MOS (dB)
60
40 30
-40
-60
20 -80
10 0 0.01
-90 0.1
1
10
-100 0.01
100
Freq (GHz)
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0.1
1
10
100
Freq (GHz)
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S- PARAMETERS
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Why S-Parameters?
• • • • • • • • • •
At HF, difficult to measure currents and voltages Difficult to create open and shorts Everything behaves like Transmission lines with reflections S-parameters are very easy to understand and use S-parameters exist for any network Can easily relate to gain, loss, reflection and power Can predict the performance of cascaded networks From S-parameters, one can convert to Z, Y or H parameters Needed for SPICE model parameter extraction Some CAD programs need S-parameters for circuit design
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Two Port Parameters 1 + V1 _
I2
I1 Device
2 + _ V2
V1 h11 I1 h12V2
V1 z11 I1 z12 I 2
I 2 h21 I1 h22V2
V2 z21 I1 z22 I 2
I1 g11V1 g12 I 2 V2 g 21V1 g 22 I 2
I1 y11V1 y12V2 I 2 y21V1 y22V2
V1 AV2 BI 2 I1 CV2 DI 2
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S-Parameters Defined 2
1 a1
Device
b2
b1
S11 S 21 S12 S 22 J. Prasad
b1 a1 b2 a1 b1 a2 b2 a2
b1 S11a1 S12 a2
a2
b2 S21a1 S22 a2
Input reflection coefficient with output terminated in Zo a2 0
Forward transmission coefficient with output terminated in Zo a2 0
Reverse transmission coefficient with input terminated in Zo a1 0
Output reflection coefficient with input terminated in Zo a1 0
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S-Parameters in terms of impedances and voltages Z1 ZO + VS
_
Z2 2
1 + Device
V1 _
+ V2 _
ZO
ZO : Characteristic impedance (50W)
Z1 Z 0 S11 Z1 Z 0 Z2 Z0 S 22 Z2 Z0
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S 21
2V2 VS
S12
2V1 VS SPara
G.Gonzalez, Microwave Transistor Amplifiers, Prentice Hall 1984 14
S-Parameters for a 6dB pad Z1 ZO + VS
S11
_
Z2 2
1 + V1 _
+ 6dB Pad
Z1 Z 0 Z1 Z 0
Z Z0 S 22 2 Z2 Z0
0
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0.5
S=
2V2 S 21 VS S12
ZO
V2 _
0.5
0
2V1 VS SPara
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Z-Parameters for a 6dB pad Z1 ZO + VS
50
1
16.6
Z2 2
+ V1 _
_
16.6
+ V2 _
66.9
ZO 50
6 dB pad
83.5
0
66.9
Z=
0.5
S= 66.9
0.5
83.5
0
Looking at Z - parameters one can not quickly infer this is a 6dB Pad!
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SIGNAL FLOW GRAPHS
a1 S21
S11
a1 S21
b2
S11 b1 S12
a2
b1 S11a1 S12 a2 b2 S21a1 S22 a2
b2
S22
S22
S22 b1 S12
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a1 S21
b2
L a2
S
S11 b1 S12
a2
in
S S in S11 12 21 L 1 S22 L
SPara
out S22
out
S12 S21 S 1 S11 S
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INTRODUCTION TO SMITH CHART
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Smith Chart Story
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Mapping of resistances – Smith Chart-1 L
Z L Z0 Z L Z0
S
Z S Z0 Z S Z0
𝑗∞
∞
0
Convert all impedances to reflection coefficient and plot it. That is Smith Chart! ZO = 50W
−𝑗∞
0
-1 0
25
50W
+1 100
200
oo
Pure resistances map along the x-axis between -1 and + 1 J. Prasad
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Mapping of reactances – Smith Chart-2 y
Z Z0 L L Z L Z0 S
Radius=1
j50
ZO = 50W
Z S Z0 Z S Z0
j100
j25
Inductive
j200 j10
Z L (W)
L
0
1180o
0
1157.4
o
j25
1126.9
o
j50
1 90o
j100
1 53.1
j200
1 28.1
j10
j J. Prasad
oo
50
x
-j10
-j200
Capacitive -j100
-j25 o
-j50
o
10
o
Note that magnitude is always 1 but angle varies. Pure reactance maps along the circumference of a unit circle. SPara
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Mapping of impedances – Smith Chart-3 Z Z0 L L Z L Z0 S
ZO = 50W
Z S Z0 Z S Z0
Z L (W)
y
Unit circle: Radius=1
j50
X=const circle 50+j50
L
Inductive o
50+j50
0.45 63.4
50 j 50
0.45 -63.4
0.45
50 o
63.4o
oo x
0 Capacitive
-j50
R=const circle
All impedances (R+jX) with R>0 will map inside a unit circle. If R is negative (R< 0), it will map outside the unit circle.
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The Glorious Smith Chart
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How to measure S-parameters? - The Vector Network Analyzer
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E 8361C PNA Series NETWORK ANALYZER 10MHz – 67GHz
You will also need a 4155 Semiconductor Parameter Analyzer for biasing.
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VECTOR NETWORK ANALYZER BLOCK DIAGRAM
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What is Calibration?
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CALIBRATION
Short the leads and adjust the ZERO OHMS pot so that the meter reads zero. We have zeroed out resistance of the test leads.
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CALIBRATION
Short the leads and write down the reading R1. Connect the resistor Rx and take the reading R2. Unknown resistor Rx = R2 – R1
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I-V curves
4155/4156 Parameter Analyzer
Measure & gen I-V curves
Measure 0.1W resistor
Multimeter
Calibrate
Output file
Measure
Output data
Measure
Output data
1 term error correction: short
Capacitance Measurement
Capacitance Meter 4980
Calibrate
2 term error correction: short and open
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4980A CAPACITANCE METER (20Hz – 2MHz)
CALIBRATION Short the leads and write down the series resistance Rs. Open the leads and write down the stray capacitance Cp. The instrument does the correction for the series resistance. Then it subtracts the stray capacitance from the measured data.
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One-Port Measurement using Network Analyzer
1-port S-parameter
8361C Network Analyzer
Calibrate
Measure
S-parameter data
3 term error correction: short, open and load
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One-Port Error Correction
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One / Two-Port Measurement using Network Analyzer
1-port S-parameter
8361C Network Analyzer
Calibrate
Measure
S-parameter data
3 term error correction: short, open and load
2-port [S] package
8361C Network Analyzer
Calibrate
Measure
S-parameter data
12 term error correction: short , open, load and thru
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TWO PORT CALIBRATION
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THRU CALIBRATION FOR GROUP DELAY
f Phase (rad) w
RFin
S
S
G
D
RFout
f w 1 360o f
Group delay t g
delayed signal S
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S
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TRL CALIBRATION At low frequencies, the lines become long. So, we need different TRL structures for different frequency bands for wide band characterization. Use SOLT for lower freq.
THRU
REFLECT
LINE
Glenn Engen, Cletus Hoer, MTT-27 (12), Dec 1979 J. Prasad
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RF MICROWAVE PROBES (CASCADE MICROTECH)
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CALIBRATION USING IMPEDANCE STANDARD SUBSTRATES
The purpose of Cal is to bring the reference plane to the probe tips
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BEFORE CALIBRATION
AFTER CALIBRATION
j50
j50
oo
50 0
0
-j50
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oo
50
-j50
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DE- EMBEDDING
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1-port S-parameter
8361C Network Analyzer
Measure
Calibrate
S-parameter data
3 term error correction: short, open and load
2-port [S] Package
8361C Network Analyzer
Measure
Calibrate
S-parameter data
12 term error correction: short , open, load and thru
On-wafer 2-port [S]
8361C Network Analyzer
Calibrate
Measure
De-embed
[S] data of device
12 term error correction: short , open, load and thru
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S
S
S
S
G
D
Cpad 100-600 fF G
D
Cdevice
100 devices
1- 6 fF S
S
S
S A device array alleviates this problem to some extent
Pad capacitance far exceeds Single device capacitance Device
Y3
G
DUT
Y2
Y1
S
S J. Prasad
D
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1-Step De-Embedding
G
Device
OPEN
Y3
Y3
DUT
Y1 S
S open y open S device y device y DUT y device y open y DUT S DUT J. Prasad
G
D Y2
D Y2
Y1
S
S
S
Measure on- wafer OPEN Measure DEVICE Use the equations on the left
DE- EMBEDS PAD CAPACITANCE ONLY !
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2- Step De - Embedding
Device S
S
G
D
Y3
G
S
Z2
Z1 Y1
D
DUT
Z3
S
S
S
Y2
DE- EMBEDS • Pad Capacitance • Series Impedance
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2- Step De - Embedding
G
Device
OPEN
Y3
Y3 D
DUT
Z1 Y1
S
S THRU
Y3
Y3 G
D
D Z2
Z1
Z2 Z3
Y2
Z3
SHORT
Z1
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Z2
Y1
S
G
S
D Z1
Y2
Z3
S
Y1
G
Z2
Y1
Y2
S
S
SPara
Z3
Y2 S
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Device
2- Step De - Embedding
Y3
G
S open y open Y S S short z short S device y device y dev _ no _ pad y device y open y dev _ no _ pad z dev _ no _ pad z DUT z dev _ no _ pad z short z DUT S DUT Whoa!
1
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D
DUT
Z2
Z1 Z3
Y2 S
DUT with Pad capacitance and series elements
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High Frequency Performance of 0.18um CMOS
Ft=50GHz, Fmax=45GHz
Measurement: 0.5-50GHz
RF Characteristics of 0.18-m CMOS Transistors: Kwangseok Han, Jeong-hu Han, Minkyu Je and Hyungcheol Shin Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Taejon 305-701 J. Prasad
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IMPERFECT on-wafer SHORT
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Layout with minimum inductance and reflections
E
E
B
C
E
E Small octagonal pads to reduce capacitance and reflections
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Definitions of Gain and Stability
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DEFINITIONS OF GAIN
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Ft and Fmax of 65nm CMOS
Limiting Factors of RF Performance Improvement as Down-scaling to 65-nm Node MOSFETs H. L. Kaoa*, B. S. Lina, C. C. Liaob, M. H. Chenc, C. H. Wuc, and Albert Chinb a Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, Taiwan, ROC b Nano-Sci. Tech. Ctr, EE. Dept., Nat’l Chiao-Tung Univ., UST, Hsinchu, Taiwan, ROC c Dept. of MicroElectronics Engineering, Chung Hua Univ., Hsinchu, Taiwan, ROC
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CIRCUIT FOR MEASURING MAXIMUM AVAILABLE GAIN & Fmax
in ZS + VS
_
out 2
1 + V1 _
Device
+ V 2_
ZL
We vary ZS and ZL so as to provide a simultaneous conjugate match. This maximizes the input power and delivers maximum output power to the load. This will give us MAG. If we do this at each frequency, we can generate a plot of MAG vs frequency. From this plot, we can determine the frequency at which the power gain will become unity. This is Fmax.
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THE EFFECT OF LOAD IMPEDANCE IN = 1 circle
S11 0.65 95
j50
S12 0.0440 S 21 5.00115 unstable
S 22 0.80 35
in S11
S12 S21 L 1 S22 L
53o 0 50
-j50 J. Prasad
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THE EFFECT OF SOURCE IMPEDANCE j50
S11 0.65 95 S12 0.0440 S 21 5.00115
OUT = 1 circle
S 22 0.80 35
out S22
S12 S21 S 1 S11 S
unstable
127o 0 50
-j50 J. Prasad
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OUTPUT STABILITY CIRCLE & UNCONDITIONAL STABILITY
j50
conditionally stable
j50
unconditionally stable
IN >1
IN >1
unstable
0
50
-j50
0
K1 MAG defined Simultaneous conjugate match possible
For unconditional stability 𝐾 > 1 𝑎𝑛𝑑 ∆ < 1
J.M.Rolett, IRE Trans CT, CT-9(1), pp 29-32, Mar 1962, J. Prasad
W.Ku, Proc IEEE 54(11), pp 1617-1618, Nov 1966
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GAIN EQUATIONS in S- Domain
Maximum Available Gain
Use only for K>1
Maximum Stable Gain
Use only for K1 over some frequency range [S]DUT over frequency [S]DUT over frequency No
K > 1 and D 1 and D