LARS PETERSEN

High Efficient Rectifiers

PhD the si s

AUTOMATION

Ørsted • DTU

AUGUST 2003

High Efficient Rectifiers

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High Efficient Rectifiers

Ph.D. Thesis Lars Petersen Ørsted•DTU, Automation Technical University of Denmark DK-2800 Kongens Lyngby August 2003

High Efficient Rectifiers

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Preface This thesis is submitted to the Technical University of Denmark in partial fulfillment of the requirements for the Doctor of Philosophy degree (Ph.D degree). The research has been carried out at the Department of Applied Electronics, Department of Electric Power Engineering and Oersted•DTU, Automation, during the period February 1st 2000 to August 9th 2003. Within this period I was on leave for 3 months. The work done in this thesis is part of the project "Energy-Saving Rectifier" which is a corporation between:






Technical University of Denmark APW power supplies A/S B&O A/S B&O ICEpower Powerlab A/S.

The project is sponsored by the Danish Energy Authority through the EFP2000 program, J.nr. 1273/00-0013. First of all I would like to thank my advisor Professor Michael A.E. Andersen for the sharing of knowledge and the support I have received during my project. All of the participating companies are thanked for their input to the project. We have had many interesting discussions both during and after work-hours. A special thanks goes to Ole S. Seiersen for his numerous inputs to the project and his way of putting things into perspective. This has helped me in keeping the "Ground-connection". Also, I would like to thank Professor Robert W. Erickson at the University of Colorado at Boulder for letting me visit his department during the spring of 2002, where I was treated as an equal member of the power electronics group. I would like to thank my good friend Peter Have for proof-reading the manuscript. Finally, I would like to express my deepest gratitude to my dear family, Robert and Lone, for their endless support and belief in me. Without them I would not have succeeded.

Kongens Lyngby, August 2003.

Lars Petersen

High Efficient Rectifiers

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Abstract In all electronic equipment the power supply plays an important role even though the power supply typically has nothing to do with the primary function of the equipment. From the manufacturers point of view, the power supply is a necessity but since it has nothing to do with the primary function of the equipment, little focus is directed towards this unit. As a result of the introduction of the new European norm EN61000-3-2, focus has been directed towards the implementation of the off-line power supplies. This norm limits the low frequency harmonic current content in the line current. The most commonly used ac/dc power supply configuration (bridge-rectifier + filter capacitor) is affected by the new norm, forcing the manufacturers to pay attention to the way that the ac/dc conversion is performed. Solutions like the PFC boost converter in a Two-Stage configuration that complies with the regulations have been known long time before the implementation of EN61000-3-2, but since the regulations accommodate some distortion of the line current, many new PFC approaches that take advantage of this have been proposed during the last decade. Two of the dominating PFC approaches are referred to as the Single-Stage approach and the Reduced Power Processing approach. This thesis is a fundamental study of the performance of these dominating PFC approaches consisting of the Single-Stage approach, the Reduced Power Processing approach and the Two-Stage approach. All of the PFC approaches basically consists of a reconfiguration of the basic dc/dc converter topologies and by characterizing the stress on these individual converters it is shown that the well known, well proven Two-Stage approach is the superior approach with regard to the component stress and thereby the conversion efficiency. As a result of this work with characterizing and comparing the different PFC approaches, a new family of PFC converters have emerged. This new type of converters is especially suited for wide input range applications since one of the strong sides of this converter is an effective reduction of the input range with a factor of 2. The new converter type has been named: Efficient Wide Range Converter - EWiRaC Experimental results confirms the theoretical prediction of the EWiRaC being a high efficient PFC converter for wide range applications and compared to the wide range PFC boost converter, the EWiRaC achieves 1-2 percentage points higher worst case efficiency.

High Efficient Rectifiers

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Resumé (Abstract in Danish) I alt elektronisk udstyr spiller spændingsforsyningen en vigtig rolle, selvom den sjældent har noget med apparatets primære funktion at gøre. Set fra producenters synspunkt, er spændingsforsyningen en nødvendighed, men da den ikke har noget at gøre med apparatets primære funktion, fokuseres der meget lidt på denne enhed. Introduktionen af EN61000-3-2 har medført at der nu skal fokuseres på spændingsforsyningen hvis denne er tilsluttet lysnettet. Denne nye norm sætter grænser for indholdet at harmoniske strømme i lysnettet. Den mest udbredte ac/dc spændingsforsyning (bro-ensretter + udglatningskondensator) rammes af de nye normer. Producenterne tvinges derved til at fokusere på den måde, at ac/dc konverteringen udføres. Løsninger, som en PFC boost konverter i en Two-Stage løsning, der overholder de nye normer, har været velkendte lang tid før at EN61000-3-2 blev introduceret, men da EN61000-3-2 tillader en del harmoniske i strømmen, er der fremkommet mange nye løsninger i det sidste årti, der udnytter dette. To af de dominerende PFC løsninger refereres til som en Single-Stage løsning og en Reduced Power Processing løsning. Denne afhandling er et grundigt studie i virkemåden af disse dominerende PFC løsninger benævnt som Single-Stage, Reduced Power Processing og Two-Stage løsninger. Alle disse PFC løsninger er grundlæggende sat sammen af de basale dc/dc konverter topologier og ved at karakterisere stresset på de individuelle konvertere, er det vist, at løsningen kaldet Two-Stage er overlegen mht. til komponent stress og derved også mht. konverteringseffektiviteten. Som et resultat af arbejdet med at karakterisere de forskellige løsninger, er der fremkommet en ny familie af PFC konvertere. Denne nye konverter-type egner sig specielt til applikationer, hvor indgangsspændingen varierer relativt meget, da en af konverterens forcer er, at den effektivt kan halvere variationen på indgangsspændingen. Denne nye konverter-type er blevet kaldt: Efficient Wide Range Converters – EWiRaC De eksperimentelle resultater underbygger de teoretiske forudsigelser om, at EWiRaCkonverteren er en høj effektiv PFC konverter til det universelle spændingsområde. Sammenlignet med en PFC boost konverter til det universelle spændingsområde, opnår EWiRaC-konverteren en forøgelse på 1-2 procent-point i worst-case effektiviteten.

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Table of Contents

List of figures...............................................................................................15 List of tables................................................................................................19 List of abbreviations....................................................................................21 1. Introduction.............................................................................................23 2. Standard PFC and EN61000-3-2............................................................25 2.1 Definition of Power Factor (PF)..............................................................................25 2.2 General PF considerations.......................................................................................26 2.3 EN61000-3-2..........................................................................................................28 2.4 Complying with EN61000-3-2................................................................................30

3. State of the art approaches in Single-Phase PFC...................................31 3.1 Characterizing the different approaches...................................................................31 3.2 A Database of published PFC topologies and approaches........................................32 3.2.1 Database structure...........................................................................................32 3.2.2 The reference Data-table.................................................................................32 3.2.3 Database inputs and search structures..............................................................33 3.3 Overall PFC approaches..........................................................................................35 3.3.1 Two-stage solutions........................................................................................36 3.3.1.1 Definition of a two-stage system..............................................................36 3.3.1.2 Two-stage configurations........................................................................36 3.3.1.3 Non-isolated PFC – isolated dc/dc...........................................................36 3.3.1.4 Isolated PFC – non-isolated dc/dc............................................................37 3.3.2 Reduced power processing systems.................................................................38 3.3.2.1 Definition of a reduced power processing system.....................................38 3.3.2.2 Introduction to reduced power processing...............................................38 3.3.2.3 Reduced power processing with dc-side auxiliary converter.....................39 3.3.2.4 Characteristics of the Reduced Power Processing systems.......................42 3.3.3 Single stage systems........................................................................................42 3.3.3.1 Definition of a single-stage system...........................................................42 3.3.3.2 Introduction to Single-stage systems........................................................43 3.3.3.3 The switch-sharing single-stage systems...................................................43 3.3.3.4 The magnetic-switch single-stage systems................................................45 3.3.3.5 Characteristics of the Single-stage systems...............................................47 3.4 Summary................................................................................................................48

4. Problem statement...................................................................................49 4.1 The research problem within the state-of-the-art approaches...................................49 4.1.1 Structural considerations of the state-of-the-art approaches.............................50

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4.1.2 Defining the research problem.........................................................................51 4.2 The approach of the future......................................................................................53 4.2.1 Efficiency driven research................................................................................53 4.2.2 Improving the efficiency..................................................................................53 4.2.3 The converter "wish list".................................................................................54 4.3 Summary................................................................................................................55

5. Converter component stress....................................................................57 5.1 Introduction to Component Load Factors...............................................................57 5.2 Using CLF on the basic topologies..........................................................................59 5.2.1 Basic non-isolated topologies..........................................................................59 5.2.2 Basic isolated topologies.................................................................................65 5.2.3 Example: Comparing single-ended isolated converters.....................................66 5.2.4 Summarized CLF calculations.........................................................................67 5.3 Properties of static and dynamic up/down conversion.............................................68 5.3.1 Static up/down conversion..............................................................................68 5.3.2 Dynamic up/down conversion..........................................................................70 5.3.3 Key points.......................................................................................................72 5.4 Using CLF on the basic power conversion systems.................................................72 5.4.1 Single-stage vs. two-stage, a simple comparison..............................................73 5.4.2 Key observations.............................................................................................74 5.5 The relation between dc- and ac-CLF.....................................................................74 5.5.1 Ac-CLF...........................................................................................................74 5.5.2. The impact of ac voltage variations compared to dc voltage variations ..........75 5.6 The pitfalls of CLF..................................................................................................77 5.7 Summary................................................................................................................78

6. Comparing the state-of-the-art approaches ..........................................79 6.1 Typical loss distribution in a universal input PFC boost converter...........................79 6.2 Discussion of the comparisons conducted...............................................................80 6.3 Applied CLF and alternative Stress measures..........................................................81 6.4 Comparisons...........................................................................................................84 6.4.1 Reduced power processing vs. Two-stage solutions........................................84 6.4.1.1 Auxiliary converter considerations...........................................................84 6.4.1.2 Main converter considerations.................................................................85 6.4.1.3 Non-sinusoidal reduced power processing...............................................88 6.4.1.4 Summary.................................................................................................90 6.4.2 Single-stage vs. Two-stage solutions...............................................................91 6.4.2.1 Key properties of the single-stage operation.............................................91 6.4.2.2 Comparisons............................................................................................93 6.4.2.3 Summary.................................................................................................96 6.5 Summary................................................................................................................97

7. Non-isolated PFC converters .................................................................99 7.1 The Boost PFC converter.......................................................................................99 7.2 Alternatives to the PFC Boost converter ..............................................................101 7.2.1 Buck-boost derived PFC converters..............................................................101 -12-

7.2.2 Switchable topologies....................................................................................102 7.2.3 Summary.......................................................................................................103 7.3 The characteristics of high performance converters...............................................104

8. A new family of Efficient Wide Range Converters..............................105 8.1 The series voltage-source approach......................................................................106 8.1.1 Requirements of the switchable topology.......................................................106 8.1.2 Voltage-source requirements.........................................................................107 8.1.3 Current-source requirements.........................................................................109 8.1.4 Fundamental implementations of the voltage-source......................................109 8.2 Transformer-based EWiRaC solutions.................................................................111 8.2.1 Standard transformer-based EWiRaC converters...........................................111 8.2.2 Alternative transformer-based EWiRaC converters........................................112 8.2.3 Active rectifier, transformer-based EWiRaC converters.................................113 8.3 Analysis of the EWiRaC operation-modes.............................................................114 8.3.1 Steady-state EWiRaC operation modes........................................................114 8.3.2 Transient EWiRaC operation........................................................................118 8.4 Comparisons.........................................................................................................119 8.4.1 Active switches.............................................................................................119 8.4.2 Diodes...........................................................................................................121 8.4.3 Inductors.......................................................................................................121 8.4.4 Output capacitor...........................................................................................123 8.4.5 EMI-filter......................................................................................................124 8.4.6 Inrush current limiting...................................................................................126 8.4.7 Output voltage considerations.......................................................................126 8.4.8 Summary.......................................................................................................126 8.5 Controlling the EWiRaC.......................................................................................127 8.5.1 Overall control considerations.......................................................................128 8.5.2 Peak current mode PFC control.....................................................................129 8.5.2.1 Standard peak current mode control......................................................129 8.5.2.2 Advanced peak current mode control.....................................................130 8.5.3 Average current mode PFC control with level shifted carrier.........................131 8.5.4 Generating the voltage-source PWM-pattern.................................................133 8.6 Alternative EWiRaC converters............................................................................133 8.6.1 The transformer-less EWiRaC.......................................................................134 8.6.2 The adopted voltage-source operation mode.................................................134 8.6.3 Modified SEPIC ...........................................................................................135 8.7 Summary..............................................................................................................136

9. Experimental results.............................................................................137 9.1 Prototype specifications........................................................................................137 9.2 Estimated worst case efficiency of the EWiRaC converter...................................138 9.3 Prototype 1: Peak current mode control................................................................138 9.4 Prototype 2: Average current mode control with level shifted carrier....................142 9.4.1 Design considerations....................................................................................142 9.4.2 Performance of the practical implementation.................................................144 9.5 Summary..............................................................................................................151

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10. Conclusion............................................................................................153 References (thesis).....................................................................................157 References (database)...............................................................................161 Appendix A ...............................................................................................175 Appendix A1..............................................................................................................177 Appendix A2..............................................................................................................187 Appendix A3..............................................................................................................195 Appendix A4..............................................................................................................205

Appendix B................................................................................................215 Appendix C................................................................................................221 Appendix C1...............................................................................................................223 Appendix C2...............................................................................................................227

Appendix D................................................................................................233 Appendix E................................................................................................239 CD-ROM:..................................................................................................................239 The data-base (Microsoft Access) PDF-version of all the references in the data-base Thesis in PDF format

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List of figures Fig. 2.1. Ac/dc conversion using peak rectification....................................................................................27 Fig. 2.2. Measurements on a bridge-rectifier + filter capacitor. VAC = 230V, POUT=330W, CB=660µF (2µF/W). a) Voltage- and current waveform. b) Harmonic content...........................................28 Fig. 2.3. The special Class D wave shape. Each half cycle of input current is within the envelope at least 95% of the time. Current peak should coincide with center line.....................................................30 Fig. 3.1. The database structure. The "Author table" and the "Data table" are linked together through a "one to many" relation using the "Author-Data link table".........................................................32 Fig. 3.2. The interface to the "Data table". This form can be used for both input to the table and as a screen read-out...................................................................................................................................33 Fig. 3.3. Block schematic of the search structure applied in order to derive an overall grouping of the PFC approaches...............................................................................................................................34 Fig. 3.4. a) Two-stage configuration with non-isolated PFC-stage. b) Two-Stage configuration with isolated PFC-stage.............................................................................................................................36 Fig. 3.5. Reduced Power Processing schemes. a) Auxiliary converter on the ac-side of the isolation. b) Isolated auxiliary converter. c) Auxiliary converter on the dc-side of the isolation..................................38 Fig. 3.6. Power flow for the Reduced Power Processing schemes of Fig. 3.5c. ...........................................39 Fig. 3.7. Power flow normalized to the output power for a the basic Reduced Power Processing system (Fig. 3.5) having sinusoidal input current. The power-flow is according to Fig. 3.6........................40 Fig. 3.8. Reduced Power Processing schemes with DC-side auxiliary converter and 68% direct power transfer. a) Isolated PFC converter with means to control the power-flow. b) Bidirectional auxiliary converter............................................................................................................41 Fig. 3.9. Isolated PFC converter with 50% direct power transfer. a) Indirect auxiliary converter. b) Direct auxiliary converter, two separate transformers in the isolated PFC converter...............................41 Fig. 3.10. Integration of two separate converters into a Single-Stage version [db107].................................43 Fig. 3.11. a) Single-Stage boost-forward. b) DC-bus voltage as a function of the boost-forward inductor ratio [10].....................................................................................................................................44 Fig. 3.12. Current-flow in the Single-Stage converter shown in Fig. 3.11a. ...............................................45 Fig. 3.13. a) A magnetic-switch converter facilitating CCM operation of the output inductor [db125]. The de-magnetizing winding on the transformer is not shown. b) Characteristic input current waveform. ................................................................................................46 Fig. 3.14. A magnetic-switch converter facilitating CCM operation of the output inductor [db162]. The de-magnetizing winding on the transformer is not shown........................................47 Fig. 4.1. The power supply system – architectural layout............................................................................50 Fig. 4.2. Different architectural layouts of a power supply system. a)-c) Decentralized power systems. d) centralized power system...............................................................................................50 Fig. 4.3. Level of complexity for possible research questions. ...................................................................52 Fig. 4.4 The target of the efficiency improvement – increasing the worst case efficiency. ..........................54 Fig. 5.1. The 3 basic dc/dc converters. a) Buck dc/dc converter. b) Boost dc/dc converter. c) Buck-boost dc/dc converter....................................................................................................................60 Fig. 5.2. Converters processing the same input power from the same source-voltage and

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High Efficient Rectifiers with the same switch duty-cycle (d=0.5). a) Boost. b) Buck-boost...............................................................60 Fig. 5.3. Transistor CLF calculated with peak voltages and rms-currents...................................................62 Fig. 5.4. Transistor CLF calculated with peak voltages and peak currents..................................................63 Fig. 5.5. Diode CLF calculated with peak voltages and average currents....................................................64 Fig. 5.6. Inductor CLF calculated with average applied voltages and rms-currents.....................................64 Fig. 5.7. Capacitor CLF calculated with dc voltages and rms-currents........................................................65 Fig. 5.8. Transistor (diode) CLF calculated with peak voltages and peak currents......................................65 Fig. 5.9. Transistor CLF calculated with peak voltages and rms-currents...................................................66 Fig. 5.10. Single-ended isolated converters with switch duty-cycle d = 0.5. a) Flyback (isolated buck-boost derived). b) SEPIC (isolated buck-boost derived). c) Forward (isolated buck derived).............................................................................................................66 Fig. 5.11. Power supply system with static conversion ratio.......................................................................68 Fig. 5.12. Power supply system with dynamic conversion ratio...................................................................70 Fig. 5.13. Simple power system configurations. a) Single-Stage system. b) Two-Stage system....................73 Fig. 5.14. MOSFET CLF calculated with peak voltages and peak currents averaged over one half line period....................................................................................................................................75 Fig. 5.15. MOSFET CLF calculated with peak voltages and rms-currents averaged over one half line period....................................................................................................................................75 Fig. 6.1. Typical distribution of power losses in a PFC boost converter [17]...............................................80 Fig. 6.2. Two different realizations of a 4:1 step-up system. a) Two cascaded boost converters. b) A single-switch version of the converter in a)........................................................................................82 Fig. 6.3. Flyback PFC converter with post-regulator. a) Reduced Power Processing scheme [21]. b) Buck post-regulator...............................................................................................................................84 Fig. 6.4. Comparison of an isolated PFC and a Two-Stage solution. a) Isolated flyback PFC. b) Two-Stage solution with a boost PFC and an isolated buck-derived dc/dc converter...............................86 Fig. 6.5. Isolated PFC boost ......................................................................................................................87 Fig. 6.6. a) Flyback input current shaper with Reduced Power Processing [22]. b) Buck input current shaper......................................................................................................................88 Fig. 6.7. Magnetic-switch Single-Stage system. Viewing the Single-Stage system as a Two-Stage system with a variable dc-bus voltage.......................................................................................91 Fig. 6.8. Two-Stage power supply system. .................................................................................................92 Fig. 6.9. Magnetic-switch Single-Stage system. a) Modeled as a series connection of a voltage-source (VS) and a loss free resistor (RLF). b) Input current waveform. Proportional to VAC when VAC is larger than VCB-VS. .................................................................................94 Fig. 6.10. Magnetic-switch Single-Stage system with full-wave isolated dc/dc converter[db194]................95 Fig. 6.11. Delay inductor current and switch current. a) Half-wave magnetic-switch configuration (Fig.3.14). b) full-wave magnetic-switch configuration (Fig.6.10)..............................................................95 Fig. 7.1. PFC boost converter with average current mode control.............................................................100 Fig. 7.2 The target of the efficiency improvement – increasing the worst case efficiency. ........................100 Fig. 7.3. Single Ended Primary Inductance Converter (SEPIC) PFC converter.........................................101 Fig. 7.4. Two-switch buck-boost PFC converter.......................................................................................102 Fig. 7.5. Boost Interleaved Buck Boost (BoIBB).......................................................................................102 Fig. 8.1. Conversion stress illustrated by the numerical gradients of the conversion lines.

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1a-1c: standard boost operation. 2a-2b: switchable topology consisting of a boost and a buck mode. 3: Static step-down................................................................................................................106 Fig. 8.2. Boost converter with a voltage source is series with the output voltage.......................................107 Fig. 8.3 Normal operation modes for the boost-boost switchable topology. a) VIN < VOUT, VS = 0, IS = 0. b) VIN > VOUT, the VS-voltage alternates between 0 and V. ...........................108 Fig. 8.4. Impedance of the the voltage source and the related operation modes.........................................108 Fig. 8.5. SMPS implementation of the voltage source. .............................................................................109 Fig. 8.6. a) Transformer coupled voltage/current source implementation. b) Reflected output voltage seen from port #1. c) Reflected input inductor current seen from port #2......................................110 Fig. 8.7. EWiRaC. Push-pull primary-side, full-bridge secondary-side rectifier........................................111 Fig. 8.8. Alternative voltage/current source implementations. a) Primary-side full-bridge switch. b) Secondary-side double-winding rectifier..............................................................................................112 Fig. 8.9. Single-ended version of the voltage/current source arrangement. a) Primary side. b) Secondary side.....................................................................................................................................112 Fig. 8.10 Dual-inductor EWiRaC.............................................................................................................113 Fig. 8.11. Auto-transformer EWiRaC .....................................................................................................113 Fig. 8.12. Active rectifier EWiRaC..........................................................................................................114 Fig. 8.13. Standard transformer-based EWiRaC.......................................................................................115 Fig. 8.14. EWiRaC operating as a standard boost converter (VIN < VOUT). a) Timing diagram of circuit voltages and currents. b) Equivalent circuits for the two operation modes....................116 Fig. 8.15. EWiRaC operating as an isolated boost converter (voltage-source mode, VIN > VOUT). a) Timing diagram of the circuit voltages and currents. b) Equivalent circuits for the 4 operation modes.......................................................................................117 Fig. 8.16. Alternative current paths in transient mode. a) Non-dissipative snubber. b) Dissipative snubber..............................................................................................................................118 Fig. 8.17. a) Two-switch buck-boost converter used in the switchable topology mode. b) Buck-boost type efficiency curve, correct choice of Q1 (solid line) over sized Q1 (dashed line)..............120 Fig. 8.18. Inductor comparison. a) VAC = 90V. b) VAC = 230V. c) VAC = 270V.........................................122 Fig. 8.19. High-frequency ac inductor current. a) Boost current. b) Buck current......................................124 Fig. 8.20. General control scheme of the EWiRaC...................................................................................128 Fig. 8.21. Boost (dB(t)) and voltage-source (dVS(t)) duty-cycles as a function of the time varying line voltage. In this example, VOUT is equal to half the line peak voltage......................................128 Fig. 8.22. Peak current mode PFC control scheme...................................................................................129 Fig. 8.23. Step in input current caused by the standard slope compensation scheme. .............................130 Fig. 8.24. Dc-shifted slope compensation.................................................................................................131 Fig. 8.25. Average current mode PFC control. Independent PWM modulation of dB(t) and dVS(t). ...........132 Fig. 8.26. Dc-shifted carrier, dual PWM modulator..................................................................................132 Fig. 8.27. Implementing the voltage-source PWM pattern. a) Logic. b) Generated PWM pattern..............133 Fig. 8.28. Transformer-less EWiRaC.......................................................................................................134 Fig. 8.29. Modified PFC SEPIC [34],[35]................................................................................................135 Fig. 9.1. Block schematic of a peak current controlled EWiRaC...............................................................139 Fig. 9.2. Input voltage and current of the experimental converter of Fig. 9.1. VAC = 90V..........................140

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High Efficient Rectifiers Fig. 9.3. Input voltage and current of the experimental converter of Fig. 9.1. VAC = 230V. ......................140 Fig. 9.4. Efficiency of the peak current controlled EWiRaC. VIN = 90VAC ..............................................141 Fig. 9.5. Block schematic of the average current controlled EWiRaC using level shifted carrier...............142 Fig. 9.6. a) Level shifted carrier approach. b) level shifted error voltage approach....................................142 Fig. 9.7. Simulated average current mode control with level shifted carrier and overlapping duty-cycles...........................................................................................................................143 Fig. 9.8. The inductor current during the transition where VIN exceeds VOUT. This view is a zoom of the marked area in Fig. 9.7..................................................................................................143 Fig. 9.9. Drain-source voltage of the switch, Q1. The bottom plateau of the waveform is equal to the output voltage of 185VDC. The upper plateau is equal to twice the VOUT...........................................144 Fig. 9.10. Line voltage (upper trace) VAC = 90V. Error signal (bottom trace) generated by the UCC3817......................................................................................................................................145 Fig. 9.11. Line voltage (upper trace) VAC = 230V. Error signal (bottom trace) generated by the UCC3817. ....................................................................................................................................145 Fig. 9.12. Input voltage and current of the experimental converter of Fig. 9.5. VAC = 115V. ....................146 Fig. 9.13. Current harmonics in the input current of the experimental converter in Fig. 9.5. VAC = 115V. ..........................................................................................................147 Fig. 9.14. Input current of the experimental converter in Fig. 9.5. VAC = 135V. .......................................147 Fig. 9.15. Input current of the experimental converter in Fig. 9.5. VAC = 185V. .......................................148 Fig. 9.16. Drain voltage of Q1, Q2 and Q3 referenced to ground. VAC = 185V, VOUT = 185V and POUT = 500W. ...............................................................................................................148 Fig. 9.17. Input voltage and current of the experimental converter of Fig. 9.5. VAC = 230V. ....................149 Fig. 9.18. Current harmonics in the input current of the experimental converter in Fig. 9.5. VAC = 230V. ..........................................................................................................149 Fig. 9.19. Measured efficiency of the EWiRaC in the low-line range.......................................................150 Fig. 9.20. Measured efficiency of the EWiRaC in the high-line range.....................................................150 Fig. 9.21. Measured efficiency of the EWiRaC at full output power, 500W, as a function of the line voltage................................................................................................................151 Fig. D.1. Input interface to the "Data-table". ...........................................................................................233

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List of tables Table 2.1. EN61000-3-2 harmonic current limits (*λ = PF)......................................................................29 Table 3.1. Useful database inputs...............................................................................................................34 Table 3.2. Non-isolated PFC converters.....................................................................................................37 Table 3.3. Isolated low bandwidth converters.............................................................................................37 Table 3.4. Examples of Reduced Power Processing PFC converters............................................................39 Table 3.5. Examples of Single-Stage PFC converters.................................................................................43 Table 5.1. Voltages and currents of interest when calculating CLF............................................................59 Table 5.2. Calculated Component Load Factors for the 2 converters shown in Fig. 5.2...............................62 Table 5.3. CLF for 3 different isolated converters......................................................................................67 Table 5.4. CLF for the basic topologies: buck, boost, buck-boost, isolated buck and isolated boost. **Does not apply to single-ended isolated Buck- and Boost converters.......................................................68 Table 5.5. Component stress for 3 different static conversion ratios............................................................69 Table 5.6. Component stress for 3 different dynamic conversion ratios.......................................................71 Table 5.7. Power system comparison between a single-stage and a Two-Stage system for a 4:1 dynamic input range..................................................................................................................................73 Table 5.8. Comparison of an ac/dc- and dc/dc boost converter....................................................................76 Table 5.9. The resulting dc/dc range after equalizing the individual component stress...............................77 Table 6.1 Comparison of component stress for the two implementations shown in Fig. 6.3........................85 Table 6.2. Comparison conditions and results (* minimum stress according to CLF).................................86 Table 6.3. Comparison of DCM flyback [22], buck and boost input current shapers...................................89 Table 6.4. Performance of the magnetic-switch Single-Stage systems. .......................................................96 Table 8.1. Conduction loss comparison at 90VAC. *) No associated switching losses.................................120 Table 8.2. Relative capacitor rms-current stress at 90VAC. .......................................................................123 Table 8.3. Summarized performance of the three approaches at 90VAC.....................................................127 Table 9.1 Calculated power losses of the experimental EWiRaC. PIN = 530W, VAC = 90V.......................138

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List of abbreviations

PFC

Power Factor Correction/Control.

EN61000-3-2 European standard setting the limits for the harmonic current content in the line current PF

Power Factor

Rms

Root mean square

ICS

Input Current Shaper

SMPS

Switch Mode Power Supply

ESR

Equivalent Series resistance

EMI

Electro Magnetic Interference

PWM

Pulse Width Modulation/Modulator

CCM

Continuous Conduction Mode

DCM

Discontinuous Conduction Mode

BCM

Boundary Conduction Mode

PCB

Printed Circuit Board

AC

Alternating Current

DC

Direct Current

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Chapter 1

Introduction When this project was initiated, one of the driving forces was the coming implementation of the new European standard, EN61000-3-2. This new standard will affect the way power supplies are designed both in terms of cost, complexity and efficiency. Consequently, the search for new power supplies dedicated to comply with EN61000-3-2 was an ongoing task. Before there were any talk of implementing regulations concerning the low frequency current harmonics in the utility grid, the only well known, well tested solution to this problem was a PFC boost converter. Adding a pre-converter in series with the original power supply would increase the cost and decrease the overall efficiency. Facing these problems researchers began developing new approaches to accommodate a reduction of the low frequency current harmonics. One of the obvious ideas, was to eliminate the pre-converter by combining the two stages, into a single stage thereby reducing the cost and increasing the efficiency. Since only one stage was processing the power compared to two stages, this approach seemed like a good alternative to the TwoStage approach. The Single-Stage approach is one of the dominating ideas presented in the past decade with numerous different implementations. Since the regulations allow for a significant amount of harmonic distortion, topologies not able to obtain a pure sinusoidal current waveform and therefor not usually used for Power Factor Correction (PFC), have been proposed. The research on the subject of Power Factor Correction has been carried out both in the industry and at the universities. The later have flooded the literature with "new and improved" methods of implementing PFC power supplies (the author not excluded). But when you turn to the industry and ask what kind of PFC solution, both in terms of topology and architecture, that they are using, the answer you get in 9 out 10 times, is a PFC boost converter in a Two-Stage system. So, regardless of all the "New and Improved"-approaches reported in the literature, the cornerstone of the modern PFC power conversion is still the basic boost converter. One of the two major objectives of this thesis, is to investigate the performance of the alternative PFC solutions, and compare them with the Two-Stage solution, using a PFC

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High Efficient Rectifiers

boost converter as the pre-converter. The objective is to clearly identify the pros and cons of the alternative solutions so that the advantages/disadvantages becomes more visible. Hopefully, this will create an overview and an understanding of how a reasonable implementation of a PFC system should be carried out. The second objective is to bring the research within ac/dc-conversion one step further. By recognizing the better approaches and identifying where the problems occur, new solutions will be introduced setting the bench-mark for future research in this field.

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Chapter 2

Standard PFC and EN61000-3-2 Obtaining power from the utility grid can be done in different ways. The most common way of doing this is by using a bridge rectifier and a large filter capacitor (peak rectification). This approach has the advantage of being very simple and low cost. For the end user of the equipment there is only one drawback, which is a significant reduction of the power factor. New regulations has been put into effect, reducing the use of the bridge rectifier, in order to obtain a better supply voltage quality. The regulations limits the allowable harmonic current distortion to a level that for some applications makes it impossible to use the standard peakrectification approach. There are already existing solutions that reduce the harmonic distortion to very low levels, but the regulations does allow for a certain amount of distortion which in some cases can be taken advantage of. This chapter gives a short introduction to the concept of Power Factor with an illustrative example. Furthermore, the new European standard, EN61000-3-2, will be introduced, and the consequences of the regulations will be discussed.

2.1 Definition of Power Factor (PF) The concept of Power Factor (PF), is a measure of how well the power from the utility grid is obtained. PF is a number in the range between 0 and 1, and it is calculated as the ratio of the Real power (consumed power) to the Apparent power. PF

Real power = Apparrent power

(2.1)

Assuming that the line voltage is almost a perfect sinusoidal, the real power is defined as the product of the fundamental of the voltage, the fundamental of the current and the phase displacement between these two:

=

⋅

⋅ ( )

P Real V 1,RMS I 1,RMS cos φ

(2.2)

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High Efficient Rectifiers

The apparent power is the product of the rms voltage and current: P App.=V RMS⋅I RMS

(2.3)

By using Eq.(2.1)-(2.3), the PF can be expressed as: PF

= II ⋅cos (φ)

(2.4)

1,RMS RMS

The total rms current, IRMS in Eq.(2.4), can be rewritten in terms of the rms value of each contributing harmonic: PF

=



2

I 1,RMS 2



2

I 1,RMS I 2,RMS .. I n,RMS

⋅cos (φ)

(2.5)

From Eq.(2.5) we can see, that the PF is affected by two things, the ratio of the fundamental to the total content of harmonic currents, and the phase difference between the fundamental of the voltage and current. The above mentioned ratio of the fundamental to the total content of harmonic currents, can also be expressed in terms of Total Harmonic Distortion (THD). The THD of the current is defined as: THD =

I 22,RMS  I 23,RMS .. I 2n,RMS I 1,RMS

(2.6)

By substituting Eq.(2.6) into Eq.(2.5) we get the relationship between the total harmonic current distortion and the PF: PF

=

1



1 THD

⋅cos (φ)

(2.7)

2

As it will be shown later in this chapter, the regulations does not directly impose limitations on the THD, PF or cosφ, but only on each individual harmonic of the fundamental current.

2.2 General PF considerations Previously, the concern regarding PF was a matter of correcting the cosφ, which corresponds to the phase difference between the fundamental of the voltage and the current. The household were dominated by equipment that basically were linear, a mixture of resistive and inductive loads. In these cases the matter of correcting the PF was a matter of correcting the cosφ, which can be accomplished relatively easy, by means of passive compensators. These compensators are not placed at the grid connection of every household but at a reasonable point covering a larger area. Form the point where the compensator is located -26-

Standard PFC and EN61000-3-2

and out to the individual households the increase in rms current-flow is inevitable, but this distance is usually nothing compared to the distance between the power plant and compensator location. Today it is no longer enough only to compensate for cosφ. The household equipment now contains a great deal of nonlinear loads dominated by the bridge rectifier followed by a large bulk capacitor (Fig. 2.1a). The nonlinear loads results in distortion of the line current, which introduce harmonics other than the fundamental.

Fig. 2.1. Ac/dc conversion using peak rectification.

The configuration shown in Fig. 2.1a is very common and can be found in most electronic equipment. This circuit converts the ac-voltage to a dc-voltage by peak rectification. Because of the peak rectification, a large number of harmonic currents are generated, resulting in a very poor PF, typically in the area of 0.5-0.6. To illustrate the effects on the line current, when using the peak rectifier as an ac/dc converter, the configuration shown in Fig. 2.1a have been tested using the following specifications: VIN POUT Load C Bridge

: 230VAC, HP6843A : 330W : Constant power load (Switch-mode Power Supply) : 660µF, esr = 200 mΩ : GBU8J, Rd = 20 mΩ

The reason for using a constant power load, is that the bridge rectifier configuration is typically loaded by a switch-mode converter. Within its regulation bandwidth, the converter constitute a constant power load. The type of load does affect the PF, but it is only significant in case of large voltage variations on the capacitor ( a small capacitor). For the setup described, there is very little difference between the results obtained using a constant power load, compared to a constant impedance load. The results obtained from the test circuit can be seen in Fig. 2.2. Fig. 2.2a shows the line voltage and current, Fig. 2.2b is the corresponding spectral-analysis of the current. For the example shown in Fig. 2.2, the resulting power factor is equal to 0.45. For the bridge rectifier configuration, the PF is dependent on the load, the parasitic resistance in the components and the size of the capacitor. In the test circuit, 2µF/W is used (a rule of thumb indicate 1.5µF/W @ 230VAC [1]). The amount of capacity at the output is dictated by the application. The test circuit is designed to have a 35ms hold-up time allowing a 20% drop in -27-

High Efficient Rectifiers

the output voltage.

Fig. 2.2. Measurements on a bridge-rectifier + filter capacitor. VAC = 230V, POUT=330W, CB=660µF (2µF/W). a) Voltage- and current waveform. b) Harmonic content.

The degradation of the PF is caused mainly by the high harmonic content, and not so much the phase-difference between the fundamentals of the voltage and current. The phase difference was measured to 0.09 rad, which is also indicated by the current placement in Fig. 2.2a. From the utility companies point of view, a PF=1 is preferable, since only real power has to be supplied, leading to better utilization of the grid. For the end user a PF correction of each apparatus would affect the retail prize, and the efficiency will most likely be penalized, resulting in higher electric bills. The real benefit for the end-user is the capability to obtain maximum power from the grid. In DK the maximum power outlet from a ordinary wall-socket is 2.3kW so a PF=0.5 will cut the obtainable power into half. This can be a problem in office buildings where the electronic equipment are dominated by computers and monitors (where the configuration of Fig. 2.1a is commonly used).

2.3 EN61000-3-2 The European norm EN61000-3-2 was put into effect January 1st 2002, with the purpose of limiting the current harmonics injected into the grid. Depending on the equipment, different classes applies. As of today, there are four different classes in EN61000-3-2.







Class A: Balanced three-phase equipment and all other equipment, except that stated in one of the following classes. Class B: Portable tools. Class C: Lighting equipment, including dimming devices. Class D: TV-receivers, PCs and PC-monitors (70W ηdcdc

(6.14)

The above equation is the mathematical correct expression but since the denominators in Eq. (6.14) are in the same range, Eq. (6.14) can for all practical use be reduced to: -92-

Comparing the state-of-the-art approaches

∆ηPFC>|∆ηdcdc|

(6.15)

The efficiency considerations regarding the Single-Stage versus the Two-Stage approach can basically be quantified by Eq. (6.15):


Can the PFC-stage efficiency be increased more than the dc/dc-stage efficiency is decreased.

6.4.2.2 Comparisons In this comparison the dc/dc stage for both the Single-Stage and the Two-Stage systems will be an isolated buck derived converter (full-bridge, half-bridge, push-pull etc.). In the TwoStage system, the PFC stage will be a PFC boost converter. The comparison will again concentrate on the losses in the active semiconductors (here MOSFETs) where significant stress is generated by the input voltage variation. The other power components that comprises the converters also suffers from the input voltage variation, but not by the implementation of the galvanic isolation. In the Single-Stage solution, the inductor in the dc/dc stage is subjected to the full voltage variation. In the Two-Stage system, the PFC boost inductor is subjected to the voltage variation whereas the inductor in the dc/dc stage is in theory not subjected to any stress (Chapter 5). The comparisons will comprise of two steps. In the first step the effects of the ICS-cell in Fig. 6.7 will be ignored so the dc/dc stage is operated from a dc voltage equal to the line peak voltage. By comparing the conduction losses of the two approaches using the same chip die area an estimate of the voltage range where the two solutions have similar conduction losses will be calculated. The second step is to investigate the ICS-cell an its effect on the losses. The target input-voltage specifications is the universal line range defined here as 90-270VAC. By comparing the Two-Stage system with a Single-Stage system consisting of a simple bridge-rectifier and a capacitor (Fig. 2.1a), cascaded by an isolated buck derived dc/dc converter, the stress on the active switches will be compared using the method described section 6.2. The worst case conduction losses occur at low line. The dc input voltage to the SingleStage dc/dc converter is equal to the line peak voltage (127V) and the dc input voltage to the dc/dc stage in the Two-Stage configuration, is equal to the maximum occurring line peak voltage (382V). For the Single-Stage converter, the conduction losses will be proportional to: 4⋅( V BR ) 2 P 1stage ∝ ( 1 ⁄ 4 )⋅ADie⋅I Q,rms,dcdc 2

(6.16)

For the Two-Stage solution the conduction losses are proportional to:

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High Efficient Rectifiers

(V BR )2 2 4⋅( V BR )2 2 P 2stage ∝ (1 x)⋅ADie⋅I Q,rms,pfc ( x ⁄ 4)⋅A Die⋅I Q,rms,dcdc

(6.17)

Solving Eq. (6,17) for minimum losses results in x=0.44 (same as Eq. (6.8)) which relates to about half of the die area is used in the PFC stage and the other half in the dc/dc stage. Assuming that VBR is the same for the two configurations (Eq. (6.16) and (6.17)), the conduction loss ratio at 90VAC is equal to: (6.18)

P 1stage =1.75 P 2stage

The conduction losses are 75% higher in the Single-Stage compared to the Two-Stage configuration and the losses associated with the ICS cell are still not accounted for. This clearly shows, that the Single-Stage systems are not suited for the wide input voltage range. Narrowing down the voltage range by increasing the minimum ac voltage results in Eq. (6.16) and (6.17) being equal for VAC = 182V. Therefore, the two configurations have the same performance with regard to worst case conduction losses for an ac voltage range of 182-270VAC which actually corresponds to the European voltage range. The effect of the ICS cell on the switch stress is not easy to quantify since the control of the ICS is indirect and changes according to line voltage and load conditions. In the following a model representing an ideal magnetic-switch scheme will be presented. With regard to component stress this model will represent the best case operation! The ICS-cell (Fig. 6.7) in the magnetic-switch Single-Stage systems presented in chapter 3 (Fig. 3.14) can be modeled as a series connection of a voltage-source and a loss free resistor. For further details regarding the model of system, refer to [db162].

Fig. 6.9. Magnetic-switch Single-Stage system. a) Modeled as a series connection of a voltage-source (VS) and a loss free resistor (RLF). b) Input current waveform. Proportional to VAC when VAC is larger than VCBVS.

The input current is proportional to the line voltage when the time varying input voltage is greater than VCB-VS. In this idealized case, it is easy to calculate the conduction angle of the current shown in Fig. 6.9b so that compliance with the regulations is possible. In order to comply with the class D limits of EN61000-3-2 a minimum theoretical conduction angle of 67.44 degrees at full power is necessary [db162]. The idealized model assumes that the input-voltage, VCB, in Fig 6.9a to the isolated dc/dc converter is a dc-voltage equal to the

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Comparing the state-of-the-art approaches

line peak voltage. In reality, for a well designed ICS-cell this voltage is slightly larger than the line peak voltage, typically about 20V-30V.

Fig. 6.10. Magnetic-switch Single-Stage system with full-wave isolated dc/dc converter[db194].

The system shown in Fig. 6.10 uses a full-wave isolated dc/dc converter which enables a magnetic-switch duty-cycle from 0 to 100% of the duty-cycle used in the isolated dc/dc converter [11],[26],[db194]. The system shown in chapter 3, Fig. 3.14, is using a half-wave isolated dc/dc converter which reduces the maximum effective magnetic-switch duty-cycle from 1 to 0.5.

Fig. 6.11. Delay inductor current and switch current. a) Half-wave magnetic-switch configuration (Fig.3.14). b) full-wave magnetic-switch configuration (Fig.6.10).

The inductor design is assumed to facilitate the ideal operation of the ICS-cell in terms of minimum switch stress. The input inductor, LB, is assumed very large (minimum ripple) and the delay inductor, LD, is designed to achieve the necessary duty-cycle modulation. Depending on the configuration, if it is a half-wave or a full-wave based magnetic-switch, there is a difference in the imposed switch-stress. The delay inductor current and the resulting switch current for the half-wave magneticswitch (a) and the full-wave magnetic-switch configuration (b) is shown in Fig. 6.11. The switch current in the half-wave configuration is simply the reflected current from the output section plus the reflected delay inductor current. The delay inductor only adds to the switch stress during the conduction period of the input section. For the full-wave configuration, the switch current is also the reflected current from the output section plus the reflected delay inductor current but in this configuration, the delay inductor current is flowing in the opposite direction of the switch-current at the beginning of each switch turn-on (only true -95-

High Efficient Rectifiers

for d > 0.25). The result is that the delay inductor current is transferred directly to the output inductor in the isolated dc/dc converter reducing the switch current in this period. After the main switches have been turned on for a while, the direction of the delay inductor current changes and can hereafter be seen as an additional current in the switch (Fig. 6.11b). Another difference between the two configurations of Fig. 6.11 is the size of the delay inductor needed to perform the current shaping. The delay inductor in the full-wave configuration operates under twice the effective frequency compared to the half-wave configuration, which is one of the known benefits of the full-wave configuration. Furthermore, the delay inductor has to change twice the current (+ILb -ILb) compared to the half-wave configuration. The delay inductance needed for the full-wave configuration is therefor 4 times smaller than for the half-wave configuration. Table 6.4 summarizes the comparison of the reference Two-Stage solution and the magnetic-switch Single-Stage solutions using a half-wave and a full-wave based magneticswitch configuration. The input voltage range is reduced for the two Single-Stage systems until the switch conduction losses are equal to that of the Two-Stage system using the same chip die area. Eq.(6.2) is used to relate the conduction losses to the die area. The switch in the half-wave configuration has higher voltage rating but is not penalized by the more than square law of Eq.(6.1). Ideal implementation (Class D compliance) Magnetic-switch type n = N1/NP

Half-wave (Fig. 3.14)

Full-wave (Fig. 6.11)

0.34

0.17

1

1

1.16

1.32

213-247 VAC

198-262 VAC

VAC,Peak / VCB VAC range (Vmax/VMin) European capability

range

American range 107-124 VAC 99-131 VAC capability Table 6.4. Performance of the magnetic-switch Single-Stage systems.

The shaded rows in table 6.4 shows the effective AC voltage range for which the worstcase conduction losses compared to a Two-Stage system are equal. The turns ratio, n, and the ratio of peak line voltage (VAC,Peak) to bulk capacitor voltage (VCB) are necessary parameters for calculating the switch rms currents. Without taking into account the effects of the ICS cell, the Single-Stage solution was found to have the same conduction losses as a Two-Stage system for an input range of 1.5:1. The effects of the ICS cell reduces this range to about 1.3:1 for the ICS cell using the fullwave configuration. The penalty of using the ICS cell is therefore relatively small. 6.4.2.3 Summary The Single-Stage systems rely on a single control loop to carry out both the PFC function and the fast regulation of the dc/dc converter. The output of the dc/dc converter is regulated by the control system and the PFC function is achieved by choosing an input section that have inherent PFC abilities. As for the Two-Stage configuration an internal -96-

Comparing the state-of-the-art approaches

energy storage is necessary to decouple the pulsating input power. This energy storage is typically comprised by a large capacitor. This capacitor voltage is not controlled by the control loop but is adjusted according to the input/output power balance. For the pure switch-sharing Single-Stage systems this voltage can only be controlled within reasonable limits if both the input- and output inductors are operated in DCM. Furthermore, this configuration always generates more semiconductor stress compared to the Two-Stage configuration. For the magnetic-switch Single-Stage systems the capacitor voltage can be controlled to just above the line peak voltage (best case) and with both the input and output inductor operating in CCM. The switch-stress contribution from the input section is significantly lower for this type of Single-Stage converters compared to the pure switchsharing type and for very narrow voltage ranges the switch stress is equal to or lower than for the Two-Stage configuration. For the universal line range (ac-range = 3), the Two-Stage solution is without doubt the optimal choice. The magnetic-switch Single-Stage configuration becomes interesting when the ac-range is reduced. For an ac range of about 1.3 the conduction losses for both the Single-Stage and the Two-Stage system are the same using the equal die area aproach.

6.5 Summary The Two-Stage solution is the superior approach for universal line operation. The alternative approaches classified as either "Reduced Power Processing" or "Single-Stage systems" generates excessive component stress when forced to operate from a wide input voltage range. For the Reduced Power Processing scheme with sinusoidal input current the isolated converter has to be connected directly between the input- and output terminal in order to achieve less than two times power processing. Having the isolated converter processing pulsating power from a variable input voltage range generates extreme component stress compared to a Two-Stage solution. Furthermore, the auxiliary converters needed for the Reduced Power Processing approach are typically buck-boost and isolated derived converters, which are high component stress converters. The switch-sharing Single-Stage systems should for most applications never be used. The magnetic-switch Single-Stage converters offers reasonable performance if the considered input range is below 1.3:1. For the wide input voltage range, the Two-Stage approach is the superior approach. The remainder of this thesis is devoted to improve the PFC converter in the Two-Stage configuration.

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Blank page

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Chapter 7

Non-isolated PFC converters Understanding that the Two-Stage solution is the most efficient approach for a universal line PFC power supply, the number of PFC converter topologies to choose between are greatly reduced. There are only a few real candidates to choose from and among these, the PFC boost converter is the obvious choice. The boost converter is one of the low component-stress topologies and is by far the predominant PFC converter. In terms of efficiency, the boost converter has demonstrated the best performance, and together with the simplicity of this approach, there has been no real alternatives. Using other types of non-isolated PFC converters are often driven by the desire to produce an output voltage below the line peak voltage, which can not be accomplished by the boost topology. This chapter will give a short presentation of the boost converter and, to the authors opinion, the best alternatives to the boost converter.

7.1 The Boost PFC converter In the Two-Stage system the lowest obtainable component stress is achieved when the PFC stage converts the ac-voltage to a fixed dc voltage. Typically, the boost converter shapes the input current to an almost perfect sinusoidal waveform even though this is not necessary according to the standard. But for a boost converter under the before mentioned conditions, the sinusoidal input current shaping is in fact the most efficient way to obtain the power from the grid. Fig. 7.1 shows the PFC boost converter and a block-schematic of the control. For medium to high power applications the predominant control strategy is the average current mode control. The average boost inductor current is measured and compared to a reference. This reference signal follows the sinusoidal line voltage and the magnitude of this reference current is controlled by an outer loop. In the outer loop the output voltage is compared to a reference voltage and the bandwidth of this loop is kept well below the line frequency. This loop has to be a slow one in order not to regulate the pulsating input power.

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High Efficient Rectifiers

Fig. 7.1. PFC boost converter with average current mode control.

Fig. 7.2 The target of the efficiency improvement – increasing the worst case efficiency.

The target of the efficiency improvement is illustrated in Fig. 7.2 as the "Before" and "After" curves. The solid line ("Before") represents a typical efficiency curve for a boosttype PFC converter and the dashed ("After") line illustrates the targeted efficiency improvements. As stated earlier, the goal is to improve the worst case efficiency for a universal line rectifier, even at the cost of reducing the best case efficiency. The efficiency-curve of the boost converter has the characteristics of the type given by Eq. (7.1). Efficiency ( x )=100( a⋅x2 b⋅x c )

(7.1)

In Eq. (7.1) the variable x represents the current, which increases when the line voltage decreases for the same output power. The losses in the converter can be split into 3 different parts: 1. Conduction losses (a·x2). These losses are determined by the rms-currents and has a squared contribution to the losses. 2. Proportional losses (b·x). These losses are proportional to the current e.g. caused by the -100-

Non-isolated PFC converters

conductive voltage drop in the input rectifier-bridge. For the boost topology the switching losses are also more or less proportional to the current given that the output voltage is constant. 3. Constant losses (c). Idle-losses e.g. in the control circuit and capacitive discharging. Power losses caused by the threshold voltage drop in the output rectifier (given a constant output voltage). The conduction losses in the boost converter are the largest contributor to the efficiency reduction at low line input. As shown in chapter 6, Fig. 6.1, the component that dissipates the most power is the MOSFET. The losses in the MOSFET are comprised by to two parts, conduction losses (1) and switching losses (2). As the nominal line voltage change, the losses changes and both the conduction losses and the switching losses goes up when the nominal line voltage goes down. The switching losses are more or less proportional to the nominal line current. The conduction losses in the parasitic resistance in the components, are dependent of the squared currents. These losses, in case of the MOSFET, will increase with more than just the squared relation. The conduction losses in the MOSFET are dependent on the switch rms current and for the PFC boost converter the rms-current can be calculated as:

I Q,rms=

1

∫

⋅ π

2




( i ac ) ⋅( 1

(7.2)

V ac,peak ⋅sin (Θ)) V Out duty cycle

Besides the squared dependency of the line current, the duty-cycle also increases as the nominal line voltage decreases. For the universal input voltage range the rms current will vary dramatically and for the 3:1 range (90VAC – 270VAC, VOUT = 400V) the resulting conduction losses will vary with a factor of 35.

7.2 Alternatives to the PFC Boost converter

7.2.1 Buck-boost derived PFC converters An alternative to the PFC boost converter is the SEPIC converter. The SEPIC converter is a buck-boost derived converter and therefore a high component stress converter so with regard to the efficiency the PFC boost converter will perform better.

Fig. 7.3. Single Ended Primary Inductance Converter (SEPIC) PFC converter.

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High Efficient Rectifiers

There are some advantages of using a PFC SEPIC compared to the PFC boost converter. The output voltage of the SEPIC can be chosen without restrains to be below the line peak voltage, and the inrush current is inherently limited to reasonable levels by the relatively small capacitor C1 in Fig. 7.3.

7.2.2 Switchable topologies The more interesting alternatives to the PFC boost converter can be found amongst a group of converters referred to as switchable topologies. A well known switchable topology is the two-switch buck-boost converter shown in Fig. 7.4.

Fig. 7.4. Two-switch buck-boost PFC converter.

Controlling the two switches Q1 and Q2 in Fig. 7.4 with the same control signal retains the buck-boost characteristics of the converter resulting in high component stresses. By controlling the switches with individually control signals the converter topology can be switched between a boost converter and a buck converter. As long as the time varying input voltage is below the output voltage, Q1 is always turned on, D1 is in-active and Q2 functions as the boost switch. When the time varying input voltage exceeds the output voltage, Q2 becomes in-active and Q1 functions as the buck switch. By switching the topology between the boost and the buck mode according to the input voltage the component stress is reduced. For a universal line application the effective input range can be cut in half be choosing the output voltage reasonable (~200V) but there are several drawbacks related to this scheme. In the buck mode the input current is discontinuous and going to the medium to high power level with this type of converter will result in large input filters with associated losses. Another problem is that all of the power has to go through Q1 and even though there is no switching losses associated with this switch in the boost mode, the size of the MOSFET can not be chosen arbitrarily large since this would affect the buck mode operation to much. To reduce the effect of having all the power going through Q1, the approach shown in Fig. 7.5 can be taken.

Fig. 7.5. Boost Interleaved Buck Boost (BoIBB).

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Non-isolated PFC converters

In the case where the time varying input voltage is below the output voltage the BoIBB [16] shown in Fig. 7.5 operates in the boost mode. In this mode Q1 is always on and the diode D1 is in-active. The advantage of this configuration is that only half of the input power has to flow through Q1 and the inductors L1 and L2 operates in parallel. When the time varying input voltage is above the output voltage, the BoIBB operates in buck mode. The switch Q2 is always off and there is no current flowing in L1 and C1. The voltage on C1 is equal to the difference between the input and output voltage. There are also a couple of drawbacks of this configuration compared to the two-switch buck-boost converter shown in Fig. 7.4. In the boost mode, high currents are flowing in C1, and Q2 has to be rated to the input voltage which for practical implementations are higher than the output voltage.

7.2.3 Summary The alternative PFC converters mentioned in this section all have the capabilities of producing an output voltage lower than the line peak voltage and typically for the universal line range the output voltage will be designed to around 200V. It is therefore not completely fair to compare these converters with the boost converter. For some applications the reduced bus voltage is very desirable e.g. where planar transformers are used in the cascaded dc/dc converter. The planar technology is typically limited by the number of turns and reducing the bus voltage with a factor of two also results in a reduction of the number of turns with a factor of two for the same flux-excursion. The lower bus voltage also facilitates the use of other semiconductors which can affect the cost and performance. In terms of energy storage, going to a lower voltage will increase the size of the capacitors for storing the same energy. This fact is slightly compensated for in the switchable topologies since the storage capacitor rms currents relative to the capacitor voltage rating are reduced. At higher power levels the switchable topologies presented in Fig. 7.4 and 7.5 are not desirable because of the discontinuous input current when going into the buck operation mode. At low power levels this filter size can be kept reasonable small but since the EMI limits are absolute limits, increasing the power will give rise to a more than proportional increase in the filter size. The SEPIC converter shown in Fig. 7.3 does not produce the discontinuous input current but retains the high component stress which is characteristic of the buck-boost type converters. If only the PFC stage is regarded, the obtainable efficiency of the boost converter is still the state-of-the-art. The reduced output voltage could have a positive effect on the efficiency of the cascaded dc/dc converter but an investigation into this subject lies outside the limits of this thesis. A commendable work [27] has been carried out on the subject of new topologies for singlephase low harmonic rectifiers and it is from this work the BoIBB converter of Fig. 7.5 -103-

High Efficient Rectifiers

originates.

7.3 The characteristics of high performance converters The switchable topologies are very interesting since they, when designed properly, can cut the effective line range into half and thereby reduce the component stress. In order to obtain the highest possible efficiency it is important that the operation modes that the converter is switching between has the characteristics of either a boost or a buck converter since these converter types will secure minimum component stress. For the ac/dc application it is furthermore desirable that the operation modes are boost like or at least secures continuous input current. In a dc/dc application this might not be so important. The converter "wish list" from chapter 4 is repeated below.





Current limiting: Inrush-, output current Independent output voltage (not dependent on the input voltage) Continuous input current Low component stress

Except for the continuous input current the switchable converters (two-switch buck-boost, BoIBB) possesses the desired features. The low component stress is a direct consequence of the effective reduction of the line range. For a switchable topology to comply with the above list, both modes that the converter switches between should have the characteristics of a boost converter. To derive a converter which switches between to modes, that are essentially the same, might seem like a contradiction. Never the less, this is the main idea presented in the following chapter.

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Chapter 8

A new family of Efficient Wide Range Converters The work done in this project on efficient rectifiers have resulted in a new approach to construct high efficient converters that target the universal line range. These ideas are originated in the approach taken in switchable topologies. Changing the operation mode according to the line voltage can lead to an effective reduction of the line range, resulting in reduced component stress. Switchable topologies are already a well known approach but one of the original contributions of this thesis is the construction of a switchable topology that switches between the same topology, in this case a boost type. The boost topology is in particular a good choice for ac/dc converters. This new type of switchable converter has been made possible by using a new approach called "The series voltage-source approach". This approach makes it possible to switch between to topologies that both have the conversion properties of a boost converter. This new family of converters has been named: Efficient Wide Range Converters, EWiRaC Legal notice: There is a patent pending concerning the subjects presented in the following chapters. This goes for both "The voltage-source approach" and the EWiRaC implementations shown.

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8.1 The series voltage-source approach

8.1.1 Requirements of the switchable topology. The idea of a switchable topology for a wide-range application makes sense since operation of these topologies makes it possible to reduce the effective voltage range. As shown in chapter 5, the larger the conversion ratio the higher the component stress and thereby losses.

Fig. 8.1. Conversion stress illustrated by the numerical gradients of the conversion lines. 1a-1c: standard boost operation. 2a-2b: switchable topology consisting of a boost and a buck mode. 3: Static step-down.

The numerical value of the gradients of the conversion lines in Fig. 8.1 illustrates the amount of stress generated for the particular conversion. The dashed conversion line shown as 1a relates to the worst case condition for a traditional universal range PFC boost converter. As the input voltage increases the conversion gradient decreases. The switchable buck-boost topologies are represented by the conversion lines 2a and 2b. The worst case gradients occur at low and high line but the size of the conversion stress is lower than for the worst case conversion of the boost converter (1a). The switchable topology consists of two modes where the conversion line 2b represents the boost mode and the conversion line 2a represents the buck mode. For the PFC application it is desirable that the input current is continuous as it is for the boost topology. To construct such a switchable topology the conversion lines of Fig. 8.1 can be helpful. As long as the time varying input voltage is below the output voltage the conversion line 2b can be used as this represents a boost function. When the input voltage increase to more than the output voltage a mode change occurs and to keep the boost function the output voltage must change, or to be more correct, the voltage seen by the inductor must change. The function needed to keep the boost operation mode can also be explained by Fig. 8.1. At the point where the input voltage reaches the output voltage the operation mode changes from the conversion line 2b to follow the 1b conversion line. The 1b line is converting up to a voltage equal to or higher than maximum line voltage which means that a static step-down action is needed. This static step-down is represented by the conversion line 3. The "1b" conversion could also step up the voltage to a dynamic changing voltage, which instead has to be larger than the input voltage. The "3" conversion then changes from being -106-

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a static conversion to a dynamic conversion. A practical example of this conversion scheme is shown in section 8.6. The requirements for the desired switchable topology according to Fig. 8.1, can be summarized as: 1. Standard boost operation mode 2. Dc-shifted boost operation mode 3. Static down conversion The first requirement suggest that the foundation of the switchable topology should be a boost converter. Before going into further details, consider the setup in Fig. 8.2.

Fig. 8.2. Boost converter with a voltage source is series with the output voltage.

The switchable boost-boost strategy presented in the form of the conversion lines in Fig. 8.1 can be materialized by the circuit shown in Fig. 8.2. The boost converter is modified by a voltage-source, VS, in series with the output voltage and a current-source, IS, in parallel with the output voltage. The voltage- and the current-source is coupled in such a way that energy can flow from VS to IS. The dc-shifted boost operation, requirement #2, is accomplished by means of the voltagesource inserted in series with the output and the down conversion, requirement #3, is accomplished by the energy transfer from the voltage-source to the current-source

8.1.2 Voltage-source requirements The operation of the scheme shown in Fig. 8.2 can be divided into two normal operation modes, VAC < VOUT and VAC > VOUT. The operation mode related to VIN < VOUT is shown in Fig. 8.3a. In this mode the voltagesource is an effective short-circuit and the standard boost converter is easy to recognize. Fig. 8.3b shows the resulting circuit when VIN > VOUT. The switch Q1 is now inactive so the control of the converter is governed by the voltage-source which switches between 0 and a predetermined voltage, V. The duration of which the voltage-source is zero, is duty-cycle controlled.

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Fig. 8.3 Normal operation modes for the boost-boost switchable topology. a) VIN < VOUT, VS = 0, IS = 0. b) VIN > VOUT, the VS-voltage alternates between 0 and V.

For the above scheme to work a basic requirement apply to the voltage- and current-source arrangement. The power obtained by the voltage-source must be delivered by the currentsource to the output. This relation can be written as: I L⋅V S,AV =V OUT⋅I S,AV

(8.1)

, where VS,AV and IS,AV are mean values of the source voltage and current. The size of L in Fig. 8.3b is assumed large, so that IL can be regarded as a dc current within one switching cycle. Since the voltage VS is duty-cycle controlled, Eq. (8.1) can be expressed as: I L⋅( 1 d )⋅V =V OUT⋅I S,AV

(8.2)

In order to fulfill all of the requirements of the converter "wish list" from section 7.3 there is one specification that in general is not associated with a voltage-source. If the switchable boost-boost converter of Fig. 8.2 should be able to control the inrush current, the voltagesource must be able to exhibit the characteristics of an infinite impedance. The voltagesource impedance should therefore be able to be controlled according to Fig. 8.4.

Fig. 8.4. Impedance of the the voltage source and the related operation modes.

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In case of a current limiting situation (inrush or fault related), the voltage-source should be able to assume a high impedance, so that the current path to the output is disrupted (or almost). This is shown in Fig. 8.4, where the third mode is a current limiting mode and the related source impedance increases to an infinite value theoretically. In the second mode the source impedance switches between zero (ideally) and the source voltage divided by the inductor current. In the first mode the voltage-source should be a short circuit so the related source impedance is ideally zero.

8.1.3 Current-source requirements Since the direction of the power flow is from the voltage-source to the current-source, the current-source should not constitute any load to the output terminals (except for a "negative" load). Like an ideal current-source, the input impedance should be as high as possible. The other basic requirement is, that the current-source is able to transfer the energy obtained by the voltage-source, to the output.

8.1.4 Fundamental implementations of the voltage-source. Because of the requirements the voltage-source has to meet, the obvious choice would be to implement the voltage-source as a regulated switch-mode power supply (SMPS). The SMPS is represented as a two-port network, where the the first port functions as a voltagesource and the second port as a current-source. The power transfer is assumed to be unidirectional and the direction of the energy flow is from port #1 (voltage-source) to port #2 (current-source).

Fig. 8.5. SMPS implementation of the voltage source.

By looking at the realization in Fig. 8.5, it is clear to sea that not all SMPS are suited for the voltage-source implementation. Since the two input ports are referenced to different nodes in the circuit, only a specific group of converters, which consists of isolated converters and buck-boost derived converters, can be used. The input ports to the SMPS block have been characterized as a voltage-source (port #1) and a current-source (port #2) fulfilling the previous defined specifications. If we turn to the impedance that the two ports, #1 and #2, are loaded with (defined as Z1 and Z2), we discover that port #1 is looking into a current-source (high impedance) formed by the inductor, and that port #2 is looking into a voltage-source comprised of the output

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capacitor. This duality is not a coincidence and for all practical circuits this will always be the case, since it makes no sense to have series connected current-sources and parallel connected voltage-sources.

Fig. 8.6. a) Transformer coupled voltage/current source implementation. b) Reflected output voltage seen from port #1. c) Reflected input inductor current seen from port #2.

The duality property can be exploited by coupling port #1 and port #2 through a transformer. The voltage-source characteristics needed for port #1, are provided by the reflected output voltage as shown in Fig. 8.6b. In the same manner, the current-source characteristics of port #2, are provided by the reflected input inductor. The energy transfer from port #1 to port #2 is also accomplished by the transformer implementation. By rewriting Eq. (8.2) and taken into account the behavior of a transformer, it is clear to see that the power balance is intact: I S,AV = V=

( 1 d )⋅I L

(8.3)

n

(8.4)

V OUT n

Inserting Eq. (8.3) and (8.4) into (8.2) results in: I L⋅(1 d )⋅V OUT V OUT⋅( 1 d )⋅I L = n n

(8.5)

Eq. (8.5) states that the power balance is intact and furthermore, it is intact cycle by cycle. This should of course not come as a surprise since this is one of the definitions of an ideal transformer. The possible voltage-source implementations should therefore be found amongst the buckboost type converters and the isolated converters, especially isolated converters where the input inductor (current-source) and the output capacitor (voltage-source) can be reused by the topology.

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8.2 Transformer-based EWiRaC solutions

8.2.1 Standard transformer-based EWiRaC converters The transformer-based solutions does not need any energy storage elements, only means to control the transformer in such a way that the voltage-source requirements can be met. Following the ideas and considerations of section 8.1, a new family of switchable boostboost converters can be constructed. In the solution shown in Fig 8.7, the combination of the input inductor L1 and transformer arrangement forms an isolated boost converter where the primary-side-section is in series with the output voltage. The primary-side transformer configuration can be recognized as a push-pull configuration and the secondary-side rectification is a full-bridge configuration. Before other configurations of the EWiRaC is presented, a brief introduction to the operation of the circuit shown in Fig. 8.7 will be given.

Fig. 8.7. EWiRaC. Push-pull primary-side, full-bridge secondary-side rectifier.

In the range where the input voltage is below the output voltage, the EWiRaC is in standard boost mode, meaning that the voltage-source complex is a shorted. This is accomplished by turning on both switches, Q2 and Q3, so that the flux in the primary-side winding will cancel. When the input voltage rises above the output voltage, the normal boost switch Q1 will be turned off for the duration of this period. In this mode the charging of the inductor is accomplished by turning on both switches Q2 and Q3. Since VIN is greater than VOUT this will result in a positive di/dt of the inductor current. At some point either Q2 or Q3 (alternating) will turn off and the inductor current will flow in the transformer winding where one of the switches is on. Since the flux is no longer canceled the reflected output voltage will occur across the primary-side windings and result in a negative di/dt of the inductor current. An in-depth description of the circuit operation will be shown later in this chapter. Other well known primary- and secondary-side configurations exists that can be used in the EWiRaC. The more useful configurations are shown Fig. 8.8.

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Fig. 8.8. Alternative voltage/current source implementations. a) Primary-side full-bridge switch. b) Secondary-side double-winding rectifier.

Fig. 8.9. Single-ended version of the voltage/current source arrangement. a) Primary side. b) Secondary side.

With the alternative voltage and current source implementations shown in Fig. 8.8 we can construct 4 different EWiRaC converters. Single-ended versions could also be implemented but these configurations have limited operation ranges (duty-cycle constrains) or add excessive voltage stresses. For the completeness on this section a single-ended version of the voltage/current-source implementation is shown in Fig. 8.9.

8.2.2 Alternative transformer-based EWiRaC converters Interleaved boost converters are well known and this concept can also be used with the EWiRaC. An interleaved version of the EWiRaC can be constructed by using the dualinductor push-pull isolated boost converter [28]. By using the duality between the boost and the buck converters, the dual-inductor boost converter can be derived from the Hybridge converter [29] (also know as the current-doubler). Besides the usual advantages achieved by interleaving, the dual-inductor EWiRaC offers further advantages. In the operation mode where the input voltage is below the output voltage, the voltage-source complex should in theory be a short circuit but for practical circuits resistance in the primary-side winding and the MOSFETs introduces some losses. For the dual-inductor EWiRaC the primary winding is bypassed in the low voltage mode. Further more, as for the Hybridge-configuration the dual-inductor EWiRaC can be integrated onto the same core.

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Fig. 8.10 Dual-inductor EWiRaC.

The transformers in the EWiRaC converters are implemented in order to create an effective voltage source in series with the output. Non-isolated transformer types like the Autotransformer can also be used. Fig 8.9 shows the Auto-transformer EWiRaC.

Fig. 8.11. Auto-transformer EWiRaC

The structure of the EWiRaC becomes more simple in the auto-transformer configuration since the secondary side winding can be omitted. The auto-transformer usually offers a much better utilization compared to an isolation transformer. In a normal transformer design, the winding area would be split in two – one half to the primary-side windings and one half to the secondary-side windings. Since there are no secondary-side windings in the auto-transformer all the winding area can be utilized for the primary-side windings which makes this structure particular useful in the EWiRaC.

8.2.3 Active rectifier, transformer-based EWiRaC converters Until now, the input voltages to all of the different EWiRaC implementations have been the rectified line voltage. As for the standard boost converter, the EWiRaC concept can also be incorporated in such a way that the line rectifier can be omitted.

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Fig. 8.12. Active rectifier EWiRaC.

One version of the EWiRaC with active rectifiers are shown in Fig 8.12. This version is based on the EWiRaC shown in Fig. 8.7 but all of the circuits presented in this chapter can be arranged accordingly. The Active-rectifier EWiRaC has the advantage of reducing the number of semiconductor voltage drops in the power path. The drawback of this circuit is the large number of components and that half of these components are only active during one half of the line period. One of the great advantages of the EWiRaC is that the voltage-rating of the boost freewheeling diode can be lowered according to the output voltage. This is not the case for the implementation shown in Fig. 8.12 where the two voltage-source implementations are linked together with the same flux. During the interval where the voltage-source connected between Q1 and D1 is in-active the anode of D1 is pulled below ground, leading to increased voltage stress. To avoid this, the voltage-sources can be implemented with independent flux-paths e.g. using alternative magnetic structures or separate transformer cores.

8.3 Analysis of the EWiRaC operation-modes The most significant change in the operation of the EWiRaC compared to the boost converter is the shift in topology when the input voltage crosses the output voltage. The operation modes will be analyzed using the standard transformer-based EWiRaC, in particular the implementation shown in Fig.8.7. The analysis applies to all implementations in the transformer based EWiRaC family.

8.3.1 Steady-state EWiRaC operation modes. The EWiRaC is only attractive if the desired output voltage is inside the line voltage range, otherwise the mode change will not come into effect and it has therefore little meaning to implement the EWiRaC if the output voltage should be higher than the maximum line voltage. In this analysis we assume, that the output voltage is below the maximum occurring line voltage. The implementation shown in Fig. 8.13 is the same as the one shown in Fig 8.7. -114-

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Fig. 8.13. Standard transformer-based EWiRaC.

The transformer configuration shown in Fig. 8.13 is a push-pull primary and a full-bridge secondary. The relations between the windings T1-T3 can be written as: T 1 : T 2 : T 3=1:1:n

(8.6)

For VIN(t) < VOUT the voltage-source complex is shorted meaning that the circuit becomes that of a standard boost converter. In this mode the input to output steady state transferfunction is given by: (8.7)

V OUT 1 = V IN 1 d 1

, where d1 is the duty-cycle applied to the switch Q1. The effective duty-cycle applied to the switches Q2 and Q3 is in this mode given by: d 2=1

(8.8)

For VIN(t) > VOUT the boost switch Q1 is turned off under the duration of this interval. The voltage-source becomes active and performs the conversion. In this mode the steady-state transfer function is given by: V OUT n = V IN n 1 d 2

(8.9)

d 1= 0

(8.10)

, where n is the transformer turns-ratio as defined by Eq. (8.6) and D2 is the effective dutycycle applied to the switches Q2 and Q3. The restriction in this mode is that the maximum input voltage must obey Eq. (8.11). V IN,Max< V OUT 

(8.11)

V OUT n

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VIN < VOUT: The timing diagram for the voltages and currents of interest is shown in Fig 8.14a and the equivalent circuits of each of the two modes is shown in Fig. 8.14b.

0 < t < T/2 or T < t < 3T/2

T/2 < t < T or 3T/2 < t < 2T

b)

a)

Fig. 8.14. EWiRaC operating as a standard boost converter (VIN < VOUT). a) Timing diagram of circuit voltages and currents. b) Equivalent circuits for the two operation modes.

In this mode the operation of the EWiRaC is exactly like the standard boost operation mode.


At t = 0, a gate signal is applied to Q1 turning it on. In this interval, the boost inductor is in the charge mode and the load is supplied entirely by the output storage capacitor.




At the time d1·T the switch Q1 is turned off and the inductor current commutates to the voltage-source arrangement in series with D1. Since both Q2 and Q3 is turned on, the transformer flux is shorted and the voltage across each winding is ideally zero. Since the flux is canceled, the transformer secondary (T3) is in-active. Assuming equal impedance of the series connection of T2, Q2 and T2 Q3, the inductor current will share equally between the two branches.




At t = T the Q1 turns on again and the operations are repeated.

The voltage stresses on the switch Q1 and the diode D1 are in the boost mode equal to the output voltage.

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VIN > VOUT: The timing diagram for the voltages and currents of interest is shown in Fig 8.15a and the equivalent circuits of each of the 4 modes is shown in Fig. 8.15b. For the duration of this interval, the switch Q1 is turned off and the converter is working in the voltage-source mode. 0 < t < d2·T

d2·T < t < T

T < t < T+d2·T

T+d2·T < t < 2·T

a)

b)

Fig. 8.15. EWiRaC operating as an isolated boost converter (voltage-source mode, VIN > VOUT). a) Timing diagram of the circuit voltages and currents. b) Equivalent circuits for the 4 operation modes.


The switch cycle starts at t = 0 and both switches, Q2 and Q3, turns on. The two windings T1 and T2 are now effectively in parallel and referring to the winding dot notation, the flux is canceled in the two primary windings. The transformer windings together with the switches can now be regarded as a short-circuit if the resistance and stray inductance of this connection is disregarded. The inductor charges in this mode since VIN > VOUT and the inductor current flows in -117-

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both transformer windings T1 and T2. Since the the transformer flux is canceled, the secondary winding, T3, is inactive which also causes the diodes D2-D5 to be reversed biased.


At t = d2·T the switch Q3 turns off and the inductor current commutates to the T1 winding. The transformer flux is no longer shorted and the voltage across the windings T1 and T2 is clamped to the reflected output voltage according to the winding dot notation. The current in the primary winding T1 is transformed to the secondary winding T3 where the transformed current flows through D3 and D4.




At t = T a new inductor charge period starts by turning on the switch Q3. Again, the transformer flux is canceled and the inductor current starts increasing.




At t = T + d2·T the switch Q2 turns off and all of the inductor current commutates to winding T2. The primary current is transformed to the secondary winding T3 where the current is flowing through D2 and D5. The voltage on the secondary is clamped to the output voltage which couples to the primary windings according to the winding dot notation and the transformer turns-ratio.




At t = 2·T a new switch-cycle starts and the 4 intervals is repeated.

Compared to the standard boost mode (VIN < VOUT), the voltage-source mode uses two switching periods before repeating. The switches Q2 and Q3 are therefore operating at half the frequency of Q1 but the effective inductor frequency is unchanged.

8.3.2 Transient EWiRaC operation. One of the benefits of using the EWiRaC compared to the standard boost converter is the ability to control the inrush-current. The voltage-source in series with the output capacitor can be switched off so that the current path from the input to the output is disrupted. This action will typically happen when the inductor current reaches a predetermined limit which means that the inductor is charged with its maximum energy. Since the current path to the output has been disrupted, an alternative path must be provided to prevent destructive voltages.

Fig. 8.16. Alternative current paths in transient mode. a) Non-dissipative snubber. b) Dissipative snubber

Fig. 8.16a shows a well known non-dissipative snubber. The extra winding added to the

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inductor L1 is connected to the output voltage through the diode DT. In case of an over current situation the voltage-source will switch off and the circuit of Fig. 8.16a is the equivalent circuit. The voltage across the switch Q1 will start rising until the voltage across L1 is equal to the reflected snubber-winding voltage. At this point the energy is transferred from the L1 winding to the snubber winding. This arrangement is basically a flyback conversion and in order for this scheme to work, the flyback voltage has to be higher than the voltage-source voltage. This means that the lowest possible voltage that will occur across the switch Q1 is: V DS,Q1 ≥V IN,MAX V OUT

(8.12)

This scheme is not the preferred approach because of the added voltage stress. During steady-state operation there is no added stress but the semiconductors used must be able to withstand the voltages during the transient mode. Another well known scheme is the dissipative snubber implemented in Fig. 8.16b. It is common practice to ad snubbers across the switching elements so this scheme will not add extra circuitry. But the snubber elements have to be designed to dissipate the inductor energy without self destruction. Since this energy can be be relative large the snubber components will be relatively large power components compared to usual snubbers dealing with leakage energy. For this approach to work, the snubber-voltage VSN in Fig. 8.16b has to be larger than: 1 V DS,Q1≥V OUT⋅( 1 )≥V IN,MAX n

(8.12)

The good thing about this approach is that the snubber voltage can be designed to be just above the maximum line peak voltage adding a minimum increase to the semiconductor voltage stress. For practical implementations the configuration shown in Fig. 8.16b might not be the preferred one since the dissipative element is a pure zener diode. There exists numerous other versions that dissipates the energy in a more smooth fashion [38].

8.4 Comparisons In this section the EWiRaC will be compared to the 2-switch buck-boost presented in chapter 7 Fig. 7.4, and a standard boost converter. The boost converter is not capable of producing an output voltage below the line peak voltage so in reviewing these comparisons one should keep this in mind.

8.4.1 Active switches The method used to compare the switch stress in chapter 6 was assuming that the same chip die area was available for each converter. Even though this method is somewhat academic, the good thing about this approach is, that it takes into account the trade-off between -119-

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conduction losses and switching losses. To reduce the conduction losses more die area should be used but this will decrease the switching speed and thereby increase the switching losses. For the switchable topologies the relation between the die area used and the related trade offs between the different types of losses are no longer so significant.

Fig. 8.17. a) Two-switch buck-boost converter used in the switchable topology mode. b) Buck-boost type efficiency curve, correct choice of Q1 (solid line) over sized Q1 (dashed line).

The two-switch buck-boost converter from chapter 7 is repeated above in Fig. 8.17a. During the interval where VIN < VOUT the switch Q1 is always turned on. A significant source of losses in the two-switch buck-boost is the conduction losses in Q1 at low line, so in order to reduce these losses a large die area MOSFET is preferable. Since the switch is always on during this interval, there is no switching losses associated with Q1 during the low line operation. During the interval where VIN > VOUT , Q2 is turned off, and the converter enters the buck mode. In this operation mode the switching losses will contribute significantly to the losses. The shape of the efficiency curve shown in Fig. 8.17b, is typical for a switchable buck-boost converter. The solid line represents a well designed circuit where the worst case efficiency is reached both at low and high line. In this case there is a good compromise between the conduction- and the switching-capabilities of the switches. The dashed line represents a design where the conduction losses has been overcompensated for, resulting in a reduced high-line efficiency. This particular limiting factor of the switchable buck-boost converter does not exist to the same extend for the EWiRaC, basically because of the boost-boost nature of the converter. The switching capabilities of the voltage-source can be decreased significantly before affecting the worst case efficiency of the converter. The switch conduction losses will in this case be estimated using the same die area per MOSFET since the added die area does not impair the switching performance of the switchable topologies. Table 8.1 summarizes the squared rms-currents relative to the output power and the estimated conduction losses using same die area per MOSFET. (IRMS/P)2 Q1 Q2 (+Q3)

2-Sw. buckboost

EWiRaC

Boost

123u*

57u

90u

57u

66u*

-

Conduction 137u 90u 90u loss Table 8.1. Conduction loss comparison at 90VAC. *) No associated switching losses.

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The Q1 switch in the 2-switch buck-boost converter has the same voltage rating as for the switches in the EWiRaC and the boost converter. The Q2 switch should only be rated to the output voltage which in this example is 200V. Because of the lower voltage rating (a factor of 2), the RDS,ON is only one fourth of the other switches used. The EWiRaC also utilizes a third switch, Q3, which is in parallel with Q2, reducing the conduction losses of this branch with a factor of 2. The 2-switch buck-boost has the highest conduction losses of the three implementations, whereas the EWiRaC and the boost converter perform the same. The boost implementation is switching to a voltage twice that of the other two implementations. The currents being switched are the same for all three implementations, so the switching losses can be estimated to be twice as big in the boost converter compared to the other two implementations.

8.4.2 Diodes For both the 2-switch buck-boost and the EWiRaC, the free-wheeling diodes in the boost mode is subjected to twice the average current compared to the diode in the boost converter simply because of the difference in output voltage. The losses in these diodes are relatively insignificant but the associated reverse recovery currents of these diodes contributes considerably to the switching losses in the MOSFET. In a typical PFC boost implementation, the diode is made up by two 300V diodes in series like the STTH806TTI from ST [30]. Reducing the voltage rating of the diodes minimizes the reverse recovery problem considerable. The active diodes in the 2-switch buck-boost and the EWiRaC, should only be rated to the output voltage of 200V which means that only one 300V diode is necessary. So, for the same reverse recovery problems the diode conduction losses related to the average current, are equal for all three implementations. Considering the losses associated with the diode rms-currents, the PFC boost converter will actually have higher losses caused by the larger average-to-rms current ratio. In the writing moment of this thesis, SiC diodes have been introduced by Infineon [18]. These diodes can be characterized as high voltage schottky diodes which does not have any reverse recovery problems. The impact of this new technology has not been considered.

8.4.3 Inductors The worst case conduction losses in the inductors occur at low line where all three topologies operate in the boost mode. It is also at low line that the maximum flux density occurs. Another important factor with regard to the inductor stress is the maximum ac-flux which is proportional to the average voltage applied to the inductor. The size of the ac-flux changes with the line voltage and the three topologies exhibit different characteristics. The output voltage of the boost converter is 400V and for the two-switch buck-boost and the EWiRaC the output voltage is 200V. Fig. 8.18 shows the time varying applied average inductor voltage for VAC = 90V, VAC = 230V and VAC = 270V. At 90VAC the two switchable topologies only operates in boost mode and the maximum applied voltage is reached at a duty-cycle of 50% which in this case corresponds to an

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average applied voltage of 50V for both converters. The average voltage applied to the inductor in the boost converter reaches a maximum of 87V.

Fig. 8.18. Inductor comparison. a) VAC = 90V. b) VAC = 230V. c) VAC = 270V

At 230VAC the two switchable topologies are changing topology at the point where the input voltage reaches the output voltage which is the point where the average applied voltages goes to zero (disregarding the line voltage zero-crossing). The EWiRaC changes from the boost to the dc-biased isolated boost topology and the maximum average applied voltage is again reached at 50% duty-cycle, corresponding to an average applied voltage of 50V. The two-switch buck-boost changes topology from the boost to buck topology which has an incremental effect on the average applied inductor voltage. For the buck topology the maximum applied inductor-voltage is proportional to (1-d) so for the two-switch buckboost converter the maximum inductor voltage is reached at maximum line voltage (270VAC) which in this case corresponds to an average applied inductor voltage of 95V. In terms of ac-flux stress the EWiRaC is only subjected to half the ac-flux at the worst case -122-

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condition compared to the other two converters. For PFC inductors that operates with a high dc-flux the energy-storage capability is a good measure of the size of the inductor. The energy stored in the inductor is given by: 1 2 E L = ⋅L⋅I peak 2

(8.13)

Designing the inductors in the three different converters to carry the same maximum acflux, the EWiRaC design results in an inductor of half the inductance compared to the other two implementations. According to Eq. (8.13), this reduces the needed energy storage capability by a factor of 2, resulting in about half the inductor size.

8.4.4 Output capacitor There are two considerations with regard to the output capacitor – energy-storage and rmscurrent stress. The energy stored in a capacitor is equal to: 1 2 E C = ⋅C⋅V C 2

(8.14)

The physical size and the capacity of the capacitor is usually related through: C⋅V C0 = K

(8.15)

, where C is the capacity, VC0 is the voltage rating of the capacitor and K is a constant related to the size of the capacitor or more correctly to the thickness of the dielectric material used in the capacitor. Eq. (8.15) states that for the same physical size of a capacitor, increasing the voltage rating with a factor of 2 will decrease the capacity with a factor of 2. The PFC boost converter in this comparison stores the energy at 400V compared to 200V for the other two implementations. By using Eq. (8.14) and Eq.(8.15) one will find, that the physical size of the capacitor in the boost implementation, will have half the size for the same energy-storage capabilities compared to the other two implementations. The worst case capacitor rms-currents occur a low line. Table 8.2 summarizes the relative capacitor rms-currents to average output current.

IC,RMS/IO,Average

2-Sw. buckboost

EWiRaC

Boost

1.29

1.29

2.08

2

1.66 1.66 4.32 (IC,RMS/IO,Average) Table 8.2. Relative capacitor rms-current stress at 90VAC.

The rms-current stress is considerable larger for the boost converter compared to the other two implementations. The associated losses in the equivalent series resistor (ESR) in the capacitor will be 2.6 times larger in the boost implementation. The reduction in rms-currents for the 2-switch buck-boost and the EWiRaC could possible -123-

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be used to reduce the physical size of the capacitor but this has not been investigated. In this comparison, the conclusion will be that storing the capacitor energy at a higher voltage using the standard boost, is preferrable.

8.4.5 EMI-filter The boost converter has the inductor in series with the input terminals and is thereby obtaining a continuous input current. The filter requirements are relatively small since only the inductor ripple current needs to be attenuated by the filter. The EWiRaC converter is of the switchable converter type but the overall topology, independent of the operation mode, is that of a boost converter. As shown in the previous section, the EWiRaC actually generates less high-frequency ripple current compared to the boost converter for the same inductance. The two-switch buck-boost converter changes topology from the boost to the buck topology. In the buck mode the input current is highly discontinuous and the generated EMI is significant. In order to give an idea of the filter requirements, consider the following example: The inductor ripple-current in an universal line PFC boost converter is typically designed to be in the area of +- 10 % of the maximum inductor current [31]. The worst case ripple current occurs at 50% duty-cycle. For the two-switch buck-boost converter operating in the buck mode with an output voltage of 200V, the worst case EMI is generated at the peak of the high line voltage(382V). The duty-cycle is at this point approaching 50%. The corresponding high-frequency currents for the boost-mode(EWiRaC) respectively buckmode operation are shown in Fig. 8.19. The amplitudes are relative to the worst case conditions and the same power level.

Fig. 8.19. High-frequency ac inductor current. a) Boost current. b) Buck current.

For the purpose of this comparison we will use this worst case condition as an indicator of the EMI-filter requirements. The high-frequency boost current for 50% duty-cycle can be expressed as [32]: A Boost ( n )=

( 8⋅A1 ) , n ∈[ 1,3,5,... ] (π2⋅n2 )

(8.14)

The high-frequency buck current for 50% duty-cycle can be expressed as [32]:

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ABuck ( n )=

( 4⋅A2 ) , n ∈[ 1,3,5,... ] (π⋅n )

(8.15)

The amplitude of the HF ac inductor current, shown in Fig. 8.19a+b for the boost respectively the buck converter, is related in the following way. The amplitude A1 for the boost current shown in Fig. 8.19a can be expressed as: A1 =

(8.16)

P IN ⋅ 2⋅0.1 90

The amplitude A2 for the buck current shown in Fig. 8.19b can be expressed as: A 2=

(8.17)

P IN ⋅ 2 270

Using Eq. (8.16) and (8.17) the relation between A1 and A2 can be found: A2=

10 ⋅A 3 1

(8.18)

The EMI-limits regarding conducted noise starts at 150kHz. It is therefore common practice, if possible, to choose a switching frequency so this frequency or the next following harmonics is just below the start of the limits. For this example, a switching frequency of 70kHz has been selected. This means that the fundamental and the second harmonic is outside the area where the regulations apply. The first harmonic to be attenuated is the third harmonic of the switching frequency. Using Eq. (8.14), (8.15) and (8.18) the ratio of the third harmonic of the boost and the buck current can be found: A Buck ( 3 ) ≈ 15 A Boost ( 3 )

(8.19)

The EMI-filter in the 2-switch buck-boost should therefore supply 23.5 dB additional attenuation compared to both the EWiRaC and the boost converter. For a simple second-order L-C filter, this would require, that the cut-off frequency of the filter is moved 2 octaves down which is equal to a lowering of the cut-off frequency of a factor of 4. The cut-off frequency of the second-order L-C filter is given by: f ω o=

1

(8.20)

2⋅π⋅ L⋅C

Lowering the cut-off frequency with a factor of 4 would require 16 times the L-C product or 4 times the inductance and 4 times the capacity. Even though this is a simple comparison, it is clear that the 2 switch buck-boost implementation requires considerable EMI-filtering compared to the EWiRaC and the boost -125-

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implementations.

8.4.6 Inrush current limiting For the 2-switch buck-boost converter, there is no additional penalty of controlling the inrush current. As shown in Fig. 8.17a, the 2-switch buck-boost converter has a switch in series with the input terminals enabling the converter to control the input current. The losses in the switch is already accounted for under "Active switches". The EWiRaC is also able to control the inrush current through the operation of the series voltage-source arrangement. Besides the switches used to implement the voltage-source, there is also the parallel connection of the two primary windings of the transformer. These windings will ad to the conduction losses in the circuit. The amount of losses in these windings can almost be arbitrarily small by using a large size transformer or omitted completely if the EWiRaC configuration of Fig. 8.10 is used. For the boost converter additional circuitry is needed to reduce the inrush current. An element of some kind, that can control the inrush current has to be placed in series with the output capacitor.

8.4.7 Output voltage considerations Besides the advantage of storing energy at a higher voltage, there is little to suggest, that the high bus voltage necessary when using the boost configuration is advantageous compared to the lower bus voltage supplied by the 2-switch buck-boost and the EWiRaC. The performance of the semiconductor suggest that a lower bus voltage would be preferable. Also, going towards higher switching frequencies, the parasitic capacitive losses are reduced by using a lower bus voltage.

8.4.8 Summary In all of the comparisons carried out in this section, each approach will be ranked according to its performance. The best approach receives 1 point, the second best 2 points and the worst approach receives 3 points. In case of a tie, the available points are either split or the ranking is split. Table 8.3 summarizes the comparison by accumulating the rankings/points given to give an overall result of the comparison.

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A new family of Efficient Wide Range Converters 2-Sw. buckboost

EWiRaC

Boost

Active switches

2.5 (2)

1 (1)

2.5 (2)

Diodes

1.5 (1)

1.5 (1)

3 (3)

Inductor

2.5 (2)

1 (1)

2.5 (2)

Output capacitor

2.5 (2)

2.5 (2)

1 (1)

EMI-filter

3 (3)

1.5 (1)

1.5 (1)

Inrush current

1 (1)

2 (2)

3 (3)

Output voltage

1.5 (1)

1.5 (1)

3 (3)

Total score 14.5 (12) 11 (9) 15.5 (15) Table 8.3. Summarized performance of the three approaches at 90VAC.

Based on the categories in this comparison, the EWiRaC has the best performance. Whether it is reasonable to summarize the performance of the converters as done in table 8.3 is questionable, since other categories could be added, e.g. cost, that will change the outcome. The cost of implementing new approaches is typically higher, mainly because of two things. The control circuits has to be implemented more or less discrete since commercially ICs are not available. Power components optimized for the new approach might not be mainstream components making these more cost sensitive. But the categories of table 8.3 used in this comparison have a direct influence on the efficiency and the performance of the complete power supply system (e.g. the down stream converter). Another problem with the above approach could be, that each of the categories in the comparison, is treated as equally important. If the size of the output capacitor was deemed the most significant category the outcome might also change. None the less, it is obvious that the performance of EWiRaC is potentially better than the boost converter and the two-switch buck-boost converter. The comparison is carried out for the worst case situation for both the EWiRaC and the boost converter. As mentioned earlier, the worst case situation for 2-switch buck-boost converter could also be the high line situation, so the performance of this approach could be somewhat degraded compared to the conclusions of table 8.3.

8.5 Controlling the EWiRaC The predominant PFC control method for medium to high power PFC boost converters is the average current mode PFC control. Many commercially control IC's are available for this control scheme. Another possible control method is the peak current PFC control. Both will be presented in this section. Besides the control of the input current and the output voltage, controlling the EWiRaC requires additional information of the input voltage relative to the output voltage in order for the switchable topology scheme to work.

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8.5.1 Overall control considerations

Fig. 8.20. General control scheme of the EWiRaC

Fig. 8.20 shows the general scheme of the control system required to control the EWiRaC. In the standard way, information about the current, input- and output-voltages should be provided to the PFC controller. From the effective duty-cycle generated by the PFC controller, duty-cycles for the boost switch and the voltage-source, has to be generated. Information about the mode change has to be provided to the PWM controller.

Fig. 8.21. Boost (dB(t)) and voltage-source (dVS(t)) duty-cycles as a function of the time varying line voltage. In this example, VOUT is equal to half the line peak voltage.

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At high line, the EWiRaC changes operation mode when the input voltage exceeds the output voltage. Fig. 8.21 shows how the mode change affects the duty-cycles. The voltage-source duty-cycle, dVS(t), is equal to 1 during the boost mode, and the boost duty-cycle, dB(t), is equal to zero during the voltage-source operation.

8.5.2 Peak current mode PFC control 8.5.2.1 Standard peak current mode control Peak current mode PFC control is not as common as the average current mode control. The achievable power factor in a wide-range application, is not as good as with average current mode control, but it is typically more than 0.98, with low enough harmonic currents to comply with regulations. In terms of controlling the EWiRaC, the peak current mode PFC control becomes very attractive since the duty-cycle demanded, seems to jump from effectively zero to effectively one. Using standard average current mode control is not an option since this would require the output of the error amplifier to change amplitude momentarily when the input voltage reaches the output voltage. Peak current mode control systems are not in the same way limited by these dynamic restrictions. The standard peak current mode PFC control is shown in Fig. 8.22. Usually, for standard boost converter control, the sensed current is obtained as the switch (Q) current. By sensing the current in this branch, a current transformer can be used instead of a sense resister. Since the switch Q, in Fig. 8.22, is inactive during the interval where VIN>VOUT, this method can not be adapted directly. The inductor current is always flowing in the return path, so placing a sense resistor here enables the peak current control.

Fig. 8.22. Peak current mode PFC control scheme.

As for any peak current mode control, instability can occur at duty-cycles above 50%. Since the input voltage varies all the way down to zero, duty-cycles above 50% is required to control the current and instability might occur. A well known method of stabilizing the -129-

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converter using peak current mode control, is to ad slope compensation [33]. By adding an external slope to the sensed inductor current, the instability can be avoided. The amount of slope required to stabilize the system has to be larger than half the inductor current down slope. diComp. 1 di > ⋅ L downslope dt 2 dt

(8.21)

The inductor down-slope in a standard boost PFC is varying because of the time varying input voltage. In order to stabilize the system, the compensating slope has to be larger than half the largest occurring down-slope, which is when the line voltage reaches zero. A prototype of an EWiRaC using standard peak current mode control is tested in the next chapter. As the results will show, the standard peak current mode control used for PFC boost converters, can not be adopted directly. 8.5.2.2 Advanced peak current mode control For an EWiRaC converter operating at high line, the duty-cycle function will vary from 1 to zero two times compared to the one time for the standard boost converter. This also means, that the maximum down-slope of the inductor current can occur, not only at the zero crossing of the line voltage, but also at the point, where the input voltage reaches the output voltage. If the output voltage is designed to be half the maximum line peak voltage, and the transformer in the voltage-source uses a 1:1 turns ratio, the inductor down-slope for the two worst case occurrences will coincide and the same compensating slope should be able to be used, both when VINVOUT.

Fig. 8.23. Step in input current caused by the standard slope compensation scheme.

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A new family of Efficient Wide Range Converters

As the experimental converter will show, the simple slope compensation scheme is unusable in case of the EWiRaC. In theory, the dynamics of the slope compensation should be able to stabilize the converter, both at the line zero crossing and at the point, where the topology is changed. But when the input voltage reaches the output voltage, the duty-cycle changes from zero to one momentarily which causes a step-change in the reference current. The current subtracted from the reference current, which make up the slope compensation, is directly proportional to the duty-cycle, so the change in the duty-cycle causes the slope compensating current to jump from zero to its full value during the mode transition. The bottom curve in Fig. 8.23 illustrates the change in the compensating current during the mode transition. The upper curve in Fig. 8.23, is the resulting line current where the transition will result in a step change of the current waveform. For a system where the output voltage is placed in the middle of the input range, such that the VIN,Peak = 2·VOUT, the required di/dt of the slope is the same for both modes (VINVOUT). The step-change in the slope compensating current can be fixed, by shifting a dc-current in/out during the transition between the two modes. The magnitude of this dccurrent, should be equal to the peak-to-peak compensating current.

Fig. 8.24. Dc-shifted slope compensation.

By shifting the dc-current in/out during the mode transition, the step-change in the slope compensating current is eliminated and the compensating current undergoes a smooth transition during the mode change. The dashed line in Fig. 8.24 shows the slope compensating current without the dc-shifted compensating current as shown in Fig. 8.23.

8.5.3 Average current mode PFC control with level shifted carrier Average current mode PFC control can be used for the EWiRaC. The switchable converter, BoIBB, shown in chapter 7 Fig. 7.5 has been presented using a modified version of the average current mode PFC control [16]. The duty-cycle functions of the EWiRaC at high-line, which necessitates a mode change, is shown in Fig. 8.21. As mentioned earlier, the controlling duty-cycle undergoes a step change during the transition between the two modes, which makes average mode control seem like an unusable control strategy because this would require the error amplifier to momentarily change the control voltage. But if we concentrate on each of the duty-cycle functions, dB(t) and dVS(t), we can see that individually, these functions are nice continuous functions. So, instead of generating the two different duty-cycle patterns on the background of the master duty-cycle, the duty-cycles should be generated separately but using the same -131-

High Efficient Rectifiers

error signal. The overall scheme of this approach is shown in Fig. 8.25.

Fig. 8.25. Average current mode PFC control. Independent PWM modulation of dB(t) and dVS(t).

As shown in Fig. 8.25, the duty-cycles for the boost switch and for the voltage-source arrangement is generated separately using the same error voltage. The duty-cycle for the boost switch is generated using the lower comparator in Fig. 8.26. In the mode where VINVOUT, the carrier signal to the lower comparator will always be larger than the error signal, resulting in dB(t) = 0. The error signal for the upper comparator is now in the range of the carrier signal resulting in dVS(t) being pulse width modulated. A clear advantage of the scheme shown in Fig. 8.26, is that the mode change is automatically carried out by the closed-loop control system. There is no need for measuring -132-

A new family of Efficient Wide Range Converters

the input and output voltage for the purpose of determining the actual mode. For the peak current PFC control scheme, this has to be carried out.

8.5.4 Generating the voltage-source PWM-pattern After successfully generating the effective duty-cycle function for the voltage-source, the PWM pattern for the individually realizations has to be generated. This PWM pattern is basically the same as the one used for isolated boost converters.

Fig. 8.27. Implementing the voltage-source PWM pattern. a) Logic. b) Generated PWM pattern

The voltage-source pattern generated in Fig. 8.27, is dedicated to the implementations of the EWiRaC using two switches in the voltage-source arrangement but is basically the same for all of the EWiRaC implementations.

8.6 Alternative EWiRaC converters The EWiRaC solutions presented so far can be characterized as a boost-boost based switchable topology which is the fundamental difference compared to other switchable topologies. The boost-boost topology offers continuous input current using a minimum stress converter (boost). The buck-boost based switchable topologies also uses minimum stress converters but with discontinuous input current in the buck mode. The continuous input current can be maintained if a boost-buck/boost based topology is used but with increased converter stress. During the work of constructing the boost-boost based EWiRaC converters another type of switchable topology emerged which has the continuous input current but not entirely the characteristics of a boost-buck/boost based topology. This new type of switchable topology is based on the voltage-source considerations presented in this chapter, but the practical implementation of the voltage-source arrangement differs from the EWiRaCs presented until now. This type of EWiRaC will be referred to as the transformerless EWiRaC (Patent pending!).

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8.6.1 The transformer-less EWiRaC

Fig. 8.28. Transformer-less EWiRaC

Instead of a transformer based voltage-source, the implementation shown in Fig. 8.28, uses a buck-boost type of converter in series with the output. This actually results in number of different operation modes of this configuration. The circuit can be related to the conversion lines of Fig. 8.1, using the alternative "1b" and "3" conversions mentioned in section 8.1.1.

8.6.2 The adopted voltage-source operation mode This mode, follows the operation mode of the EWiRaC converters presented so far. The same control strategies can be adopted, except for the fact that the duty-cycle functions to the voltage-source is reduced to one instead of at least two for the transformer based EWiRaCs. The operation of the circuit in Fig 8.28 will briefly be explained in the following. As for the transformer based EWiRaC, the switch Q2 is always turned on (except for current limiting situations), when the time varying input voltage is below the output voltage. The equivalent circuit is similar to the standard boost converter, and the steady-state transfer function is therefor given by: V OUT 1 = V IN 1  d 1

(8.22)

d 2=1

(8.23)

For VIN > VOUT the switch Q1 is always turned off and the steady-state transfer function is given by: V OUT d = 2 2 V IN d 2 1 d 2

(8.24)

d 1= 0

(8.25)

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In this mode, the voltage on the capacitor C2 is dependent on the duty-cycle d2. The conversion characteristics from the capacitor voltage VC2, to the output, is that of a buckboost converter. V OUT d = 2 V C2 1 d 2

(8.26)

If we assume an output voltage of 200V and a maximum input voltage of 400V, the voltage stress across Q1, in case of a buck-boost type converter, would be 600V. For the converter of Fig. 8.28 operated in the voltage-source mode, the maximum voltage across Q1 can be found to 523V, which is below the voltage stress of a buck-boost type converter. The configuration shown in Fig. 8.28 can also be used as a switchable topology between a boost converter and a SEPIC converter. The switch Q2 would then be a manually operated switch. If the converter was to be operated in Europe, the switch Q2 would be open, and the converter operates as a SEPIC converter. In North America, the switch Q2 would be closed, and the converter operates as a boost converter.

8.6.3 Modified SEPIC The Modified SEPIC converter shown in Fig. 8.29, can also be constructed from the circuit shown in Fig. 8.28.

Fig. 8.29. Modified PFC SEPIC [34],[35].

The difference between a SEPIC and a Modified SEPIC, is the diode D2 in series with L2 and that the capacitor C2, is a large bulk capacitor. By operating the converter in DCM, the voltage across the capacitor C2 can be controlled by the ratio of L1 to L2. In [34] (Appendix A4), a Modified SEPIC has been constructed for the universal line range (90VAC-270VAC). The experimental results of a 210V output, 100W converter shows efficiencies of 93% over the total line range. The voltage on the capacitor is designed to reach 190V at 270VAC so that the maximum voltage stress on the semiconductors are kept at 400V as for the boost converter. At low line (90VAC) the capacitor voltage drops to about 20V reducing the switching losses considerable compared to a standard SEPIC. The BCM Modified SEPIC converter achieves worst case efficiencies comparable with that of the boost converter, but with the capabilities of producing the lower output voltage. The work on this converter is fully documented in [34] and [35] so for further information on the operation of this converter, please turn to Appendix A2 and A4, where copies of the referenced papers can be found in full.

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8.7 Summary The implementation of the voltage-source approach, solves the most significant problems in the existing switchable topologies. Since the voltage-source approach facilitates a switchable topology that uses the boost topology in both modes, the characteristics of the boost converter is maintained throughout the entire input voltage range. This means, that the input current does not become discontinuous as it does for other switchable topologies. These new converters based on the voltage-source approach, are called Efficient Wide Range Converters (EWiRaC). Designing the converters in order to optimize the worst case condition is also simplified since, as for the boost converter, the worst case situation for the EWiRaC is the largest input current situation. For other switchable topologies there are typically two situations that qualify for the worst case situation, which occurs at both extremes of the input voltage range. Several versions of the EWiRaC has been presented together with different control strategies. At the present time, the average current mode control with level shifted carrier seems to be the preferred approach. Using this scheme, eliminates the need for a separate measurement of the input and output voltage to determine the mode change. Peak current mode control can also be used, especially in the interleaved versions of the EWiRaC, where the peak current mode would be advantageous. A modified slope compensation scheme has been presented, to solve the problem with the change of reference current during the transition interval. Furthermore, a comparison between a two-switch buck-boost converter (switchable type), a standard boost converter and the EWiRaC, has been carried out. In this comparison, the EWiRaC demonstrates the lowest overall component stress and thereby shows the potential of being a high efficiency converter. For low power applications, the transformer-less EWiRaC is a good alternative to the boost converter, achieving efficiencies comparable with the boost converter, but with the ability to produce a medium high output voltage, e.g. 200V.

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Chapter 9

Experimental results New converter topologies often seems attractive on paper but with disappointing performance when tested experimental. Prototyping new circuits is the best way to reveal any non-ideal behavior of a circuit. In terms of optimizing the power circuit, the EWiRaC is still in its early phase. The effort put into the experimental work has also been dedicated to verify the operation of the EWiRaC and not so much as to optimize the individually power components. This chapter is devoted to verify the operation of the EWiRaC and show the potential of this converter as a very high efficient, wide input range, ac/dc converter. Besides the work that has been done deriving the power circuit of the EWiRaC, many challenges still exist in designing the surrounding circuitry e.g. the control system. The functions needed to operate the EWiRaC can not be implemented with a single control IC, which is possible for the well known approaches. The EWiRaC has been tested with two different control strategies and the results of the experimental work will be presented in the following.

9.1 Prototype specifications The specifications of the prototypes tested, are given below. The specifications are targeted to be in a typical wide range application in the medium to high power range. VAC VOUT POUT fSwitching

: : : :

90VAC – 260VAC 185VDC 500W 70kHz

The switching frequency is selected so that the first and the second harmonic is outside the frequency band of regulations. The EN55022, which sets the EMI-limits in Europe, starts at 150kHz. Similar regulations in the US, also starts at 150kHz.

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9.2 Estimated worst case efficiency of the EWiRaC converter The worst case operation for the EWiRaC in terms of power losses occurs, as for the standard boost converter, at low line. The selected power components has not undergone a full optimization process, but based on know-how, reasonable power components have been selected to insure high efficiency. In table 9.1, the power components and the associated losses are listed. Component

Type

Losses

% ofPIN

EMI-filter

2*2.7mH, 8A, Rdc= 22mOhm

1.53W

0.29%

Bridge rectifier

GBU8J (8A, 600V)

9.34W

1.76%

3.08

0.58%

STW45NM50, 80mOhm

5

0.94%

SPP20N60S5, 190mOhm

3.7

0.70%

Transformer

RM12, Np=43, dCu=0.75mm

1.01

0.19%

Diode

STTH806TTI (1 diode)

5.03

0.95%

3

A083081-2, Ve=11cm , N=60, dCu=0.95mm

Inductor MOSFET's Q1 Q2+Q3

Total 28.69W 5.41% Table 9.1 Calculated power losses of the experimental EWiRaC. PIN = 530W, VAC = 90V.

A MathCad spreadsheet of the calculated power losses can be found in Appendix B. The theoretical losses are calculated using an input power of 530W at VAC = 90V. The worst case efficiency of the EWiRaC, according to theoretical design, should be in the area of 94%-95% (94.6%). Using the same components, but in a boost configuration, the losses in Q1 would double, the losses will increase in the inductor and the diode (using both diodes in the tandem configuration). The improvements, not counting the losses in the voltage-source, would amount to about 2% at low line. The losses in the voltage-source (Q2,Q3 and the transformer), amounts to almost 1% in efficiency, and the total savings in terms of efficiency, depends on how efficient, the inrush control of the boost converter can be implemented. The EMI filter is constructed as a double-π filter using two common mode chokes. The differential mode chokes are comprised by the leakage inductance of the common mode chokes. This can be practical if the large common mode filter is needed, otherwise this approach take up a relative large amount of board space.

9.3 Prototype 1: Peak current mode control The peak current mode control seems like a good choice of control strategy for the EWiRaC. As shown in chapter 8, the effective duty-cycle exhibits a step change from zero to one and vice versa, in the transition between the two modes of operation. The average current mode PFC control in its original version used in PFC boost converters,

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Experimental results

are not capable of maintaining the control of the input current during the transition. The peak current mode PFC control is not limited in terms of fast duty-cycle changes and does therefore seem like a usable control strategy. The prototype is based on the auto-transformer EWiRaC shown in Fig. 8.11 in chapter 8. Fig. 9.1 is a block schematic of the peak current controlled EWiRaC.

Fig. 9.1. Block schematic of a peak current controlled EWiRaC.

To generate the effective duty-cycle for the EWiRaC, the ML4812 from Fairchild, which is a peak current mode PFC controller, is used. The "Mode selection"-block is a simple comparator determining whether the input voltage is above or below the output voltage and thereby the mode of operation. The "Logic"-block receives information about the effective duty-cycle and the operation mode. Based on these information, the respective duty-cycle functions are generated. The duty-cycles are interfaced to the power circuit through the gate drivers IR2110 from International Rectifier [36]. Fig. 9.2 shows the input current of the experimental converter at an input voltage of 90VAC.

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Fig. 9.2. Input voltage and current of the experimental converter of Fig. 9.1. VAC = 90V.

At 90VAC the EWiRaC is only operating in the boost mode. The voltage source is in this mode to be reckoned as a short circuit. Only in case of an over current situations, the power path through the voltage-source will be disrupted. For an input voltage of 230VAC, the EWiRaC changes mode. The resulting input current is shown in Fig. 9.3.

Fig. 9.3. Input voltage and current of the experimental converter of Fig. 9.1. VAC = 230V.

This first prototype was not implemented with the advanced slope compensation scheme, which is clearly visible in the current waveform. During the transition between the two modes of the EWiRaC, the current is more or less out of control. The step change in reference current causes large oscillations as shown in Fig. 9.3. The current waveform, after the oscillations have died out, follows a different reference compared to the part of the waveform before the oscillations as shown in chapter 8, Fig. 8.23. -140-

Experimental results

Other factors, besides the slope compensation, causes problems near and during the transition between the two different modes. Peak current control becomes very noise sensitive as the duty-cycle goes to zero. Very narrow pulses can be hard to detect, and at very small duty-cycles, the peak current controller will go into a pulse-skipping mode. Furthermore, detecting the right time for the change of modes can also introduce distortion during the transition. A way to overcome the transition problems, is to force the EWiRaC into a third mode of operation, which has not been discussed yet. In the third mode of operation, the EWiRaC operates like a standard boost converter, boosting the voltage up to above the maximum line peak voltage. As the boost switch, Q1, turns off, only one of either Q2 or Q3 is turned on forcing the voltage on the drain connection of the MOSFETs up to twice the output voltage, just like a normal boost converter. This will ensure that the duty-cycle will be about 50% during the transition. The time at which this mode is entered is not crucial as long as it is before the input voltage reaches the output voltage. The drawback of this approach, is that the inductor current ripple will be twice as large during the transition compared to the worst case condition before. The effects in terms of EMI has not been investigated. Despite the problems during the transition between the two modes, the performance in terms of efficiency of the converter is still very good. The worst case efficiency of the EWiRaC configuration shown in Fig. 9.1, is 94% (Fig.9.4). This configuration uses the flyback snubber shown in Fig. 8.16a, which increased the voltage rating of the switch Q1. Instead, a 600V FET was used (CoolMos : SPW47N60C3 [18]), with higher losses as a result.

Fig. 9.4. Efficiency of the peak current controlled EWiRaC. VIN = 90VAC

The distortion of the line current has little impact on the efficiencies. At nominal line voltage of 115VAC, the efficiency at full load is 95.6% and at 230VAC the efficiency is 96,5%. The peak current control scheme for the EWiRaC is still in its early phase, but development will continue in this area. Even though there are good alternatives, as will be shown in the next section, the peak current controlled PFC approach has some clear advantages when it comes to the interleaved EWiRaC approaches.

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9.4 Prototype 2: Average current mode control with level shifted carrier

9.4.1 Design considerations

Fig. 9.5. Block schematic of the average current controlled EWiRaC using level shifted carrier.

The peak current controlled EWiRaC, has some disadvantages regarding the transition between the two modes. The instant where VIN=VOUT has to be detected, and the peak current approach has trouble producing very small duty-ratios. These problems can be overcome by using average current mode control with level shifted carrier. To generate the error signal, a standard average current mode PFC controller is used, in this case the UCC3817 from Texas Instruments [37].

Fig. 9.6. a) Level shifted carrier approach. b) level shifted error voltage approach.

The two independent duty-cycles is generated by a dual PWM IC (TL1451) [37]. In the TL1451, the carrier is fixed for the two PWM circuits, so for practical reasons, the error signal is level shifted instead. Besides containing the carrier signal and the PWM

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comperator, the TL1451 also has two independent error amplifiers. These can be used for conditioning the error signal from the UCC3817. The carrier available in the TL1451 has a peak-to-peak voltage of 0.6V and is level shifted 1.4V. The error signal used to generate the duty-cycle for the voltage-source (dVS(t)), should be level shifted as much as the peak-to-peak carrier voltage (VBias = 0.6V). To prevent a dead zone during the transition, where both of the duty-cycles are inactive because of mismatch in the level shifted error signal, the VBias voltage should be reduced below the 0.6V. This will create an overlap where both duty-cycles will be active. The overlapping of duty-cycles will not result in excessive inductor ripple which is the case for the peak current controlled EWiRaC in the mode 3 operation discussed in the previous section.

Fig. 9.7. Simulated average current mode control with level shifted carrier and overlapping duty-cycles.

A dc/dc version of the EWiRaC configuration shown in Fig. 9.5, has been simulated to show the behavior of the inductor current during the transition. The schematic of the system can be found in Appendix C1. The simulation results are shown in Fig. 9.7 and Fig. 9.8.

Fig. 9.8. The inductor current during the transition where VIN exceeds VOUT. This view is a zoom of the marked area in Fig. 9.7.

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For more details on the circuit, see Appendix C1. The input voltage is increased above output voltage as shown in Fig. 9.7. The current waveform, is set to follow the input voltage as it would do in an ac/dc application. Using overlapping duty-cycles, secures a smooth transition. The "Zoom area" shown in Fig. 9.7, can be seen in Fig. 9.8, where a few samples of the inductor current is depicted during the transition where the input voltage exceeds the output voltage. The transition shown in Fig. 9.8, is comprised by 3 modes. Mode 1, is the charge mode, where the switch Q1 turns on. The di/dt of the inductor is very high since the maximum applied inductor voltage occurs in the mode. Mode 2 can be either a charge mode or a discharge mode. In this mode Q1 is turned off, and Q2 and Q3 is turned on. If the input voltage is below the output voltage, the inductor di/dt will be negative and the mode is a discharge mode. If the inductor di/dt is positive, the mode is a charge mode. The exact time of transition can be determined from the inductor di/dt in this mode, as shown in Fig. 9.8. The last mode, mode 3, is a discharge mode where either Q2 or Q3 is turned of.

9.4.2 Performance of the practical implementation The full schematic of the EWiRaC configuration shown in Fig. 9.5 can be found in Appendix C2. The important power components are listed in table 9.1. The experimental EWiRaC was first tested as a dc-dc converter. Fig. 9.9 shows the drainsource voltage of the switch Q1 (the boost switch). The input voltage is 260VDC, which is higher than the output voltage, so in this mode the switch Q1 is turned off all the time, and Q2 and Q3 is PMW modulated. The voltage on the drain of Q1 (and Q2,Q3) alternates between the output voltage and twice the output voltage, as expected.

Fig. 9.9. Drain-source voltage of the switch, Q1. The bottom plateau of the waveform is equal to the output voltage of 185VDC. The upper plateau is equal to twice the VOUT.

The error signal to the dual PWM driver is shown in Fig. 9.10 and Fig. 9.11 for an ac input voltage of 90VAC and 230VAC.

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Fig. 9.10. Line voltage (upper trace) VAC = 90V. Error signal (bottom trace) generated by the UCC3817.

Fig. 9.11. Line voltage (upper trace) VAC = 230V. Error signal (bottom trace) generated by the UCC3817.

In the practical implementation, the output from the dual PWM driver, had to be inverted to maintain the negative feedback loop. Therefore, the error signal is not varying between 1.4V and 2V as we would have expected for the error signal determining the duty-cycle (dB(t)) of the switch Q1. To maintain the proper operation of the circuit, the error signal to generate dB(t), has to be dc biased. The dc bias was designed to give an overlap of approximately 10% to ensure a smooth inductor current transition. Because of the inversion after the dual PWM driver, the error signal to generate the voltage-source duty-cycle is within the carrier peak-to-peak voltage. We would expect the error signal to vary with about twice the carrier peak-to-peak voltage, but the inductor current goes into DCM at about 130V at full load and VAC=230V. This minimizes the error voltage excursion downwards. Fig. 9.12. shows the input current and voltage at nominal low line voltage (115VAC) and full output power.

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Fig. 9.12. Input voltage and current of the experimental converter of Fig. 9.5. VAC = 115V.

Besides the fact the the input current is almost sinusoidal and in phase with the line voltage (PF=0.999), there are two noticeable distortion phenomenon of the line current. At the zero crossing of the line voltage we see cusp distortion of the current followed by an overshoot. The cusp distortion is typically because of the di/dt limitations imposed by the inductor, but in this case the inductor is not the limiting factor. The inductor current should be able to follow the reference current, when the input voltage reaches 0.6V (not including bridge rectifier voltage drop). This should therefore not give rise to the amount of distortion encountered. Because the control system is made of several control ICs, compromises in the interfacing between these, have resulted in that some of the features, like soft-start, have been lost. This can of course be implemented but for the prototype, the problems at start-up has been fixed by limiting the maximum duty-cycle of the switch Q1. This is the main reason for the cusp distortion. The other distortion phenomenon encountered, is the dither at the two extremes of the waveform. The mode with the overlapping duty-cycles is reached near the top of the 115VAC line voltage. This should in theory and as seen with the simulation, not give rise to any problems. One explanation is that the transition generates noise that interfere with the control system. As will be shown later, the PCB design created was not very noise immun. The harmonic content of the current shown in Fig. 9.12, is very moderate, and compliance with the regulations is not a problem. For the sake of completeness, the harmonic analysis of the current of Fig. 9.12, is shown in Fig. 9.13.

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Fig. 9.13. Current harmonics in the input current of the experimental converter in Fig. 9.5. VAC = 115V.

At the extreme of the low line range, 135VAC (Fig. 9.14), the converter operates in the overlapping mode a larger portion of time. Besides the dither distortion, the line current distortion caused by the change of mode is moderate.

Fig. 9.14. Input current of the experimental converter in Fig. 9.5. VAC = 135V.

The line current for VAC = 185V is shown in Fig. 9.15. The dither distortion at this input voltage is gone, and the transition between the two modes can be seen as a little glitch in the current. The line current is shifted a little to the left, so the transition does not occur at the same current level.

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Fig. 9.15. Input current of the experimental converter in Fig. 9.5. VAC = 185V.

The drain voltage of Q1,Q2 and Q3 referenced to ground, is shown in Fig. 9.16. The figure illustrates the different modes that the EWiRaC, shown in Fig. 9.5, goes through at high line.

Fig. 9.16. Drain voltage of Q1, Q2 and Q3 referenced to ground. VAC = 185V, VOUT = 185V and POUT = 500W.

In the first mode, the switches Q2 and Q3 are turned on and the switch Q1 is PWM modulated. This interval is located around the zero crossing of the line and up until the overlapping duty-cycle mode starts. In the overlapping duty-cycle mode, the drain voltage on the switches varies from zero to VOUT to twice VOUT. In the last mode, the switch Q1 is turned off all the time and the drain voltage is switched between VOUT and twice VOUT. At the nominal high-line voltage, 230VAC, the noise problems reoccur. The current glitch at the transition between the modes, can easily be recognized, and besides the cusp distortion, distortion around the line peak voltage occur. It is most likely a noise generated phenomenon. The duty-cycle signal for the switch Q1 is triggered, and turns on Q1. This results in a high gain of the inductor current which causes instability in the current loop. A -148-

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proper layout and an adjustment of the current loop should take care of these problems.

Fig. 9.17. Input voltage and current of the experimental converter of Fig. 9.5. VAC = 230V.

The harmonic content of the line current is still very low as can be seen from the harmonic analysis shown in Fig. 9.18.

Fig. 9.18. Current harmonics in the input current of the experimental converter in Fig. 9.5. VAC = 230V.

The efficiency of the EWiRaC at low line is shown in Fig. 9.19 as a function of the output power.

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Fig. 9.19. Measured efficiency of the EWiRaC in the low-line range.

The efficiency at 90VAC and full power is 94.8% which is very close to the predicted by the theoretical calculations of table 9.1. In order to see the effect of the voltage-source on the losses, a wire was placed across the voltage-source to short circuit it. The losses were reduced with 4W at full power which is slightly below the calculated value. The theoretical calculated efficiency is very close to the measured efficiency but this does not mean that calculated values are absolutely correct. Different temperatures of the component will influence the losses. The purpose of the efficiency calculations was to determine whether the design was competitive with the standard boost converter. Besides the relative high efficiency achieved at 90VAC, it is remarkable, that the efficiency of the 135VAC is not better than the efficiency at 115VAC. The reason for this is the increased losses that the overlapping duty-cycle mode imposes on the converter. This overlapping period is going on for about 2/5 of the time (see Fig. 9.12). The efficiency at 115VAC of 96.15% is actual higher than the efficiency at 135VAC (96%). This is atypical compared to a standard boost converter, but has no significance, as long as the worst case efficiency is not sacrificed.

Fig. 9.20. Measured efficiency of the EWiRaC in the high-line range.

The efficiency for the high-line range, is shown in Fig. 9.20. In this range, there is a relative small difference in the efficiencies at full power (96.5% - 97%). During the interval where the input voltage is above the output voltage, power is transferred to the output both in the on and the off periods of the voltage-source duty-cycle. At 185VAC, a larger portion of the power is supplied to the output during the on period, where the voltage-source is a short circuit. As the input voltage increases, the input current decreases, minimizing the effects of -150-

Experimental results

the voltage-source resistance.

Fig. 9.21. Measured efficiency of the EWiRaC at full output power, 500W, as a function of the line voltage.

The efficiency as a function of the line voltage at full output power, is shown in Fig. 9.21. As explained earlier, the efficiency at 135VAC is slightly lower because of the overlapping duty-cycle mode. Other wise, the intended improved efficiency at low-line has been achieved with approximately 1-2 percentage points, dependent on the implementation of the inrush current limiter. The high line efficiency does not seem to suffer from the EWiRaC operation mode. In all of the efficiency measurements, the auxiliary supply has not been accounted for, and was measured to about 2W. Further more, as can be seen in Fig. 9.21, the input voltage range was reduced to 255VAC, because of the noise induced instability at the high input line. This, on the other hand, does not have any consequences for the achieved performance.

9.5 Summary The efficiency improvements obtained using the EWiRaC compared to a standard boost converter, has been estimated to be in the range of 1-2% percentage points, mostly dependent on how efficient the inrush current limiter is implemented. This means, that a state-of-the-art implementation of a hard-switched CCM boost PFC for the universal line range, should achieve efficiencies in the range of 92.5%-93.5% whereas the EWiRaC should achieve an efficiency of about 94.5% which reduces the power losses with about 15% to 30%. In order to verify the high efficiency capability of the EWiRaC, the results obtained on two prototypes have been reported. The first prototype was implemented using standard peak current mode control. As predicted, in chapter 8, the transition between the two modes causes problems. The effect of not using the improved slope compensation scheme is clearly visible in the line current waveform. Besides the problems with the slope compensation, other factors were pointed out, such as the problems that can occur when narrow duty-cycles are demanded by the peak current mode controller. A way to solve these problems, would be to go into the standard boost mode in a narrow interval around the mode change. Thereby, the converter -151-

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would operate with an effective duty-cycle close to 50% assuming that the output voltage is selected in the middle of the line range. Despite the above mentioned problems, the efficiency of the converter was relatively good (94%). For the main switch (Q1), a different type MOSFET with a voltage rating of 600V was used, which was not as good as the one listed in table 9.1. The second prototype was implemented using the average current mode control with level shifted carrier. Besides the experimental converter, simulated results, showing the behavior of the inductor current during the mode change, has also been presented. The worst case efficiency reached 94.8%, thereby verifying the predicted quality of the EWiRaC as a high efficient wide input range converter.

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Chapter 10

Conclusion The overall goal of this thesis has been to provide the knowledge and the understanding that can lead to an increased efficiency for ac/dc power systems complying with EN61000-3-2 in wide input range applications. The first part of the thesis focus on the different approaches that can be taken to provide the necessary ac/dc conversion for compliance with the regulations. For a majority of the research in ac/dc conversion, the focus has been on integrating the PFC-unit into the existing dc/dc converter and one of the tasks in this thesis has been to analyze the effects on the conversion efficiency by doing this. The two major groups of alternative PFC solutions have been recognized as the Reduced Power Processing approach and the Single-Stage approach. In order to investigate the performance of the different approaches, the basic converter topologies, both isolated and non-isolated, have been analyzed in terms of component stress, in chapter 5. Several important observations were made in this process. The two most important observations with direct influence on how the different PFC approaches perform are listed below.


Non-isolated buck and boost type converters are low component stress converters compared to the buck-boost type converters.




Isolated buck and boost converters have increased semiconductor component stress, and exhibits a dramatically increase in these stresses when exposed to input voltage variations.

In the Reduced Power Processing approach a typically way of evaluating the performance of this approach, is to calculate the amount of power processing. In this evaluation the TwoStage approach is used as the worst case approach with its two-times of power processing, calculated as one time for the PFC pre-converter, and one time for the isolated dc/dc converter. As shown in chapter 6, the amount of power processed is a very poor indicator of how efficient the conversion is performed and in all practical cases, the Reduced Power Processing approaches expose the components to a higher stress compared to the Two-

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Stage approach. The reason for this, is that the Reduced Power Processing approach has to make use of high component stress converters (buck-boost derived) and/or isolated converters in high stress configurations. The basic conclusion is: It is not how much, but in what way the power is processed, that is the determining factor on the components stresses and thereby the efficiency. The Single-Stage approach is comprised of an isolated dc/dc converter with means to shape the input current so that compliance with the regulations is possible. The output voltage is regulated with a fast control loop, and the Single-Stage approach does not rely on a separate control system to regulate the input current. In order to decouple the pulsating input power, a large bulk capacitor serves as the energy storage. Since there is only one control system regulating the output voltage, the storage capacitor voltage is not directly regulated. This voltage depends on the input/output power balance, and will typically vary proportional to the line voltage. This means, that for a 3:1 ac input-voltage range, the input to the isolated dc/dc converter will also be exposed to a 3:1 voltage range. Therefore, as shown in chapter 6, the Achilles heal of the Single-Stage approach, is the isolated dc/dc converter-part. The varying input voltage will expose the power semiconductors to excessive stress resulting in the Two-Stage approach to be more efficient. For the best Single-Stage configurations, the approach becomes competitive with the Two-Stage approach when the input voltage range is reduced to about 1.3:1. This means that for very narrow voltage range applications, the best of the Single-Stage approaches might be a reasonable solution. For wide input applications, the Two-Stage approach, using a boost PFC, is the superior approach compared to the Reduced Power Processing approach and the Single-Stage approach. Even though the boost converter is a low component stress converter, the voltage variation is still the limiting factor on the efficiency. Since the boost converter is only able to produce an output voltage larger than the maximum line peak voltage, the worst case situation for the converter is at low line, where the step-up ratio is maximized. Other PFC pre-converters exists that are capable of producing an output voltage below the maximum line peak voltage. The SEPIC converter is capable of this, but because the converter is a buck-boost derived converter, the component stresses are high with reduced efficiency as a consequence. Besides the lower output voltage, the SEPIC is also capable of controlling the inrush current, which is something that the boost converter is unable to do, unless extra circuitry is provided. Switchable topologies like the two-switch buck-boost is a better approach compared to the SEPIC. This converter is able to change the topology from being a boost type to a buck type according to the instantaneous value of the line voltage. If the line voltage is below the output voltage the converter works in the boost mode and in the buck mode if the line voltage is above the output voltage. The most significant drawbacks of this approach is, that all the input power has to flow through the buck switch, and that in the buck mode, the input current becomes highly discontinuous, increasing the EMI filtering requirements. All of the above investigations, considerations and observations, have lead to the construction of a new type of PFC converter that addresses the problems with the boost converter but retain its efficient conversion properties.

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Conclusion

This new converter has been named Efficient Wide Range Converter (EWiRaC) and possesses the following features.





High efficiency Output voltage below the line peak voltage Continuous input current (low EMI-filter requirements) Inrush-current limiting

Several versions of the EWiRaC have been presented, all which are based on an approach called the series voltage-source approach. This approach makes it possible to effectively reduce the input voltage range with a factor of two. The EWiRaC has been compared with both the two-switch buck-boost and the standard boost converter. The results of this comparison showed, that the EWiRaC potentially would be able to achieve higher efficiency compared to both the two-switch buck-boost, and the standard boost converter. To verify the performance of the EWiRaC, two prototypes have been presented using different control schemes. The EWiRaC was designed for the universal line range with an output voltage of 185VDC capable of 500W output power. The peak current controlled EWiRaC exhibited problems in the region where the mode change occurs resulting in distortion and large oscillations in the input current. Despite the less successfully implemented control scheme, the efficiency at 90VAC and full power reached 94%. The second prototype used average current mode control with level shifted carriers. Besides some noise-related problems at voltages approaching the upper limit of the input voltage, this control scheme exhibits an almost unnoticeable mode change. Furthermore, the efficiency reached with this prototype was 94,8% and for the full line range, the worst case efficiency was in the range of 94,8%-97%. For a boost PFC converter using the same power components, the efficiency will be at least 1-2 percentage points lower, which translates into a reduction of the power losses of 15%30% by using the EWiRaC. The complexity of the EWiRaC is relatively large, mainly because of the associated control circuitry. Since the EWiRaC is a new invention, commercially control ICs are not available that collects all of the control features into a single package. When this becomes a reality, the complexity will reduce considerable.

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References (thesis) In the thesis, two different reference systems are used. In the first system, the references are number consecutively after when they appear in the thesis. The second system covers the references in the database. These references uses the database reference number with "db" added in front. The database reference list is called "References (database)" and can be found in the following section. [1]

K. Billings, "Switchmode power supply handbook",second edition, McgrawHill 1999.

[2]

Measurements on standard off-the-shelf power supplies. Truls Andersen, Powerlab (www.powerlab.dk) and Lars Petersen, Technical University of Denmark, 2000.

[3]

O. Garcia, J.A. Cobos, R. Prieto, P. Alou and J. Uceda, "Simple ac/dc converters to meet IEC 1000-3-2", APEC 2000, pp. 487-493.

[4]

N. Mohan, T.M. Undeland, W.P. Robbins," Power Electronics", 2nd edition, 1995 Wiley & Sons.

[5]

R.W. Erickson, D. Maksimovic, "Fundamentals of Power Electronics", 2nd edition, 2001 Kluwer Academic Publishers.

[6]

Villegas, P.J.; Sebastian, J.; Hernando, M.; Nuno, F.; Martinez, J.A.; Power Electronics, IEEE Transactions on , Volume: 15 Issue: 5 , Sept. 2000 pp.813 -819.

[7]

O. Garcia, J.A. Cobos, R. Prieto, P. Alou and J. Uceda, "A new approach for single stage AC/DC power factor correction converters with an improved energy processing", PESC 1998, pp. 1061-1067.

[8]

E. Rodriguez, O. Garcia, J.A. Cobos, J. Arau and J. Uceda, "A single-stage rectifier with PFC and fast regulation of the output voltage", PESC 1998, pp. 1642-1648.

[9]

O. Garcia, P. Alou, J.A. Oliver, J.A. Cobos, J. Uceda and S. Ollero, "AC/DC converters with tight output voltage regulation and with a single control loop", APEC 1999, pp. 1098-1104.

[10]

Lars Petersen, "Advantages of using a two-switch forward in single-stage power factor corrected power supplies", INTELEC 2000, pp. 325-331.

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[11]

A. Fernandez, A. Ferreres, P. Villegas, J. Sebastian and L. Alvarez, "Size comparison between a half bridge converter with an AICS and a two-stage boost converter operating in a narrow input voltage range", PESC 2001, pp. 1793-1798.

[12]

L. Petersen and M. Andersen, "Two-stage power factor corrected power supplies: The low component-stress approach", APEC 2002, pp. 1195-1201

[13]

Christian Wolf, "Ensrettere med sinusformet netstrøm", Ph.d.-thesis, Institut for Automation, Technical University of Denmark, 1995.

[14]

M.A.E. Andersen, "Fast prediction of differential mode noise input filter requirements for flyback and boost unity power factor converters", EPE 1997, pp. 2.806-2.809.

[15]

Bruce Carsten, “Converter component load factors; A performance limitation of various topologies”, PCI 1988, Munich

[16]

J. Chen, D. Maksimovic, R. Erickson, "A new low-stress buck-boost converter for universal-input PFC applications", APEC 2001, pp. 343-349.

[17]

I. Lindroth, P. Melchert, T. Sahlstrom, "Methods of improving efficiency in wide input range boost converters at low input voltage", Intelec proc. 2000, pp. 424-431.

[18]

[www.infineon.com]

[19]

Correspondence with Dr. Gerald Deboy, head of High voltage MOS development, Infineon Technologies AG, Power management & supplies.

[20]

M.A.E. Andersen et al., "Basic power electronics" (in Danish), 1997, Dep. of Automation, Technical University of Denmark.

[21]

O. Garcia, J.A. Cobos, P. Alou, R. Prieto, J. Uceda, S. Ollero, “A new family of single stage AC/DC power factor correction converters with fast output voltage variation”, PESC Proc. 1997, pp. 536-542

[22]

A. J. Calleja, J. M. Alonso, J. Ribas, E. L. Corominas, M. Rico-Secades, J. Sebastian, "Design and experimental results of an input-current-shaper based electronic ballast", IEEE Transactions on Power Electronics, VOL. 18, NO. 2, March 2003, pp.547-557

[23]

J.G. Kassakian et al. "Principles of Power Electronics", Addison-Wesley 1992.

[24]

www.vicr.com

[25]

www.vicr.com/products/datasheets/ds_vi-ham.pdf

[26]

J. Sebastian, A. Fernandez, P.J. Villegas, M.M. Hernando, J.M. Lopera, "Improved active input current shapers for converters with symmetrically

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driven transformer", IEEE Transactions on Industry Applications, VOL. 37, O. 2, March 2001, pp.592-600 [27]

J. Chen, "Topologies and control of low harmonic rectifiers", Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Colorado at Boulder. 2002.

[28]

De Aragao Filho, W.C.P.; Barbi, I.,"A comparison between two current-fed push-pull DC-DC converters-analysis, design and experimentation", INTELEC 1996, pp. 313-320.

[29]

C. Peng, M. Hannigan, O. Seiersen, "A new efficient high frequency rectifier circuit", Proceedings of High Frequency Power Conversion 1991, pp. 236-243.

[30]

[www.st.com]

[31]

Unitrode power supply design seminar, SEM-1000, topic 1: J. Noon, "A 250kHz,500W power factor correction circuit employing zero voltage switching".

[32]

Elektronik Ståbi, 7. udgave, Teknisk Forlag A/S 1995. ISBN 87-571-1481-1

[33]

D. M. Mitchell, "DC-DC switching regulator analysis", DMMitchell consultants 1992.

[34]

Lars Petersen, Robert W. Erickson, "Reduction of voltage stresses in buck-boost-type power factor correctors operated in boundary conduction mode", APEC 2003, pp. 664-670

[35]

Lars Petersen, "Input-current shaper based on a modified SEPIC converter with low voltage stress",PESC 2001, pp. 666-671

[36]

www.irf.com

[37]

www.ti.com

[38]

P.C. Todd, "Snubber cicuits: Theory, design and application", Unitrode design seminar, SEM1000, P4.

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References (database) [db1]

Laszlo Balogh, "Power-Factor Correction with Interleaved Boost Converters in Continuous-Inductor-Current Mode", APEC 1993, pp. 168-174

[db2]

P. Tenti, C. Licitra, G. Spiazzi, B. Fabiano, L. Rossetto, "Fast-Response HighQuality Rectifier With Sliding-Mode Control", APEC 1993, pp. 175-181

[db3]

Roberto Martinez, Prasad N. Enjeti, "A High Performance Single Phase AC to DC Rectifier with Input Power Factor Correction", APEC 1993, pp. 190-195

[db4]

Eric X. Yang, Yimin Jiang, Fred C Lee, Guichao Hua, "Isolated Boost Circuit for Power Factor Correction", APEC 1993, pp. 196-203

[db5]

Jih-Sheng Lai, Daoshen Chen, "Design Consideration for Power Factor Correction Boost Converter Operating at the Boundary of Continous Conduction Mode and Discontinuous Conduction Mode", APEC 1993, pp. 267-273

[db6]

G. K. Dubey, M. S. Dawande, "Programmable Input Power Factor Correction Method For Switch Mode Rectifiers", APEC 1993, pp. 274-280

[db7]

James J. Spangler, Anup K. Behera, "A Comparison Between Hysteretic and Fixed Frequency Boost Converters Used For Power Factor Correction", APEC 1993, pp. 281-286

[db8]

Yimin Jiang, Wei Tang, Fred C Lee, Guichao Hua, "A Novel Single-Phase Power Factor Correction Scheme", APEC 1993, pp. 287-292

[db9]

Wei Tang, Yimin Jiang, Guichao Hua, Fred C Lee, I. Cohen, "Power Factor Correction With Flyback Converter Employing Charge Control", APEC 1993, pp. 293-298

[db10]

William F. Yadusky, Arthur W. Kelley, "Rectifier desing for minimum line current harmonics and maximum power factor", APEC 1989, pp. 13-22

[db11]

G. Joos, P. D. Ziogas, M. Kazerani, "Programmable input powerfactor correction methods for single phase diode rectifier circuits", APEC 1990, pp. 177-184

[db12]

Mehmet K. Nalbant, "Power factor calculations and measurements", APEC 1990, pp. 543-552

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High Efficient Rectifiers

[db13]

S. A. Oliveira da Silva, Ivo Barbi, "Sinusoidal line current rectification at unity power factor with boost quasi-resonant converters", APEC 1990, pp. 553-562

[db14]

C. D. Manning, K. A. Amarasinghe, "A resonance power supply that provides dynamic power factor correction in capacitor input off-line converters", APEC 1990, pp. 563-570

[db15]

JHR Enslin, GL Van Harmelen, "Real-time, dynamic controller for dynamic power filters in supplies with high contamination", APEC 1990, pp. 571-578

[db16]

Mark A. Geisler, "Predicting power factor and other input parameters for switching power supplies", APEC 1990, pp. 579-587

[db17]

William F. Yadusky, Arthur W. Kelley, "Phase-controlled rectifier line-current harmonics and power factor as a function of firing angle and output filter inductance", APEC 1990, pp. 588-597

[db18]

Michael Madigan, Robert Erickson, Sigmund Singer, "Design of a simple highpower-factor rectifier based on the flyback converter", APEC 1990, pp. 792-801

[db19]

Robert L. Steigerwald, Mustansir H. Kheraluwala, Michael J. Schutten, "Characteristics of load resonant converters operated in a high power factor mode", APEC 1991, pp. 5-16

[db20]

Michael D. Moore, Arthur W. Kelley, James L. Nance, Mohab A. Hallouda, "Near unity power factor single phase AC to DC converter using a phase controlled rectifier", APEC 1991, pp. 387-392

[db21]

James J. Spangler, Anup K. Behera, Badruzzaman Hussain, "Electronic fluorescent ballast using a power factor correction technique for loads greater than 300 W", APEC 1991, pp. 393-399

[db22]

R. Krishnan, Geunhie Rim, "AC to DC power conversion with unity power factor and sinusoidal input current", APEC 1991, pp. 400-406

[db23]

M. S. Elmore, W. A. Peterson, S. D. Sherwood, "A power factor enhancement circuit", APEC 1991, pp. 407-414

[db24]

Jih-Sheng Lai, Tom Key, Don Hurst, "Switch-mode power supply power factor improvement via harmonic elimination methods", APEC 1991, pp. 415-422

[db25]

Richard Hoft, Soonwook Hong, Ray Hudson, "Modeling and simulation of a digitally controlled active rectifier for power conditioning", APEC 1991, pp. 423-429

[db26]

Carlos Alberto Canesin, Ivo Barbi, "A unity power factor multiple isolated outputs switching mode power supply using a single switch", APEC 1991, pp. 430-436

[db27]

James M. Simonelli, David A. Torrey, "Input filter design considerations for boost-derived high power-factor converters", APEC 1992, pp. 186-192

-162-

[db28]

Laszlo Balogh, Richard Redl, "RMS, DC, peak, and harmonic currents in highfrequency power-factor correctors with capacitive energy storage", APEC 1992, pp. 533-540

[db29]

Roger J. King, Douglass B. Robless, "A 1-kW unity-power-factor rectifier with isolation and fault protection", APEC 1992, pp. 541-548

[db30]

John C. Salmon, "Circuit topologies for single-phase voltage-doubler boost rectifiers.", APEC 1992, pp. 549-556

[db31]

David M. Otten, Martin F. Schlecht, Brett A. Miwa, "High efficiency power factor correction using interleaving techniques", APEC 1992, pp. 557-568

[db32]

Bonanni Ignazio, "High power factor resonant rectifier for UPS systems", APEC 1992, pp. 594-597

[db33]

A. R. Prasad, S. Manias, P. D. Ziogas, "A new active power factor correction method for single-phase buck-boost AC-DC converter", APEC 1992, pp. 814820

[db34]

Harold Seidel, "A power factor tuned class D converter", PESC 1988, pp. 10381042

[db35]

Kwang-Hwa Liu, Yung-Lin Lin, "Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters", PESC 1989, pp. 825-829

[db36]

Sigmund Singer, "The application of the "Loss-Free Resistors" in power processing circuits", PESC 1989, pp. 843-846

[db37]

James B. Williams, "Design of feedback loop in unity power factor AC to DC converter", PESC 1989, pp. 959-967

[db38]

G. Verghese, J. Thottuvelil, A. Heyman, K. Mahabir, "Linear averaged and sampled data models for large signal control of high power factor AC-DC converters", PESC 1990, pp. 372-381

[db39]

Chen Zhou, Raymond B. Ridley, Fred C Lee, "Design and analysis of a hysteretic boost power factor correction circuit", PESC 1990, pp. 800-807

[db40]

J. A. Cobos, J. Sebastian, J. Uceda, J. Arau, F. Aldana, "Improving power factor correction in distributed power supply systems using PWM and ZCS-QR SEPIC topologies", PESC 1991, pp. 780-791

[db41]

Robert L. Steigerwald, Mustansir H. Kheraluwala, Ramachandran Gurumoorthy, "A fast response high power factor converter with a single power stage", PESC 1991, pp. 769-779

[db42]

Do-Hyun Jang, Jong-Soo Won, Gyu-Ha Choe, "Asymmetrical PWM method for AC chopper with improved input power factor", PESC 1991, pp. 838-845

[db43]

Karel Jezernik, Franc Mihalic, Miro Milanovic, Uros Milutinovic, "Single phase

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High Efficient Rectifiers

unity power factor correction circuits with coupled inductance", PECS 1992, pp. 1077-1082 [db44]

J. A. Cobos, J. Sebastian, J. Uceda, P. Gil, F. Aldana, "Analysis of the zerocurrent-switched quasiresonant converters used as power factor preregulators", PESC 1992, pp. 1052-1060

[db45]

Gyu-Ha Choe, Dong Y. Huh, Hack S. Kim, "New group of ZVS PWM converters operable on constant frequency and its application to power factor correction circuit", PESC 1992, pp. 1441-1446

[db46]

I. Batarseh, C. Q. Lee, Rui Liu, "A unified approach to the design of resonant power factor correction circuits", PESC 1992, pp. 181-188

[db47]

Bo H Cho, Fakhralden A Huliehel, Fred C Lee, "Small-signal modelling of the single-phase boost high power factor converter with constant frequency control", PESC 1992, pp. 475-482

[db48]

Andre S Kislovski, Richard Redl, "Source impedance and current-controlled loop interaction in high-frequency power-factor correctors", PESC 1992, pp. 483-488

[db49]

Toshiyuki Sugiura, Takashi Yamashita, Hisahito Endo, "A high-power-factor buck converter", PESC 1992, pp. 1071-1076

[db50]

Rui Liu, C. Q. Lee, I. Batarseh, "Resonant power factor correction circuits with resonant capacitor-voltage and inductor-current-programmed controls", PESC 1993, pp. 675-680

[db51]

Domingos S.L. Simonetti, J. Uceda, J. Sebastian, "A small-signal model for sepic, cuk and flyback converters as power factor preregulators in discontinous conduction mode", PESC 1993, pp. 735-741

[db52]

Sam Ben-Yaakov, Gregory Ivensky, Alexander Abramovizt, "A resonant power factor conditioner", PESC 1993, pp. 995-1001

[db53]

Widodo Sulistyono, Prasad N. Enjeti, "A series resonant AC-to-DC rectifier with high-frequency isolation", APEC 1994, pp. 397-403

[db54]

L C de Freitas, A V da Costa, C H. G. Treviso, "A new ZCS-ZVS-PWM boost converter with unit power factor operation", APEC 1994, pp. 404-410

[db55]

Fred C Lee, Guichao Hua, R Watson, "Characterization of an active clamp flyback topology for power factor correction applications", APEC 1994, pp. 412418

[db56]

Ed Deng, Slobodan Cuk, "Single stage, high power factor, lamp ballast", APEC 1994, pp. 441-449

[db57]

Y Nishida, T Haneyoshi, E Ohtsuji, O Miyashita, "High power factor PWM rectifiers with an analog pulse-width predictor", APEC 1994, pp. 563-568

[db58]

Esam Ismail, Robert Erickson, Michael Madigan, "Integrated high quality

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rectifier-regulators", PESC 1992, pp. 1043-1051 [db59]

J. A. Cobos, J. Uceda, J. Sebastian, P. Gil, "The determination of the boundaries between contintinuous and discontinuous conduction modes in PWM DC-to-DC converters used as power factor preregulators", PESC 1992, pp. 1061-1070

[db60]

Mila M. Jovanovic, Dan M.C. Tsang, Fred C Lee, "Reduction of voltage stress in integrated high-quality rectifier-regulators by variable-frequency control", APEC 1994, pp. 569-575

[db61]

Richard Redl, Jiatian Hong, Iftikhar Khan, Dragan Maksimovic, Robert Erickson, "Half-cycle control of the parallel resonant converter operated as a high power factor rectifier", APEC 1994, pp. 556-562

[db62]

Sarma Mulukutla, C Michael Hoff, "Analysis of the instability of PFC power supplies with various AC sources", 1994 1994, pp. 696-702

[db63]

Brian P Erisman, Laszlo Balogh, "Reducing distortion in peak-current-controlled boost power-factor correctors.", APEC 1994, pp. 576-583

[db64]

John O'Connor, John Bazinet, "Analysis and design of a zero voltage transition power factor correction circuit", APEC 1994, pp. 591-597

[db65]

Dragan Maksimovic, "Design of the clamped-current high-power-factor boost rectifier", APEC 1994, pp. 584-590

[db66]

Laszlo Balogh, Richard Redl, "Design considerations for single-stage isolated power-factor-corrected power supplies with fast regulation of the output", APEC 1995, pp. 454-458

[db67]

John C. Salmon, "Performance of a 1-phase buck-boost rectifier using two coupled windings and a spilt dc-rail output voltage", APEC 1995, pp. 427-433

[db68]

Michael T Zhang, Mila M. Jovanovic, Fred C Lee, Yimin Jiang, "Single-phase three-level boost power factor correction converter", APEC 1995, pp. 434-439

[db69]

L C de Freitas, Joao L Andres, Adriano Alves Perira, "A high power factor operating self-resonant-PWM forward converter", APEC 1995, pp. 440-446

[db70]

Milivoje Brkovic, Slobodan Cuk, "Novel single-stage AC-to-DC converters with magnetic amplifiers and high power factor", APEC 1995, pp. 447-453

[db71]

Dragan Maksimovic, Robert Erickson, "Universal-input, high-power-factor, boost doubler rectifiers", APEC 1995, pp. 459-465

[db72]

Richard Redl, Laszlo Balogh, "Power-factor correction in bridge and voltagedoubler rectifier circuits with inductors and capacitors", APEC 1995, pp. 466472

[db73]

DaFeng Weng, S. Yuvarajan, "Constant-switching-frequency AC-DC converter using second-harmonic-injected PWM", APEC 1995, pp. 642-646

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High Efficient Rectifiers

[db74]

Yungteak Jang, Dragan Maksimovic, Robert Erickson, "Nonlinear-carrier control for high power factor boost rectifiers", APEC 1995, pp. 635-641

[db75]

John C. Salmon, "Circuit topologies for pwm boost rectifiers operated from 1phase and 3-phase ac supplies and using either single or split dc rail voltage outputs", APEC 1995, pp. 473-479

[db76]

V. Belaguli, A K.S. Bhat, "Operation of LCC-type parallel resonant converter as a low harmonic rectifier", APEC 1996, pp. 131-137

[db77]

D. Balocco, C. Zardini, "The half-wave quasi-resonant ZCS flyback converter as an automatic power factor preregulator : an evaluation", APEC 1996, pp. 138144

[db78]

M. S. Elmore, "Input current ripple cancellation in synchronized, parallel connected critically continuous boost converters", APEC 1996, pp. 152-158

[db79]

Dragan Maksimovic, Carlos Oliveira, "Zero-current-transition converters for high-power-factor AC/DC applications", APEC 1996, pp. 159-165

[db80]

P. P. Mok, C. S. Moo, "Multi-resonant boost converter as active filter for power factor correction", APEC 1996, pp. 166-171

[db81]

Praveen Jain, Gerry Moschopoulos, G. Joos, "Practical design considerations for a zero-voltage switched power factor correction converter", APEC 1996, pp. 172-178

[db82]

Chin-Yuan Hsu, Horng-Yuan Wu, "A new single-phase active power filter with reduced energy storage capacitor", PESC 1995, pp. 202-208

[db83]

L. Rossetto, P. Mattavelli, G. Spiazzi, "Power factor preregulators with improved dynamic response", PESC 1995, pp. 150-156

[db84]

Ned Mohan, Franz C. Zach, Girish R Kamath, Johann W Kolar, "Self-adjusting input current ripple cancellation of coupled parallel connected hysteresiscontrolled boost power factor correctors", PESC 1995, pp. 164-173

[db85]

John S. Glaser, Arthur F. Witulski, "Desing issues for high power factor AC-DC converter systems", PESC 1995, pp. 542-548

[db86]

W. Shireen, G. Arun, Prasad N. Enjeti, "Improved active power factor correction circuit using a zero voltage switching boost converter", PESC 1995, pp. 701-706

[db87]

A. Kandianis, S. Manias, G. Kostakis, "Novel boost converter topologies with zero switching losses for DC-DC and AC-DC applications", PESC 1995, pp. 707-713

[db88]

J. Uceda, J. Sebastian, C. Aguilar, F. Canales, "An integrated charger/discharger with power factor correction", PESC 1995, pp. 714-719

[db89]

Milivoje Brkovic, Slobodan Cuk, "Anovel single stage AC-to-DC full-bridge converter with magnetic amplifiers for input current shaping", PESC 1995, pp.

-166-

990-995 [db90]

J. R. Pinheiro, H. A. Grundling, D. L.R. Vidor, "Dual output three-level boost power factor correction converter with unbalanced loads", PESC 1996, pp. 733739

[db91]

M. H.L. Chow, C. K. Tse, "Single stage high power factor converter using the Sheppard-Taylor topology", PESC 1996, pp. 1191-1197

[db92]

Xiao-Ming Yuan, Wei-Xun Lin, Laszlo Balogh, Jin-Fa Zhang, Hong-Ying Wu, "Single-phase unity power factor current-source rectification with buck-type input", PESC 1996, pp. 1149-1154

[db93]

Konrad Mauch, Jing Wang, William G. Dunford, "A fixed frequency, fixed duty cycle boost converter with ripple free input inductor current for unity power factor operation.", PESC 1996, pp. 1177-1183

[db94]

Ivo Barbi, Grover V. Torrico Bascope, ""Isolated flyback-current-fed push-pull converter for power factor correction"", PESC 1996, pp. 1184-1190

[db95]

J. A. Ferreira, M van der Berg, "A family of low EMI, unity power factor correctors", PESC 1996, pp. 1120-1127

[db96]

J. Uceda, Domingos S.L. Simonetti, J. A. Cobos, J. Sebastian, "Analysis of the conduction boundary of a boost PFP fed by universal input", PESC 1996, pp. 1204-1208

[db97]

Y. Murai, K. Kamiya, M. Matsubara, "Soft-switched single-phase AC/DC converter circuit with sinusoidal input-current", PESC 1996, pp. 159-164

[db98]

M. Daniele, Praveen Jain, G. Joos, "A single stage single switch power factor corrected AC/DC converter", PESC 1996, pp. 216-222

[db99]

C. Q. Lee, Joel P. Gegner, "Linear peak current mode control: A simple active power factor correction control technique for continuous conduction mode.", PESC 1996, pp. 196-202

[db100]

Fred C Lee, R Watson, "A soft-switched, full-bridge boost converter employing an active-clamp circuit", PESC 1996, pp. 1948-1954

[db101]

Alexandre Ferrari de Souza, Ivo Barbi, "A new ZVS semi-resonant high power factor rectifier with reduced conduction losses", PESC 1996, pp. 203-209

[db102]

Moorthi Palaniapan, Ramesh Oruganti, "Inductor voltage controlled variable power factor buck-type AC-DC converter", PESC 1996, pp. 230-237

[db103]

Alexandre Ferrari de Souza, Ivo Barbi, "A new ZCS quasi-resonant unity power factor rectifier with reduced conduction losses", PESC 1995, pp. 1171-1177

[db104]

K. W.E. Cheng, S. R.N. Prakash, S Y.R. Hui, "A class of fully soft-switched power factor correction circuits", PESC 1995, pp. 1165-1170

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High Efficient Rectifiers

[db105]

C. Q. Lee, Ching-Yao Hung, Joel P. Gegner, "High power factor AC-to-DC converter using a reactive shunt regulator", PESC 1994, pp. 349-355

[db106]

L. Rossetto, G. Spiazzi, "High-quality rectifier based on coupled-inductor Sepic topology", PESC 1994, pp. 336-341

[db107]

Laszlo Balogh, Nathan O. Sokal, Richard Redl, "A new family of single-stage isolated power-factor correctors with fast regulation of the output voltage.", PESC 1994, pp. 1137-1144

[db108]

Denizar Cruz Martins, Adriano Peres, Ivo Barbi, "Zeta converter applied in power factor correction", PESC 1994, pp. 1152-1157

[db109]

Yimin Jiang, Fred C Lee, "Single-stage single-phase parallel power factor correction scheme", PESC 1994, pp. 1145-1151

[db110]

Alexandre Ferrari de Souza, Ivo Barbi, "A new ZVS-PWM unity power factor rectifier with reduced conduction losses", PESC 1994, pp. 342-348

[db111]

Ivo Barbi, Carlos Alberto Canesin, "A novel single-phase ZCS-PWM high power factor boost rectifier", PESC 1997, pp. 110-114

[db112]

M. S. Dawande, V. J. Farias, J. A. Correa Pinto, Adriano Alves Perira, J. B. Vieira, "A power factor correction preregulator AC-DC interleaved boost with soft-commutation", PESC 1997, pp. 121-125

[db113]

M. H.L. Chow, C. K. Tse, "New single-stage power-factor-corrected regulatots operating discontinous capacitor voltage mode", PESC 1997, pp. 371-377

[db114]

J. P. Ferrieux, J. Barbaroux, H. BenQassmi, "Current-source resonant converter in power factor correction", PESC 1997, pp. 378-384

[db115]

Huai Wei, I. Batarseh, Peter Kornetzky, Guangyong Zhu, "A single-switch AC/DC converter with power factor correction.", PESC 1997, pp. 527-535

[db116]

J. Arau, E. Rodriguez, E. Rodriguez, F. Canales, "A novel isolated high quality rectifier with fast dynamic output response", PESC 1997, pp. 550-555

[db117]

Mila M. Jovanovic, Laszlo Huber, "Design optimization of single-stage, singleswitch input-current shapers", PESC 1997, pp. 519-526

[db118]

G. Spiazzi, "Analysis of buck converters used as power factor preregulators", PESC 1997, pp. 564-570

[db119]

Michihiko Nagao, "One stage forward-type power factor correction circuit", 0, pp.

[db120]

O Garcia, F Nuno, P Villegas, J. Sebastian, J. Arau, "Improving dynamic response of power factor preregulators by using two-input high-efficient postregulators", Pesc 1996, pp. 1818-1824

[db121]

C. H. Chan, M. H. Pong, "Input current analysis of interleaved boost converters

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operating in discontinuous-inductor-current mode", Pesc 1997, pp. 392-398 [db122]

Dhaval Dalal, James P. Noon, "Practical design issues for PFC circuits", APEC 1997, pp. 51-58

[db123]

C. Qian, C. Qian, L. Ma, David M. Xu, C. Yang, X. He, "A novel single-phase active-clamped PFC converter", APEC 1997, pp. 266-271

[db124]

Y. S. Lee, B. T. Lin, K. W. Siu, "Novel single-stage power-factor-corrected power supplies with regenerative clamping", APEC 1997, pp. 259-265

[db125]

Mila M. Jovanovic, Laszlo Huber, "Single-stage, single-switch, isolated power supplt technic with input-current shaping and fast output-voltage regulation for universal input-voltage-range applications", APEC 1997, pp. 272-280

[db126]

Huai Wei, Peter Kornetzky, I. Batarseh, "A novel one-stage power factor correction converter", APEC 1997, pp. 251-258

[db127]

Fred C Lee, Jinrong Qian, "A high efficient single stage single switch high power factor AC/DC converter with universal input", APEC 1997, pp. 281-287

[db128]

J. Sebastian, M. M. Hernando, S. Ollero, P Villegas, "High quality flyback power factor corrector based on a two input buck post regulator", APEC 1997, pp. 288294

[db129]

Gerry Moschopoulos, G. Joos, Praveen Jain, Yan-Fei Liu, "A single-stage zerovoltage switched pwm full-bridge converter with power factor correction", APEC 1997, pp. 457-463

[db130]

Praveen Jain, Harry Soin, Praveen Jain, Nasser Ismail, "A power factor corrected single stage full bridge AC/DC converter topology with zero switching losses", APEC 1997, pp. 464-470

[db131]

Du I. Song, Geun H. Rim, Jung G. Cho, Ju W. Baek, Dong W. Yoo, "Zerovoltage-transition isolated PWM boost converter for single stage power factor correction.", APEC 1997, pp. 471-476

[db132]

G. Joos, Praveen Jain, J. R. Pinheiro, "Series-parallel resonant converter in selfsustained oscillating mode for unity power factor applications", APEC 1997, pp. 447-483

[db133]

Simon Fraidlin, Alexey Nemchinov, Rais Miftakhutdinov, Sergey Korotkov, "Asymmetrical half-bridge in a single stage PFC AC/DC converter", APEC 1997, pp. 484-488

[db134]

Ramesh Srinivasan, Ramesh Oruganti, "Analysis and design of power factor correction using half bridge boost topology", APEC 1997, pp. 489-499

[db135]

J. Arau, E. Rodriguez, F. Chan, J. Beristain, N. Vazquez, "An integrated high quality rectifier with sliding-mode contro", PESC 1998, pp. 1649-1654

[db136]

Ping H. Lin, Hung L. Cheng, C. S. Moo, "Parallel operation of modular power

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High Efficient Rectifiers

factor correction circuits", PESC 1998, pp. 1619-1624 [db137]

Praveen Jain, Mei Qiu, Gerry Moschopoulos, Humberto Pinheiro, "A PWM fullbridge converet with natural input power factor correction", PESC 1998, pp. 1605-1611

[db138]

Fred C Lee, Wei Chen, "Single magnetic, unity power factor, isolated power converter with ripple free input current", PESC 1998, pp. 1450-1455

[db139]

C. K. Tse, M. H.L. Chow, "A theoretical examination of the circuit requirements of power factor correction", PESC 1998, pp. 1415-1421

[db140]

C. H. Chan, M. H. Pong, "A fast response full bridge power factor corrector", PESC 1998, pp. 1436-1442

[db141]

M. H.L. Chow, C. K. Tse, Y. S. Lee, "Single-stage single-switch isolated PFC regulator with unity power factor, fast transient response and low voltage stress.", PESC 1998, pp. 1422-1428

[db142]

In-Dong Kim, Bimal K. Bose, "A new ZCS turn-on and ZVS turn-off unity power factor pwm rectifier with reduced conduction loss and no auxiliary switches", PESC 1998, pp. 1344-1350

[db143]

M. O. Buss, D. S. Schramm, "Mathematical analysis of a new harmonic cancellation technique of the input line current in DICM boost converters", PESC 1998, pp. 1337-1343

[db144]

Y. T. Choi, Y. K. Cha, B. C. Choi, H. G. Kim, M. H. Ruy, "Single stage AC/DC converter with low conduction loss and high power factor", PESC 1998, pp. 1362-1367

[db145]

J. Diaz, A. Fontan, M. M. Hernando, P Villegas, J. Sebastian, "A new current shaping technique using converters operating in continuous conduction mode", PESC 1998, pp. 1330-1336

[db146]

Jun-Young Lee, Gun-Woo Moon, Myung-Joong Youn, "Design of high quality AC/DC converter with high efficiency based on half bridge topology", PESC 1998, pp. 1054-1060

[db147]

Shin-ichi Motegi, Akeshi Maeda, "High quality input current waveform on softswitching DCM boost converter applying pulse-space-modulation", PESC 1998, pp. 1036-1040

[db148]

Pietro Scalia, "A double-switch single-stage PFC offline switcher operating in CCM with high efficiency and low cost", PESC 1998, pp. 1041-1047

[db149]

Lishan Tu, Haruo Watanabe, Fujio Kurokawa, Hirofumi Matsuo, "A novel softswitching buck-boost type AC-DC converter with high power efficiency, high power factor and low harmonic distortion", PESC 1998, pp. 1030-1035

[db150]

Chang Y. Jeong, Geun H. Rim, Ju W. Baek, Jung G. Cho, "Novel zero-voltagetransition isolated PWM boost converter for single stage power factor

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correction", PESC 1998, pp. 1023-1029 [db151]

Yoshio Mizutani, Takuya Ishii, "Power factor correction using interleaving technique for critical mode switching converters", PESC 1998, pp. 905-910

[db152]

Naganandini Jayaram, Dragan Maksimovic, "Power factor correctors based on coupled-inductor SEPIC and Cuk converters with nonlinear-carrier control", APEC 1998, pp. 468-474

[db153]

Mark Edmunds, R. Venkatraman, "A soft-switching single-stage AC-to-DC converter with low harmonic distortion - Analysis, design, simulation and experimental results.", APEC 1998, pp. 662-668

[db154]

O Garcia, J. A. Cobos, J. Uceda, P Alou, R. Prieto, "A high efficient low output voltage (3.3V) single stage AC/DC power factor correction converter", APEC 1998, pp. 201-207

[db155]

David C. Hamill, Nathan O. Sokal, K. Kit Sum, "A capacitor-fed, voltage-stepdown, single-phase, non-isolated rectifier", APEC 1998, pp. 208-215

[db156]

Jinrong Qian, Qun Zhao, Fred C Lee, "Single-stage single-switch power factor correction (S4-PFC) AC/DC converters with DC bus voltage feedback for universal line applications", APEC 1998, pp. 223-229

[db157]

Ivo Barbi, Claudio Manoel da Cunha Duarte, "A new ZVS-PWM activeclamping high power factor rectifier: Analysis, design, and experimentation", APEC 1998, pp. 230-236

[db158]

T. F. Wu, Y. C. Liu, T. H. Yu, "Principle of synthesizing single-stage converters for off-line applications", APEC 1998, pp. 427-433

[db159]

Rais Miftakhutdinov, Alexey Nemchinov, Simon Fraidlin, Valery Meleshin, Sergey Korotkov, "Integrated AC/DC converter with high power factor", APEC 1998, pp. 434-440

[db160]

M. M. Hernando, P Villegas, S. Ollero, J. Diaz, J. Sebastian, A. Fontan, "Improving dynamic response of power factor correctors by using seriesswitching post-regulator", APEC 1998, pp. 441-446

[db161]

Richard Redl, "An economical single-phase passive power-factor-corrected rectifier: Topology, operation, extensions and design for compliance", APEC 1998, pp. 454-460

[db162]

J. Sebastian, P Villegas, "Input current shaper based on the series connection of a voltage source and a loss-free resistor", APEC 1998, pp. 461-467

[db163]

M. M. Hernando, M. H.L. Chow, C. K. Tse, Y. S. Lee, "An efficient PFC voltage regulator with reduced redundant power processing", PESC 1999, pp. 87-92

[db164]

Jorma Kyyra, Vlad Grigore, "Analysis of a high power factor rectifier based on discontinuous capacitor voltage mode", PESC 1999, pp. 93-98

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[db165]

P Villegas, A. Fernandez, J. Sebastian, M. M. Hernando, "One stage, fast response, buck based ac-to-dc converter with active input current shaping", PESC 1999, pp. 99-104

[db166]

P Alou, J. Uceda, O Garcia, J. A. Cobos, R. Prieto, "A simple single-switch single-stage AC/DC converter with fast output voltage regulation", PESC 1999, pp. 111-116

[db167]

J. Fernando Silva, V Fernao Pires, "A single phase two-switch buck-boost type AC-DC converter with a high power factor and sinusoidal source current", PESC 1999, pp. 123-128

[db168]

Jose Antenor Pomilio, G. Spiazzi, "A low-inductance line-frequency commutated rectifier complying with IEC 1000-3-2 standars", PESC 1999, pp. 313-318

[db169]

O. Hernandez, N. Vazquez, J. Arau, E. Rodriguez, "A novel single stage DCUPS with power factor correction", PESC 1999, pp. 325-330

[db170]

Dariusz Czarkowski, Zivan Zabar, Doron Shmilovitz, "A novel rectifier/inverter with adjustable power factor", PESC 1999, pp. 337-341

[db171]

Mila M. Jovanovic, Yungteak Jang, "A new technique for reducing switching losses in pulse-width-modulated boost converters", PESC 1999, pp. 993-998

[db172]

Jindong Zhang, Fred C Lee, Mila M. Jovanovic, "Comparison between CCM single-stage and two-stage boost PFC converters", APEC 1999, pp. 335-341

[db173]

Jose Antenor Pomilio, G. Spiazzi, "A double-line-frequency commutated rectifier complying with IEC 1000-3-2 standars", APEC 1999, pp. 349-355

[db174]

S. Buso, G. Spiazzi, "A line frequency commutated rectifier complying with IEC 1000-3-2 standards", APEC 1999, pp. 356-362

[db175]

Soo-Yeub Yoo, Doron Shmilovitz, Dariusz Czarkowski, Zivan Zabar, "A novel reversible boost rectifier with unity power factor", APEC 1999, pp. 363-368

[db176]

A. Fernandez, P Villegas, M. M. Hernando, S. Ollero, J. Sebastian, "AC-to-DC buck converter with active input current shaper", APEC 1999, pp. 369-374

[db177]

Fabio Toshiaki Wakabayashi, Carlos Alberto Canesin, "A new family of zerocurrent-switching PWM converters and a novel HPF-ZCS-PWM boost rectifier", APEC 1999, pp. 605-611

[db178]

Vlad Grigore, Jorma Kyyra, "High power factor rectifier based on buck converter operating in discontinuous capacitor voltage mode", APEC 1999, pp. 612-618

[db179]

Mila M. Jovanovic, Yungteak Jang, "A novel active snubber for high-power boost converters", APEC 1999, pp. 619-625

[db180]

Yuri Panov, Mila M. Jovanovic, "Performance evaluation of 70-W two-stage adapters for notebook computers", APEC 1999, pp. 1059-1065

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[db181]

Michael Egan, Richard Morrison, "A new rugged integrated ac/dc converter with optimised input current.", APEC 1999, pp. 1086-1092

[db182]

R. L. Newsom, W. C. Dillard, R. M. Nelms, "A capacitor charging power supply utilizing digital logic for power factor correction", APEC 1999, pp. 1115-1122

[db183]

Fabiana Pottker de Souaza, Ivo Barbi, "A unity power factor buck pre-regulator with feedforward of the output inductor", APEC 1999, pp. 1130-1135

[db184]

Jindong Zhang, Fred C Lee, Mila M. Jovanovic, "An improved CCM singlestage PFC converter with low-frequency auxiliary switch.", APEC 1999, pp. 7783

[db185]

M. M. Hernando, S. Ollero, A. Fernandez, P Villegas, J. Sebastian, "Desing of an AC-to-DC converter based on a flyback converter with active input current shaper", APEC 1999, pp. 84-90

[db186]

Fu-sheng Tsai, Qun Zhao, Fred C Lee, "Design optimization of an off-line input harmonic current corrected flyback converter", APEC 1999, pp. 91-97

[db187]

Mila M. Jovanovic, Laszlo Huber, "Single-stage, single-switch input-currentshaping technique with reduced switching loss", APEC 1999, pp. 98-104

[db188]

F. F. Linera, L. Alveraz, J. Sebastian, A. Fernandez, J. Arau, "Single stage ACto-DC converter with self-driven synchronous rectification that complies with IEC-1000-3-2 regulations", APEC 1999, pp. 105-111

[db189]

Fred C Lee, Mila M. Jovanovic, Laszlo Huber, Jindong Zhang, "Single-stage input-current-shaping technique with voltage-doubler-rectifier front end", APEC 1999, pp. 112-118

[db190]

Praveen Jain, Mei Qiu, Humberto Pinheiro, Gerry Moschopoulos, "Analysis and design of a single-stage power factor corrected full-bridge converter", APEC 1999, pp. 119-125

[db191]

Z. Qian, Y. C. Ren, X. H. Wu, J. M. Zhang, David M. Xu, "A novel single-phase active-clamped ZVT-PWM PFC converter.", APEC 2000, pp. 456-459

[db192]

Zhaoming Quian, T C Green, Huiming Chen, Zhengyu Lu, "An improved topology of boost converter with ripple free input current", APEC 2000, pp. 528532

[db193]

Wen-Sung Chien, C. Leu, Jim H. Liang, "Skynet power factor correction cell", APEC 2000, pp. 475-479

[db194]

P Villegas, M. M. Hernando, S. Ollero, J. Sebastian, A. Fernandez, "A new active input current shaper for converters with symmetrically driven transformers", APEC 2000, pp. 468-474

[db195]

Keyue M. Smedley, Chongming Qiao, "A topology survey of single-stage power factor corrector with a boost type input-current-shaper", APEC 2000, pp. 460467

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Appendix A Appendix A is a collection of the papers published during the project. A1. A2 A3 A4

Lars Petersen, "Advantages of using a two-switch forward in singlestage power factor corrected power supplies", INTELEC 2000, pp. 325-331. Lars Petersen, "Input-current-shaper based on a modified SEPIC converter with low voltage stress", PESC 2001, pp. 1195-1201. Lars Petersen, Michael Andersen, "Two-stage power factor corrected power supplies: The low component stress approach", APEC 2002, pp. 666-671. Lars Petersen, Robert W. Erickson, "Reduction of voltage stresses in buck-boosttype power factor correctors operating in boundary conduction mode", APEC 2003, pp. 664-670.

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Appendix A1

Lars Petersen, "Advantages of using a two-switch forward in single-stage power factor corrected power supplies", INTELEC 2000, pp. 325-331.

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Advantages of using a Two-Switch Forward in Single-Stage Power Factor Corrected Power Supplies Lars Petersen Department of Applied Electronics, IAE Technical University of Denmark Building 451, DTU DK-2800 Lyngby, DENMARK Phone: (+45) 4525 5285, Fax: (+45) 4525 5300, email: [email protected] Abstract: A Single-Stage power factor corrected power supply using a two-switch forward is proposed to increase efficiency. The converter is operated in the DCM (Discontinues Conduction Mode) and it will be shown that this operation mode insures the intermediate DC-bus to be controlled only by means of circuit parameters and therefore independent of load variations. The DCM operation often has a diminishing effect on the efficiency but by use of the two-switch topology high efficiency with minimum circuit complexity can be achieved in this mode. A 500W 70V prototype of the two-switch boost-forward PFC power supply has been implemented. The measured efficiency is between 85% and 88.5% in the range 30W-500W and the measured power factor at full load is 0.95.

VAC

VDC

DC-bus PFC-Cell

DC/DC-Cell

DC/DCControl

PFC-Control

Figure 1a. Two-stage converter. Separate control of PFC and DC/DC conversion.

1 Introduction VAC

The introduction of the EN61000-3-2 specifications has resulted in a wide range of new active PFC-circuits. To reduce component count and productions cost the focus on the Single-Stage approach has been great. The block scheme in figure 1b shows the Single-Stage approach. In the Single-Stage approach only the output voltage is controlled by the control system. Therefore the topology used to implement the PFC-cell must be of one that will inherently perform this function. The most commonly used topology to perform the PFC in the Single-Stage approach is the DCM (Discontinuous Conduction Mode) boost-converter. The DC/DC-cell must perform the conversion from the DC-bus voltage to the desired output voltage and secure the galvanic isolation. One of the challenges in the Single-Stage approach is to control the DC-bus voltage without increasing the complexity of the converter. In this paper the proposed converter will be driven in the DCM for both cells. This mode of operation has the benefit of controlling the DC-bus voltage independent of load-current. The trend in the Single-Stage approach is going towards driving the cells in the CCM (Continuous Conduction Mode) to increase efficiency and reduce the need for EMI-filtering [1], [2]. With the proposed topology it will be shown that high efficiency and low complexity can be achieved in the DCM.

PFC- & DC/DC-Cell

VDC

DC-bus

Control

Figure 1b. Single-stage converter. DC/DC control circuit

2 Single-Stage Boost-Forward PFC Topology An important aspect of the Single-Stage approach is the ability to perform as good as or better than two-stage approach with respect to efficiency. Achieving higher efficiency over the two stage solution is difficult because optimisation of the Single-Stage converter usually comprise either the PFC ability or the DC/DC conversion. Another aspect of the Single-Stage approach is the stressing of the circuit components. For the Single-Stage circuit in figure 2 the critical component regarding loss of efficiency on the primary side is the switch Q. It must process the current from both the boost- and the forward-section. To keep losses to a minimum a low on-resistance switch is required. This again affects the switching qualities of the device increasing these losses. To achieve a high PF the power drain from the mains has to be pulsating (power proportional to sin2(ωt) gives PF=1).

LBoost

d2

d1

dm n:1

CB

LForward

and the flyback-inductance. Using this method on the boostforward topology the DC-bus voltage can be determined. The converter efficiency is assumed to be 100%:

PIN = POUT

Q

Forward-cell

Boost-cell Figure 2. Single-Stage power supply using Boost-Forward topology.

If the output voltage of the converter is to be tight regulated the pulsating power has to be decoupled internally. In the converter of figure 2 the pulsating power is decoupled by the storage capacitor CB. The DC-bus voltage at this node, VCB, is subjected to the power balance between the boost- and the forward-cell. There are 4 possible operating modes for the converter of figure 2 and depending on the actual mode the DC-bus voltage VCB will adjust accordingly. 2.1 CCM for both Cells For the converter of figure 2 this mode of operation is not very interesting because of the poor PF qualities of the continuous-current boost cell operated with constant switch on-time. As shown in [2] the DC-bus voltage is independent of load variations and is controlled by the steady state transfer function of the two cells. The CCM of the cells can only be sustained to a certain power level. Going from CCM to DCM will change the power balance, thus affecting the DC-bus voltage. 2.2 CCM Boost, DCM Forward Operating with constant switch on-time the CCM boost operation is not interesting as stated in section 2.1. 2.3 DCM Boost, CCM Forward When the Forward cell is operated in CCM and the boost cell is kept in the DCM the DC-bus voltage becomes dependent on load conditions. It has been shown in [3] that the DC-bus voltage increase dramatically when the forward cell is going towards the DCM.

The input-power of the boost-cell is given by:

  VCB 2 vIN (t ) ⋅ D 2 ⋅ T ⋅   V − v ( t )  CB IN  pIN (t ) = 2 ⋅ LBoost

(2)

where D is the duty-factor, VCB is the DC-bus voltage, vIN(t) is the time variant line voltage and T is the switching period. Averaging over one half period of the line frequency, input power can be expressed as:

  VCB ⋅ D 2 ⋅ T   ⋅    V − Vˆ ⋅ sin  n ⋅ π IN   CB  N  2 ⋅ LBoost ⋅ N

 n ⋅π VˆIN2 ⋅ sin 2  ∑  N n =1 N

PIN =

N=

2 ⋅ f Line f Switch

     

(3)

(4)

where VIN is the peak value of the line voltage, n indicates the nth switching period, fSwitch is the switching frequency and fLine is the line frequency. One would like to use the integral-form instead of the summation in Eq. (3), but there is no closed form solution to this equation when solving for the DC-bus voltage VCB. Thus, Eq. (3) must be solved numerical. The output power is given by:

POUT =

VCB ⋅ ( VCB − n12 ⋅VOUT ) ⋅ D 2 ⋅ T 2 ⋅ n122 ⋅ LForward

(5)

where n12 is the turns ration and VOUT is the output voltage. Using Eq. (1), (3) and (5):

 n ⋅π  VˆIN2 ⋅ sin 2    N   n ⋅π  VCB − VˆIN ⋅ sin    N  VCB − n12 ⋅ VOUT

1 N n ⋅ ⋅∑ N n =1 2 12

2.4 DCM for both Cells As shown in [4] the DC-bus voltage in a Single-Stage boostflyback topology, operated in DCM, can be determined by investigating the power balance between input and output. The result of this investigation was that the DC-bus voltage was found to be independent of load variations and only dependent on the line voltage and the ratio between the boost-

(1)

LBoost = LForward

(6)

From Eq. (6) one sees that the DC-bus voltage VCB is dependent on the boost-forward inductor-ratio, the turns

DC-bus voltage, VCB [V]

500

LBoost

450

d2

d1 CB

LForward

Q2 n:1 dm2

dm1 400

350

300

Q1 0

5

10

15

Inductance ratio, LBoost/LForward

Inductance ratio LBoost/LForward

Figure 3. DC-bus voltage as a function of Boost-Forward inductor ratio. The plot applies for VAC = 230V, VOUT = 70V and n12 = 1.5.

40 30

Figure 5. Single-Stage power supply using the two-switch Boost-Forward topology.

When using the two-switch forward in figure 5 instead of single-switch cell, the need for rectifier d2 becomes obsolete. The resetting of the magnetizing current effectively clamps the switch-voltage to the DC-bus. When taking the magnetizing current path into account further component reduction is possible. After the shortening of d2 one sees that rectifier dm1 is in parallel with d1 making dm1 obsolete. This gives us the simplified version of the two-switch boostforward of figure 6. LBoost

20

CB Q2 n:1 d 3 dm2

10 0

3

2 Turns ratio, n12

1 0

d1

100 50 Output voltage, VOUT [V]

Figure 4. Boost-Forward inductance ratio as a function of the turns ratio and output voltage. The plot applies for VAC = 230V and DC-bus voltage VCB = 400V.

ratio, the line-voltage and the output voltage but not on load conditions. In figure 3 the variation of the DC-bus voltage at different inductance ratios can be seen. Normally the line voltage is given and the DC-bus voltage is dictated by the availability of good high voltage devices (MOSFET’s, storage capacitors etc.). Figure 4 displays the inductance ration as a function of both the turns ratio and the output voltage. Unfortunately for the boost-forward topology the transformer turns ratio and the output voltage of the forward cell are also determining factors when calculating the DC-bus voltage as opposed to the boostflyback topology analyzed in [4].

LForward d4

Q1

Figure 6. Simplified version of the Single-Stage power supply using the twoswitch boost-forward topology.

IQ1

ILBoost IQ2

IQ2 IMagnetizing

ILBoost

Id1

2.5 The Two-Switch Boost-Forward Topology Instead of using the single-switch topology of figure 2 the two-switch forward can be used to reduce voltage stress and improve efficiency (figure 5). Both the single-switch and the two-switch boost-forward topology are part of the SingleStage family presented in [4] and [5].

Idm2 t0

t1

t2

t3

t4

Figure 7. Primary side current waveforms for the DCM two-switch boostforward topology of figure 6.

3. Circuit Operation As shown in section 2.4 the DCM operation of both cells will control the DC-bus voltage independent of load variations. Also, the DCM boost will offer a control/correction of the power factor [6]. Figure 7. shows the current waveforms of the primary side semiconductors for the converter in figure 6 when the DCM operation are employed. Circuit operation is simple and straightforward. t0:

t1:

Q1 and Q2 turns on. Rectifier d3 is forward biased while d1, dm2 and d4 is reversed biased. Energy starts building up in the Boost inductor, Forward inductor and the primary inductance of the transformer. Q1 and Q2 turns off. The Boost inductor current is directed trough d1 to the capacitive energy storage together with the magnetizing current. The Forward inductor current begins to flow in d4 as d3 is reversed biased. The magnetizing current from Q2 starts to flow trough dm2.

t2:

The resetting of the transformer is complete, thus turning off dm2

t3:

Energy stored in the Boost inductor during the interval t0-t1 has been delivered to the energy storage capacitor.

t4:

A new switching period begins.

RDS ( on ) ∝

2.5 VBR A

(7)

, where A is the die area. A 1000V MOSFET would have 5.6 times higher RDS(on) than a 500V MOSFET with the same die area. If the high voltage rating is needed the use of IGBT’s becomes more attractive. But because of the DCM operation of both cells the switching losses are confined to turn off losses only (except the discharging of the parasitic drain-source capacities of the MOSFET’s). The fact that the IGBT’s typically are associated with relatively high turn off losses may result in unacceptable overall efficiency. Throughout this section the leakage- and magnetizing currents will be disregarded. If you look at the two-switch topology in an ordinary DC/DC converter you can easily convert the expected reduction of on-resistance into how much you can reduce the conduction losses. Comparing a single-switch and a two-switch topology using the same total die area in the switches and assuming that the ON-resistance is proportional to the channel width the reduction in conduction losses can be calculated to:

PConduction ,1Switch PConduvtion ,2 Switch

=

2 I Sw , RMS ⋅ R ⋅ 5.6 2 I Sw , RMS ⋅ R ⋅ 2 ⋅ 2

= 1.4

(8)

,where R is the on-resistance for the low-voltage rated device.

Besides the stored magnetizing energy also leakage energy will be returned to the DC-bus making transformer design simple. The cost of using the two-switch forward over the single switch forward is the need for the extra switch and high side drive circuit. By use of a push-pull controller like the UC3825 or similar and a gate-drive transformer a cost effective gatedrive circuit can be implemented. 4. Performance of the Two-Switch Topology It is well known in design of regular DC/DC-converters that higher efficiency can be achieved by using two-switch topologies even though the current is processed by two switches. The need for lower voltage-rated devices allows the use of transistors where the on-resistance versus the switching qualities is relatively better than higher voltage rated devices. For MOSFET’s rated above 100V the major contributor to the channels on-resistance (RDS(on)) is the extended drain region, which is strongly related to the breakdown voltage (VBR) of the device. It can be shown that the relation between RDS(on) and breakdown voltage can be expressed as [7]:

Eq. (8) corresponds to a 40% increase of the conduction losses in the single-switch approach. The switching losses will also be reduced. Using only half the die area will reduce the parasitical capacitances and therefore increase the switching speed. Assuming that the channel width is proportional to the switching speed the switching losses per device will be reduced with a factor of two. In the single-switch case the drain-source voltage will have to be changed from zero to the supply voltage before the switch current starts to ramp towards zero. In the two-switch case the current will start this action when the drain-source voltage reaches half the supply voltage. A realistic guess would be that the over all switching losses are reduced with a factor of two. The effects of using a two-switch forward instead of a singleswitch forward with respect to efficiency are obvious. When the two-switch topology is employed in the single-stage PFC approach (figure 6) the effect on the efficiency is a bit more troublesome to present in a clear manner. The lower switch Q1 in figure 6 has to carry both the forward and the boost current, as shown in figure 7. In the following section a way

of quantifying the effects of using the two-switch configuration as opposed to a single-switch will be presented. Because of the forward cell being operated in the DCM the peak-current in the upper switch, Q2, can be expressed as:

2 ⋅ Pout IˆQ 2 = VCB ⋅ D

VCB Vˆ

(15)

(9)

D = IˆQ 2 ⋅ = 3

2 ⋅ POUT ⋅

2

    2⋅ P D  + 1 ⋅ OUT ⋅ 3  D ⋅VCB   (16)

(10)

VCB ⋅ D

 n ⋅π VˆIN ⋅ sin   N IˆLBoost (n) = LBoost

I Q1, RMS

  n ⋅π k ⋅ sin  1 N   N = ⋅ ∑ N n =1  η ⋅ Sum1  

c

D 3

The current flowing through Q1 is the sum of the switchcurrent, IQ2, and the boost-inductor current. The later varies in amplitude with the input line voltage over one half line period:

  ⋅ D ⋅T 

(11)

The input power is given by Eq.(4). Isolating LBoost from Eq.(4) and inserting this expression into Eq.(11) the peak inductor current can be expressed in terms of input power:

 n ⋅π  2 ⋅ PIN ⋅ sin    N  IˆLBoost (n) = D ⋅ VˆIN ⋅ Sum1

I Q1, RMS

  n ⋅π k ⋅ sin  1 N   N = ⋅ ∑ N n =1  η ⋅ Sum1  

2

     + 1 ⋅ I Q 2, RMS   

In the ordinary DC/DC converter with a two-switch topology the conduction losses are same for the two switches as stated earlier. A way of characterizing the difference in the conduction losses in the two-switch single-stage PFC converter is to investigate the ratio of the RMS2 currents because of the proportionality to the conduction losses.

RMS

2 Ratio

 I Q 2, RMS = I  Q1, RMS

(12)

  

2

  1 = N  

  n ⋅π k ⋅ sin  N   N  ∑ η ⋅ Sum1 n =1   

     + 1   

2

−1

   (17)   

Using the same notation as in Eq.(8) the conduction losses in the two-switch single-stage PFC can be expressed as:

where

 1 N  2  n ⋅π Sum1 = ⋅ ∑  sin  N n =1   N  

VCB  ⋅  V − Vˆ ⋅ sin  n ⋅ π CB IN   N

     

2 PConduction ,2 Switch = 2 ⋅ R ⋅ I Q21, RMS + 2 ⋅ R ⋅ I Q21, RMS ⋅ RMS Ratio

(13)

I Q1, RMS =

∑  ( Iˆ N

n =1



Q2

)

+ IˆLBoost ( n ) ⋅ 2

D  3

c 2 Q1, RMS

⋅ (1 + RMS

2 Ratio

)

Comparing the conduction losses of the single- and the twoswitch approaches as in Eq.(8), the conduction loss ratio in the single-stage PFC can be expressed as : (14)

c

PConduction ,1Switch PConduction ,2 Switch

   n ⋅π  2 ⋅ PIN ⋅ sin   N  2 ⋅ POUT   N = ∑    + ˆ  V ⋅ D  VIN ⋅ D ⋅ Sum1 n =1     CB    

(18)

PConduction ,2 Switch = 2 ⋅ R ⋅ I

The RMS-current in Q1 can the be expressed as:

I Q1, RMS

k=

In

The RMS-current flowing through Q2 can then be expressed as:

I Q 2, RMS

Introducing the term k as the ration between DC-bus voltage and the peak AC line voltage and taking the converter efficiency (η) into account Eq. (14) can be expressed as:

2      D    ⋅   3      

=

2.6

(1 + RM ) 2 Ratio

(19)

The RMS2Ratio given by Eq.(17) is plotted in figure 8 as a function of the ratio k (Eq.(15)). When the boost cell is operated in the DCM with a constant switch on-time, the

1

n12, Min =

PF 0.8 0.6 0.4

RMS2Ratio

0.2 0

1

1.5 k Figure 8. RMS2Ratio and PF as a function of k

2

theoretical PF can be determined by the ratio k. The exact equations are given in [6] so the result of the calculations will only be plotted in figure 8 together with the RMS2Ratio. Example: If the line voltage is 230V (325VPeak) and the DCbus voltage is 400V, then the ratio k = 1.23. This value of k translates into a PF = 0.95 and a RMS2Ratio = 0.5. Using Eq.(19), the reduction in conduction losses can be found:

PConduction ,1Switch PConduction ,2 Switch

=

2.6 = 1.73 (1 + 0.5)

(20)

The result of Eq.(20) states that the conduction losses of a single-switch approach would give rise to an increase in the conduction losses of 73% as opposed to a two-switch solution using the same chip die area.

5. Key Design Parameters The key element in designing the converter of figure 6 is to choose a desired DC-bus voltage VCB. To keep the boost-cell in DCM operation the duty-factor is limited to:

DMax =

VCB − VˆIN VCB

(21)

Under all circumstances the duty-factor D must be below 0.5 because of the two-switch forward. By taking into account the efficiency of the converter, the boost-inductor value is given by the desired output power:

  D 2 ⋅ T ⋅ VCB 2 2  n ⋅π  ˆ  V ⋅ sin ⋅ ∑ IN    N   V − Vˆ ⋅ sin  n ⋅ π n =1 IN   CB  N  = P 2 ⋅ OUT ⋅ N η N

LBoost

     

(22)

The minimum value of the turns ratio n12 to keep the twoswitch forward in the DCM is given by:

VCB ⋅ DMax VOUT

(23)

To reduce the RMS-currents on the secondary side and minimize losses the best choice of n12 is close to the minimum value of Eq (23). On the other hand a minimum value of n12 causes use of higher voltage-rated rectifiers on the secondary side. When the turns ratio has been selected the forward inductor can be calculated. Assuming converter efficiency of 100% will result in a DC-bus voltage smaller than expected. The reason for this, is that energy lost in the converter will affect the power balance. The calculated inductance ration given by Eq. (6) should be adjusted with the expected efficiency of the converter: ∗

 LBoost   LBoost   =  LForward   LForward

  ⋅η 

(24)

6. Experimental Results To verify the abilities of the converter a prototype of the twoswitch Boost-Forward PFC has been tested. A design of a 500W 70V output converter for 230V line input voltage (50Hz) has been implemented. The design and circuits parameters are: VCB = 400V, n12 = 1.5, LBoost = 63µH, LForward = 19µH, fSwitch = 100kHz, Q1 = Q2 = IRFP450LC, d1 = STTA8060, d3 = d4 = BYT115. As seen in figure 9 high efficiency is achieved over the full power range of the converter. Efficiency is over 88% from 80W – 320W and at full output power 86% is achieved. If more rugged power switches are used the efficiency at the high power levels can be increased but this will compromise the efficiency at the low levels. The idle power consumption is very low (< 2W) making the converter ideal for applications with large load variations. The DC-bus voltage was measured to 397V-405W over the full power range. The current waveform at full output power (485W) is shown in figure 10. With respect to the EN61000-3-2 this waveform will be classified as class D thus the relative limits of harmonic current applies. In figure 11 the harmonic content of the current is compared with the limits given by EN61000-3-2 at PIN = 564W. The measured current harmonics are well below the limits.

Efficiency (%)

90 88 86 84 82 80 0

100

200 300 400 Output Power, Pout (W)

500

Figure 9. Measured efficiency as a function of output power.

Figure 12. The experimental two-switch boost-forward Single-Stage PFC power supply.

Acknowledgments The author would like to thank Associated Professor Dr. Michael A.E. Andersen at the Technical University of Denmark for his valuable advice during this work. References

Current amplitude [Arms]

Figure 10. Measured line current of the experimental boost-forward converter at 564W input. The PF was measured to 0,947. Vertical spacing: 2A/div, horizontal spacing: 5ms/div.

Measured

2.5

EN61000 2 1.5 1 0.5 0 1

3

5 7 Harmonic number

9

11

Figure 11. Measured current harmonics at 564W input power and the limits given by EN61000-3-2 class D.

7 Conclusion This paper draws the attention to the properties of the twoswitch boost-forward topology as a high efficient SingleStage PFC power supply. Further more the two-switch topology makes it possible to achieve high efficiency in the medium to high power range. Experimental results have shown efficiency above 85% in the power range of 30W500W with good power factor and compliancy with the European norm EN61000-3-2.

[1] Laszlo Huber and Milan M. Jovanovic, “Single-stage, single-switch input-current-shaping technique with reduced switching loss”, IEEE Applied Power Electronics Conference, pp. 98-104, 1999 [2] Jinrong Qian, Qun Zhao and Fred C. Lee, “Single-stage single-switch power factor correction (S4-PFC) AC/DC converters with DC-bus voltage feedback for universal line applications”, IEEE Applied Power Electronics Conference, pp. 223-229, 1998 [3] Milan M. Jovanovic, Dan M.C. Tsang and Fred C. Lee, “Reduction of voltage stress in integrated high-quality rectifier-regulators by variable-frequency control”, IEEE Applied Power Electronics Conference, pp. 569-575, 1994 [4] R. Redl, L. Balogh and N. O. Sokal, “A new family of single-stage isolated power-factor correctors with fast regulation of the output voltage”, IEEE Power Electronics Specialists Conference, pp. 1137-1144, 1994 [5] R. Redl and L. Balogh, “Design considerations for singlestage isolated power-factor correctors with fast regulation of the output voltage”, IEEE Applied Power Electronics Conference, pp. 454-458, 1995 [6] Kwang-Hwa Liu and Yung-Lin Lin, “Current Waveform Distortion In Power Factor Correction Circuits Employing Discontinuous-Mode Boost Converters”, IEEE Power Electronics Specialists Conference, pp. 825-829, 1989 [7] J.G. Kassakian, M.F. Schlect and G.C. Verghese, “Principles of Power Electronics”, Addison-Wesley Publishing Company, Inc. 1991

High Efficient Rectifiers

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Appendix A2

Lars Petersen, "Input-current-shaper based on a modified SEPIC converter voltage stress", PESC 2001, pp. 1195-1201.

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with

low

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*

Input-Current-Shaper Based on a Modified SEPIC Converter with Low Voltage Stress Lars Petersen Department of Electric Power Engineering, ELTEK Technical University of Denmark, B. 325, DK-2800 Lyngby, DENMARK Tel: (+45) 4525 3481, Fax: (+45) 4588 6111 e-mail: [email protected]

Abstract-The boost topology is often the designer’s first choice when dealing with PFC front-ends. This topology is well documented in the literature and has obvious advantages like continuous input current and low voltage- and current-stress compared to other PFC topologies. The PFC SEPIC converter also has the advantage of the continuous input current but suffers from high voltage- and current stress. In this paper a Modified SEPIC converter is presented with reduced voltage stress, comparable to that of the boost converter. Experimental result of a 200W prototype for 185-270 V line voltage will also be presented.

I. INTRODUCTION By January 2001 the European standard, EN61000-3-2, will be a reality. The limits on the current harmonics imposed by EN61000-3-2 have been one of the driving forces in the past decade concerning research in the field of Power Factor Correction (PFC) and Input Current Shaping (ICS). For many applications, the main goal is not to achieve unity Power Factor (PF) but just to stay within the harmonic current-limits by minimum effort concerning circuit-complexity, cost and loss of efficiency. Therefore researchers have put a lot effort into developing power converters that could achieve PFC together with fast regulation of the output voltage ([1], [2]) (Single-stage topologies). The most commonly used topology for PFC, is the boost-converter. The distinct advantage of this topology is the continuous input current making EMIfiltering less of a problem compared to buck, buck-boost topologies. By using a boost-converter the output voltage has to be higher than the line peak voltage, which is not necessarily the optimal operating point for the following DC/DC-stage. The SEPIC converters input current is continuous and the output voltage can be lower than the line peak voltage. The major drawback of the SEPIC converter is the high current and voltage stress of the components [3]. In [4] it is shown how the SEPIC-converter in Discontinuous Conduction Mode (DCM) with a simple voltage loop achieves good PF. The voltage loop bandwidth has to be low in order not to regulate on voltage fluctuations caused by the pulsating power drawn from the line. Because of the voltage stress the use of IGBTs instead of MOSTETs are preferable. Since the switching abilities of IGBTs can be a problem concerning the efficiency, soft switching techniques are often employed ([4], [5]) further increasing the circuit complexity. In [6] the Sheppard-Taylor

topology is used as a PFC converter with the ability of creating a voltage lower than the line peak voltage with continuous input current but with increased circuit complexity as a result. In [7]-[9] buck topologies are used. A way to increase the PF for the buck converters is shown in [8] and [9], where a buck-boost converter is operated in parallel with the buck converter, so that current is flowing from the line even though the output voltage is above the instantaneous line voltage. When considering the different PFC topologies that are able to produce a voltage below the line peak voltage, the SEPIC converter seems to be an attractive alternative; mainly because of the continuous input current. In this paper a converter based on the SEPIC converter will be proposed as a PFC front-end. The voltage stress in the proposed converter is comparable with the voltage stress in the boost converter. In section II the proposed Modified SEPIC converter will be introduced. In section III, two different operation modes will be described and in section IV the theoretical calculations of section III will be experimentally verified with two different prototypes for line voltages in the range of 185Vac-270Vac.

II. THE MODIFIED SEPIC CONVERTER

L1

VAC

C1

Q1

L2

C2

Ro

Fig. 1. Classical PFC SEPIC converter The proposed converter is based on the classical SEPIC converter shown in Fig. 1, and compared to this converter, the proposed Modified SEPIC converter differs in two ways. The capacitor C1 is a large bulk capacitor; a diode is placed in series with the inductor L2. The bulk capacitor serves to decouple the pulsating input power, and the diode insures that the inductor L2 can be operated in discontinuous mode (DCM) without the capacitor C1 being charged to above the peak line voltage.

___________________________ This work is sponsored by the Danish Energy Agency under the Energy Research Program. J.nr. 1273/00-0013

*

D1

L1

C1

In the denominator of (1) the first fraction is related to the direct power transferred through L1 and the second fraction is related to the power transferred through L2. It is assumed that the bulk capacitor voltage, VC1, is constant during one half line period and therefore also during one switching cycle. The assumption that VC1 is constant during one half of the line period is not entirely correct. Twice the line frequency voltage-variation will be present on the capacitor C1.

D1

+ VAC

L2

Q1

C2

Ro

D2

Fig. 2. Modified PFC SEPIC converter. The input power to the converter is given by:

III. OPERATION MODES The modes described in this section, are all with the Modified SEPIC converter in DCM. The DCM operation is often used in low-power applications. The advantage of this mode is small magnetics, no reverse recovery problems with the rectifiers and reduced turn-on losses in the switch. The downside is higher rms-currents and more HF noise. A. Fast regulation of the output When regulating the boost PFC converter, a slow outer control loop is always applied in order not to regulate the pulsating input-power. This is not necessary with the Modified SEPIC converter because that the input-power is internally decoupled by the series bulk capacitor. The output is thereby decoupled from the input, and a fast loop can be implemented. The output power consists of two contributions; the direct transferred power from the input through L1 and the contribution from the series bulk capacitor, C1, through L2 to the output. Because of the fast regulation loop the output power will be kept constant and the duty-cycle, d(t), will be adjusted accordingly.

2 2 1 N TSwitch ⋅ d ( n ) ⋅ VˆIN ⋅ sin ( nN⋅π ) ⋅ (VC1 + VOUT ) ⋅∑ N n =1 2 ⋅ L1 ⋅ VC1 + VOUT − VˆIN ⋅ sin ( nN⋅π ) 2

PIN =

(

It has been shown in numerous papers (e.g. [2], [3] and [10]) how VC1 can be determined numerically. By using (1) and (2) one can determine VC1 as a function of the ratio L1 to L2, the input voltage and a given output voltage. The ratio of L1 to L2 should be chosen so that the maximum voltage level applied to C1 and Q1 in Fig.2 is below the desired level. In order to demonstrate the input current shaping a 200V output Modified SEPIC converter will be used. The use of 500V MOSFETs is desirable, so the ratio of L1 to L2 will be adjusted according to a maximum voltage stress on Q1 of 450V. The capacitor C1 should then be able to withstand 250V. With a ratio L1/L2 = 1.25, the voltage at the drain of Q1 will stay below 450V. Calculating the input current waveforms for a design of a 100W converter operated from 185-270 Vac, results in the waveforms shown in Fig. 3. 0.8

185 Vac 0.6

270 Vac 0.2

POUT

(

C1

OUT

IN

0

5 ms

10 ms

Line period (ms)

TSwitch ⋅ VOUT ⋅ VˆIN2 ⋅ sin 2 (ω t ) T ⋅V 2 + Switch C1 2 ⋅ L2 2 ⋅ L ⋅ V + V − Vˆ ⋅ sin (ω t ) 1

230 Vac

0.4

0

d (t ) =

(2)

)

In (2), N is the number of switch cycles during one half line period, and n is a running integer.

Input current (A)

The inductor L2 does not necessarily have to be operated in DCM but by insuring that no current can flow in the “off” direction of D2, the voltage VC1 can arbitrarily be controlled by the ratio of L1 to L2, as long as the sum of the output voltage and VC1 is higher than the line peak voltage. The drawback of adding D2 in series with L2, is not so much the power loss, since only part of the total power flows through D2, but the inherent galvanic isolation possibility is lost.

)

, where TSwitch is the high-frequency switching period.

(1) Fig. 3. Input current waveforms with line voltages of 185Vac, 230Vac and 270Vac for the Modified SEPIC converter with fast output regulation. POUT=100W.

2 CB VO2 − Vmin = 2 CO VCB

0.8

185 Vac

Duty-cycle

0.6

0.4

The Modified SEPIC converter with a maximum voltage stress of 450V at 270Vac, will have a minimum storage capacitor voltage of 100V at 185Vac. If the same size capacitor where to be used in a PFC buck-boost converter with an output voltage of 200V, using (5), the minimum voltage that the buck-boost converter should be able to handle is 173V, or a voltage drop of 13.5% of the output voltage. If the following DC/DC-stage can handle a larger voltage drop, the hold-up capabilities are better for the buckboost converter and vice versa.

230 Vac

0.2

270 Vac 0

(5)

0

5 ms

10 ms

Line period (ms)

Fig. 4. Duty-cycle variations given by (1) for 185Vac, 230Vac and 270Vac. L1 = 250 uH.

B. Constant peak-current control

Figure 4 shows the time varying duty-cycle. The increasing duty-cycle when the line voltage drops from the peak value, is responsible for the current shaping. Designing the fast outer voltage loop becomes increasingly difficult the larger the output capacity becomes. In the standard boost converter the output capacitor has to be large enough to decouple the pulsating input-power to meet the required ripple-voltage specifications. For the Modified SEPIC converter C1 serves as the decoupling capacitor, so small polyester capacitors can be used at the output. If holdup time is required, the main energy storage is then the series bulk capacitor, C1. The amount of energy stored is given by: 2 ECap. = 12 ⋅ C ⋅VCB

(3)

At low line, the voltage on VC1 is at its minimum and it is therefore in this situation, the value of the capacitor must be chosen to secure the hold-up capability. In case of a line failure the converter performs an active energy transferring from VC1 to the output. With the input cut-off, the converter is reduced to a buck-boost converter. For converters with passive energy-storage (e.g. boost, buck-boost) the useable energy can be determined by:

By using fast regulation of the output, the resulting dutycycle was seen to have a good current shaping quality. Using peak-current control with a slow voltage loop will also provide inherent high-quality input-current shaping. When keeping the switch peak-current constant over one half line period, the duty-cycle function can be described as:

d (t ) =

I ref

(6)

 Vˆ ⋅ sin (ω t ) VC1  + TSwitch ⋅  IN   L1 L2  

In (6) Iref is the demand peak-current set by the voltage loop. Since the voltage loop is slow, this reference current can be regarded as a constant, also with regard to the line period. By inserting (6) into (1) and (2), the bulk capacitor voltage VC1 can be calculated in the same manner as before. The duty-cycle function for a 200W, 200V Modified SEPIC converter is shown in Fig. 5, and the resulting input current is shown in Fig. 6. The values of L1 and L2 are 220 uH and 160 uH. 0.7 0.6

2 O

2 min

)

(4)

In (4) CO and VO is the capacitance and voltage at the output, and Vmin is the minimum voltage that can be accepted at the output. Using (3) and (4) a comparison of the energy storage capability can be made:

0.5 185 Vac Duty-cycle

EHold − up = ⋅ CO ⋅ ( V − V 1 2

0.4 230 Vac 0.3 0.2 270 Vac 0.1

0

5 ms Line period (ms)

10 ms

Fig. 5. The duty-cycle variation for the Modified SEPIC converter with constant peak-current control. POUT = 200W.

200uH, C1 = 680uF/250V, C2 = 2.2uF/250V, Q1 = IRF830 (500V). Fig. 7 shows the resulting input current for line voltages of 185Vac, 230Vac and 270Vac.

2 185 Vac

1.5 Current (A) Voltage (V)

Input curret (A)

Voltage (V) 170

0.6 230

90

0.3 115

230 Vac

1

0

0

Current (A) 0.4 0.2

0

0

Voltage

Voltage

270 Vac

0.5

a) 0

b)

Voltage (V)

0

5 ms

Current (A)

10 ms

Line period (ms)

270

0.4

135

0.2

0

0

Voltage

Fig. 6. Input-current waveform for the Modified SEPIC converter with constant peak-current control. c)

1.4 0.7 0 -0.7 -1.4

0 ms

5 ms

10 ms

15 ms

20 ms

25 ms

30 ms

a) 1.1 0.55

C. Alternative control strategies

0

The simple voltage follower approach can also be used. The input current will exhibit the same properties as a boost converter operated in the same way. A dedicated PFC control scheme is of course always a possibility if unity PF is the goal.

Line current (A)

In the constant peak-current controlled converter, the energy storage can be placed at the output without creating stability problems. But in order to keep the voltage relatively constant on C1, a certain amount of capacitance should make up this capacitor. With respect to the hold-up capability, it is not indifferent where the capacitance is located. The total energy storage to be used in case of a line failure is now, for the Modified SEPIC converter with a bulk capacitor at the output, the sum of (3) and (4). This means, that if the left side of (5) is larger than 1, the capacitance is more useful at the output and vice versa.

Fig. 7. Input-current of the Modified SEPIC converter with fast output regulation a) Vin = 185Vac, PF=0.89. b) Vin = 230Vac, PF=0.97. c) Vin = 270Vac, PF=0.98.

Line current (A)

The resulting current waveforms shown in Fig. 6, is not far from being sinusoidal.

-0.55 -1.1

0 ms

5 ms

10 ms

15 ms

20 ms

25 ms

30 ms

b)

IV. EXPERIMENTAL RESULTS

0

Line current (A)

1 0.5

-0.5

To verify the two operation modes, two prototypes have been tested. From a Power Factor point of view, the constant peak-current approach offers the most consistent high-quality current and the attention will therefore mainly be on the constant peak-current controlled converter (prototype 2).

-1

0 ms

5 ms

10 ms

15 ms

20 ms

25 ms

30 ms

c)

A. Prototype 1

Figure 8. Input current for prototype 2 of the Modified SEPIC converter with constant peak-current control. a) Vac=185, PF = 0.992. b) Vac=230, PF =0.990. c) Vac=270, PF = 0.986

The first prototype with the fast-regulated output voltage was tested with a simple voltage feedback loop. A 100W 200V output for 185-270Vac input voltage were build. The following component values were used: L1 = 250uH, L2 =

There is very god correlation with the predicted inputcurrent waveforms of Fig. 3. The asymmetry of the waveforms of Fig. 7 is caused by the 100Hz voltage variation

on the bulk capacitor C1. Even though the PF drops rapidly when the line voltage decreases, the harmonic content of the current (not shown), is well below the limits of EN61000-3-2, both class D and class A. B. Prototype 2 The second prototype was realized with the constant peakcurrent control. The experimental results were taken from a 200W, 200V output for 185Vac-270Vac. The following component values were used for this prototype: L1 = 220uH, L2 = 160uH, C1 = 680uF/250V, C2 = 680uF/250V, Q1 = IRFBX10N50A (500V). The input-current of the Modified SEPIC converter with the constant peak-current control is shown in Fig. 8. Again, the correlation between the predicted current waveforms of Fig. 6 and the experimental obtained is very good. Fig. 9 shows the efficiency for the nominal line voltage of 230Vac as a function of the output-power, and Fig. 10 shows the efficiency as a function of the line voltage (185Vac270Vac) at 200W.

The efficiency at maximum output power over the line voltage variation is above 93%. The line variation has very little effect on the efficiency, below 0.5% percent. Compared to a boost converter, the high-line efficiency of the Modified SEPIC converter is relatively far away from what can be expected from a boost converter, but at the low line, this relation improves. Since a 400VDC link-voltage not necessarily is the optimal operation point for the following DC/DC stage, the total system efficiency could be as good, or better than a standard approach with a boost converter.

V. FUTURE WORK The Modified SEPIC converter is not restricted to operate in DCM, even though this paper has only dealt with this operation mode. Ongoing work shows, that CCM operation is possible using the constant peak-current control. A working 200W prototype for universal mains (90Vac – 270Vac) is being investigated and the results obtained in this work, will be presented in a future paper.

VI. CONCLUSSION

Efficiency (%)

100

The task of shaping the input current to comply with EN61000-3-2 can be achieved using standard DC/DC control IC’s. Reducing the voltage stress to a level where the range of components is larger makes the design easier to dedicate to a specific application.

95 90 85 80 75

For the Modified SEPIC converter the most important pros and cons are:

70 65 10

50

100

150

200

Output power (W)

Pros •

Fig.9. Efficiency as a function of output-power for 230Vac line voltage (prototype 2).

Cons • • •

95

Efficiency (%)

• • •

94

Component voltage stress comparable with boost converters High quality input-current shaping Current limiting capabilities Uses standard current-mode control ICs

High current stress in the switch High current stress in the series bulk capacitor Inrush current limiting and galvanic isolation is lost (compared to the classical SEPIC)

93

REFERENCES

92 185

230

270

Line voltage (Vac)

Fig. 10. Efficiency as a function of the line voltage at POUT=200W for prototype 2.

[1]

[2]

M. Madigan, R. Erickson and E. Ismail, “Integrated High Quality Rectifier-Regulators”, PESC 1992 record, pp.1044-1051. R. Redl, L. Balogh and N.O. Sokal, “A New Family of Single-Stage Isolated Power-Factor Correctors

[3]

[4]

[5]

with Fast Regulation of the Output Voltage”, PESC 1994 record, pp.1137-1144. M.M. Jovanovic, D.M.C. Tsang and F.C. Lee, “Reduction of Voltage Stress in Integrated HighQuality Rectifier-Regulators by Variable-Frequency Control”, APEC 1994 record, pp.569-575. J. Sebastian, J. Uceda, J.A. Cobos, J. Arau and F. Aldana, “Improving power factor correction in distributed power supply systems using pwm and ZCS-QR SEPIC topologies”, PESC 1991 record, pp.780-791. C. Oliveiraand D. Maksimovic, “Zero-currenttransition converters for high-power-factor AC/DC applications”, APEC 1996 record, pp.159-165.

[6]

[7]

[8]

[9]

[10]

C.K. Tse and M.H.L. Chow, “Single stage high power factor converter using the Sheppard-Taylor topology”, PESC 1996 record, pp.1191-1197. AH. Endo, T. Yamashita and T. Sugiura, “A highpower-factor buck converter”, PESC 1992 record, pp.1071-1076. A.S. Kislovski, “Internal active parallel DC powerfactor and line-current correctors”, INTELEC 1996 record, pp.131-136. G. Spiazzi, “Analysis of buck converters used as power factor preregulators”, PESC 1997 record, pp.564-570. L. Petersen, “Advantages of using a two-switch forward in single-stage power factor corrected power supplies”, INTELLEC 2000 record, pp.325331.

Appendix A3

Lars Petersen, Michael Andersen, "Two-stage power factor corrected power supplies: The low component stress approach", APEC 2002, pp. 666-671.

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Two-Stage Power Factor Corrected Power Supplies: The Low Component-Stress Approach Lars Petersen

Michael Andersen

[email protected]

[email protected]

Department of Electrical Engineering Technical University of Denmark 2800 Lyngby, Denmark

Abstract- The discussion concerning the use of single-stage contra two-stage PFC solutions has been going on for the last decade and it continues. The purpose of this paper is to direct the focus back on how the power is processed and not so much as to the number of stages or the amount of power processed. The performance of the basic DC/DC topologies is reviewed with focus on the component stress. The knowledge obtained in this process is used to review some examples of the alternative PFC solutions and compare these solutions with the basic twostage PFC solution.

V * ⋅ I* (1) P * * The V and I in (1) are the voltages and currents that the specific component is sensitive to. E.g. MOSFETs are sensitive to maximum drain-source voltage and peak-currents with respect to switching losses and rms-currents with respect to conduction losses. More information and background for CLF can be found in [1].

I. INTRODUCTION

To keep the CLF calculations simple, the following assumptions are made:

Numerous single-stage and reduced power processing topologies have been presented in the literature predicting higher efficiency and/or lower cost. But very seldom these predictions are verified. The purpose of this paper is to direct the focus back on how the power is processed and not so much as to the number of stages or the portion of energy processed. The method used to compare the different approaches take its basis in the concept of Component Load Factors (CLF) introduced in [1]. Component stress can be translated into cost, size and efficiency so investigating the basic topologies and reviewing how the component stress evolves under different circumstances an overview of reasonable solutions are obtained together with an overview of what not to do. The knowledge obtained from the use of CLF can then be used to recognize where unnecessary component-stress is produced. Examples are given in section IV. In the first example part of a detailed analysis is shown. In the second example the limitations of the configuration is identified. II. COMPONENT LOAD FACTORS (CLF) The motivation for using a tool like CLF to compare different converter topologies is that it gives a quantitative measure of the performance of the converter. This is very useful when choosing between topologies. Definition of CLF:

CLF =

a. b.

PIN = POUT Inductor ripple current is small – meaning that square current waveforms are being switched.

In the first part of this section the case where the input is a DC-source will be reviewed. In the second part the CLF for the converters connected to an AC-source will be discussed. A. DC Input The Component Load Factors for the three basic topologies Buck, Boost and Buck-Boost will be presented. Since CLF represents accumulated stress for each component type, the calculated CLF of the basic Buck-Boost converter shown in figure 1c will actual represent the CLF for all Buck-Boost derived converters like the SEPIC, Cuk etc. If MOSFETs are used as switches (Q) in Fig. 1, the currents of interest are the peak-, and rms-currents. For the diodes the currents of interests are the peak-, and average-currents and to some extend rms-currents. The inductors (L) in Fig. 1 are all high-frequency inductors, so the use of rms-currents and the average voltage is of interest. The capacitors are sensitive to the DC-voltages and the RMS-currents. In table 1 the relevant CLF is listed for the three topologies shown in Fig. 1. The calculated CLF is presented as a function of the input/output voltage ratio.

Device

V*

I*

Q (MOSFET)

VDS, Peak

IPeak

VIN VOUT

VOUT VIN

VDS, Peak

IRMS

VIN VOUT

VOUT V ⋅ 1 − IN VIN VOUT

D (diode)

L (Inductor)

Buck

Boost

VAC, Peak

IPeak

VIN VOUT

VOUT VIN

VAC, Peak

IAverage

VIN −1 VOUT

1

VAverage

IDC(RMS)

æ

2 ⋅ çç1 − è

C1 (Input Capacitor)

VDC

C2 (Output Capacitor)

VDC

IRMS

VOUT VIN

ö ÷ ÷ ø

VIN −1 VOUT

æ

2 ⋅ çç1 − è

VIN VOUT

Buck-Boost

2+ æ VOUT ç ç V è IN

ö ÷ ÷ ø

+ 3⋅

ö ÷ ÷ ø

VOUT VIN

4⋅

VOUT 4 ⋅ VIN ⋅ 4− VIN VOUT

V IN VOUT

VIN VOUT

VOUT VIN

4⋅

VIN +1 VOUT

V IN VOUT

æ

* 2 ⋅ çç1 − è

VIN VOUT

VOUT −1 VIN

0

4⋅

2

0

IRMS

8⋅

VOUT V + IN + 3 VIN VOUT

VIN V + OUT VOUT VIN 1+

Isolated Boost

V 4 ⋅ IN VOUT

VIN V + OUT VOUT VIN

2

2+

Isolated Buck

*

VOUT VIN

VOUT VIN

2 ö ÷ ÷ ø

æ

2 ⋅ çç1 −

*

è

VIN −1 VOUT 0

VIN VOUT

ö ÷ ÷ ø

0

*

VOUT −1 VIN

Table 1. CLF for the basic topologies: Buck, Boost, Buck-Boost, isolated Buck and isolated Boost. * Does not apply to single-ended isolated Buck- and Boost converters

VIN

C1

D

VIN

C1

C2

VOUT

C2

VOUT

a)

L

D Q

b) Q VIN

C1

MOSFET Vp*Ip CLF

0.1

15 14 13 12 11 Buck 10 9 Boost 8 7 BuBo 6 5 4 3 2 1 0

a)

1

10

VOUT /VIN

10

MOSFET Vp*Irms CLF

CLF

D L

15 14 13 12 11 Buck 10 9 Boost 8 7 BuBo 6 5 4 3 2 1 0

CLF

L

Q

C2

VOUT

c) Figure 1. a) Buck DC-DC converter. b) Boost DC-DC converter. c) BuckBoost DC-DC converter.

The capacitor stress calculated in table 1 is carried out by assuming that the current flowing into and out of the converters of Fig. 1 are DC-currents. By investigating the results of table 1, one will find that the performance of the Buck and Boost converter is very similar and that they exhibit lower component stress than the BuckBoost derived converters, which should not come as a surprise. In the case where peak voltages and peak currents are used to calculate the CLF, shown in Fig. 2a, the Buck and boost performance is similar.

0.1

b)

1

10

VOUT /VIN

Figure 2. Switch CLF. a) CLF calculated with peak voltage and -current. b) CLF calculated with peak voltage and rms current.

The lowest CLF is obtained at the input/output ratio of 1 where the CLF=1 for the Buck and the Boost topology and CLF=4 for the Buck-Boost topology. As expected, the switch stress in the Buck-Boost topology is significantly higher. When the switch CLF using rms currents are used, the Buck and the Boost converter no longer perform the same. Fig. 2b, shows how the Boost topology is exposed to more stress compared to the Buck topology when the output/input ratio

CLF

Buck Boost BuBo

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Diode Vp*Iav CLF

0.1

a)

1

10

VOUT /VIN Inductor CLF

2

Boost 1

0.1

1

b)

CLF

10

VOUT/VIN

a)

1

10

VOUT/VIN MOSFET Vp*Irms CLF

0.1

b)

1

10

VOUT /VIN

Figure 4. Switch CLF for the isolated versions of the converters of figure 1. a) CLF calculated with peak voltage and current. b) CLF calculated with peak voltage and RMS current.

Capacitor CLF

4

0.1

15 14 13 12 11 Isolated Buck 10 9 Isolated Boost 8 7 Isolated BuBo 6 5 4 3 2 1 0

Buck

0

MOSFET Vp*Ip CLF

CLF

CLF

BuBo

15 14 13 12 11 Isolated Buck 10 9 Isolated Boost 8 7 Isolated BuBo 6 5 4 3 2 1 0

CLF

3

Buck Boost

2

BuBo 1

0 0.1

c)

1

VOUT /VIN

10

Figure 3 CLF. a) Diode CLF calculated with peak voltage and average current. b) Inductor CLF calculated with mean voltage and RMS current. c) Capacitor CLF calculated with DC voltage and RMS current.

increases/decreases. The stress characteristic for the BuckBoost topology seems to follow the Buck and the Boost stress pattern in the respective output/input ranges, although higher. The diode, inductor and capacitor stress is shown in Fig. 3. In all cases the Buck-Boost topology impose the most stress on the components. It is worth noticing the large difference in inductor and capacitor stress between the Buck-Boost derived topologies and the Buck- and Boost derived topologies when moderate step-up/step-down ratios are considered. As the step-up/stepdown ratio increases the difference in component stress evens out. If isolated converters derived from these three basic topologies are investigated one will find that the stress characteristics will change. Using isolated Buck- or Boost derived topologies will result in a substantial increase in semiconductor stress where as the stress on the rest of the components remain the same except when single-ended converters are used. The reason for this is that the effective

duty-cycle of these converters cannot exceed 50 percent. The minimum component stress for the inductors and capacitors is therefore equal to the component stress found at a stepup/step-down ratio of 2 for the non-isolated Buck- and Boost converters. For the Buck-Boost topology the isolation will not affect the component stress. The minimum stress for the isolated Buck and Boost derived topologies is obtained at an input/output ratio of 1 (CLF=4, Fig. 4a). The switch stress for the isolated Buckand Boost derived topologies shown in figure 4a, is a factor of 4 larger than for the non-isolated converters. The observations made when considering the component load factors for the basic topologies leads to the following key points: No voltage variations at the input: • •

•

The non-isolated Buck and Boost topologies are superior to the Buck-Boost topologies with regard to component stress. Isolating the Buck- and Boost derived topologies give rise to a substantial increase in semiconductor stress whereas the isolation does not affect the Buck-Boost derived topologies. If voltage step-up/step-down of more than a factor 4 is needed, an isolated topology should be considered.

Voltage variations at the input: •

Two-stage solutions should be considered since: 1) Isolated Buck- and Boost derived topologies are severely penalized with regard to semiconductor stress. 2) Buck-Boost derived topologies have high overall component stress.

B. Rectified AC Input

III. PFC SOLUTIONS

By investigating Boost and Buck-Boost derived topologies almost all practical PFC front-end circuits are covered. The Buck derived topologies are very seldom used especially when the universal line application is considered since the output voltage has to be lower the line peak voltage. Developing an AC/DC-version of the Component Load Factor is not as straight forward as for the DC/DC version. The good thing about CLF for the DC/DC converters is the simplicity of the calculations. This also insures that the correlation between the calculated stress factors and the actual component stress is not lost in process. For the AC/DC converters the voltages and/or currents change in the components during the line period. Therefore some kind of averaging is needed and in doing so, some of the characteristics of the circuit may disappear in this process. In the AC/DC case the inductors carry both a low and a high frequency component which makes it unsuitable to be characterized with a simple number as done for the DC/DC case. Semiconductor stress can be characterized using the same methods as in the previous section. The switch stress of the 3 obvious PFC candidates is shown in Fig. 5. 15 14 13 12 11 Boost 10 9 Isolated Boost 8 7 BuBo 6 5 4 3 2 1 0

MOSFET Vp*Ip CLF

CLF

15 14 13 12 11 Boost 10 9 Isolated Boost 8 7 BuBo 6 5 4 3 2 1 0

The step-up/step-down ratio for the AC/DC converters is defined as the ratio of the output- to line peak-voltage. From Fig. 5 it is clear to see that the isolated Boost PFC is a pour choice with regard to switch stress. The non-isolated Boost PFC exhibits the lowest switch stress but it is difficult see how it will perform compared to the Buck-Boost PFC, especially in case of the universal line range. This property will be investigated in section IV.

There are numerous ways to classify the different proposed PFC solutions. A suggestion of how this can be done is shown in Table 2[2]. There are two main groups: “1. Sinusoidal Current” and “2. Non-sinusoidal current”. 1. Sinusoidal Current 2. Non-Sinusoidal Current 1.1 Voltage follower 2.1 Passive filters 1.2 Passive filters 2.2 Reducing switches 1.3 Processing less energy 2.3 Removing control loops 1.4 Better processing 2.4 Combining topologies 1.5 Active filtering 2.5 Modifying DC/DC Table 2. Characterizing PFC solutions [2]

More information about the groupings of table 2 can be found in [2]. Almost all of the alternative PFC solutions presented in the different subgroups of table 2 uses one or both of the following properties: 1. 2.

Isolated converters operated directly from the acsource (1.4, 1.5). Energy storage capacitor where the storage voltage is dependent on the AC-source voltage (2.2, 2.3, 2.4, 2.5).

A. Property 1

0.1

a)

1

10

VOUT/VIN

MOSFET Vp*Ip CLF

CLF

For the solutions where the main idea is to process the energy less than 2 times the isolated converter has to be connected to both the input and the output since any galvanic isolation requires at least 1 full power-processing step. So in order to keep the processing below 2 full power-processing steps the isolated converter must be connected AC-source. As shown both for the DC/DC and AC/DC case the isolated converters have high semiconductor stress. In case of voltage variation at the input the semiconductor stress for the Boost converter increase dramatically. The Buck-Boost derived converters are not so sensitive to the voltage variation but these converters suffer from overall high component stress. B. Property 2

0.1

b)

1

10

VOUT /VIN

Figure 5. Switch CLF for the PFC Boost, Isolated Boost and Isolated/NonIsolated Buck-Boost converters. a) CLF calculated with peak voltage and current. b) CLF calculated with peak voltage and rms current.

In order to comply with the given regulations pulsating power has to be drawn from the AC-line. Therefore, internal

D1

decoupling of this pulsating power is also a requirement to maintain fast output regulation. The PFC approaches that use non-regulated internal energy storage are also known as Single-Stage converters. Normally these converters have a single control loop that regulates the output voltage but sometimes frequency control is added to the duty-cycle control to either limit the maximum internal storage voltage or to force the input current to comply with regulations. In all cases, the storage voltage is not constant but will vary with the input voltage. IV. HIGH COMPONENT STRESS PFC CONFIGURATIONS In this section examples of converters that suffer high component stress caused by the properties outlined in the previous section will be presented. The originally idea for the example converters of this section was to increase the efficiency by either reduce the number of stages or reduce the processing of power. A. Processing less power: The converter presented in [3] is the type of converter that without increasing the circuit-complexity compared to a twostage approach only process the power 1.5 times. The idea is that by reducing the total power processed higher efficiency can be achieved. D1 Q2 VAC

D2 Q1

L

C2

VAUX

C1

R

VOUT

Figure 6. Converter of [3] with 1.5 times power-processing.

The voltage VAUX in Fig. 6 is equal to VOUT, which enables half of the power to be transferred directly to the output reducing the overall power-processing to 1.5 times compared to 2 times for the standard two-stage approach. The auxiliary converter can be identified as Q2, D2, L and C2 and make up a Buck-Boost converter. The power processed by the auxiliary converter is pulsating from zero to full output power with an average equal to half the output power. Instead of the scheme shown in Fig. 6, the components used for the buck-boost converter could be used to utilize a Buck or a Boost converter as a post regulator in a two-stage configuration. In order to keep the comparison fair, the boost configuration is omitted because of its lacking ability to limit the output current. The voltage, VAUX, on the capacitor C2 is assumed to be equal to two times the output voltage so that the conditions for the isolated PFC stage is unchanged. A simple comparison between the schemes of Fig. 6 and Fig. 7 can then be carried out. The component stress for the two different approaches is presented in table 3.

L

Q2 VAUX

C2

D2

C1

R

VOUT

VAC Q1 Figure 7. Two-stage PFC I. Buck-Boost II. Buck I./II. Ratio 2 ⋅ VO 2 ⋅ VO VPeak 1 Q2 PO / VO IRMS PO /( 2 ⋅ VO ) 2 ( 4 ⋅ PO ) /(π ⋅ VO ) PO / VO IP,mean 4 /π 2 ⋅ VO 2 ⋅ VO VPeak 1 D2 PO /( 2 ⋅ VO ) PO /( 2 ⋅ VO ) IAV 1 ( 4 ⋅ PO ) /(π ⋅ VO ) PO / VO IP,mean 4 /π VO VO L VMean 1 PO / VO IRMS 2 ⋅ PO / VO 2 Table 3. Comparison between a “50%” power processing Buck-Boost converter and a “100%” power processing Buck converter.

The result of the comparison between the two approaches clearly shows that even though the Buck-Boost auxiliary/post regulator only process 50% of the power, the component stress and thereby the loses are greater than the approach with the Buck regulator despite the fact that this stage process 100% of the power. Besides the fact that the approach with the Buck converter is offering less component stress also energy storage and dynamic behavior of the converter is improved. In the scheme of Fig. 6, the auxiliary-converter has to be a Buck-Boost type or an isolated Buck or Boost converter – all which would have higher component stress compared to the solution with the simple Buck converter as a pre regulator. The isolated PFC converter is necessary for the PFC approach that process less power. From Fig. 5 in section II, it is clear to see that the isolated Boost PFC are subjected to severe semiconductor stress, especially if the universal voltage range is applied. For the isolated Buck-Boost derived PFC circuits it is not clear to see if the component stress could be reduced by separating the PFC-function from the isolated converter. In order to investigate the switch stress of the isolated PFC buck-boost converter of Fig. 8a, the conduction and switching losses of this configuration will be compared with the two-stage system shown in Fig. 8b. This system consists of a PFC boost converter and an isolated Buck derived converter. Here the switch stress comparison is carried out assuming that the total chip die area is the same for the two configurations of figure 8. Further more, it is assumed that the switching devices have the same voltage rating. The last assumption is not completely fair to the two-stage system since lower voltage rated devices can be used compared to the isolated PFC Buck-Boost converter. For the universal line range (90VAC-270VAC) the output voltage of the boost converter has to be:

D1

VOUT ,BOOST = Voltage _ range ⋅ VˆLine , Min

(2) C1 VAC

As shown in section II, the minimum component stress for the Buck-Boost derived converters is in the area of 50% dutycycle (VIN = VOUT). The output voltage should therefore be calculated as: (3) VOUT ,BUCK − BOOST = Voltage _ range ⋅ VˆLine ,Min

Q1 a) L

D1 Isolated BuckConverter

C1

The On-resistance of a MOSFET is proportional to 1/ADie [4]. The conduction losses are therefore proportional to: I2 PConduction−loss ∝ RMS (4) ADie The largest conduction losses occur at low line for both systems. An expression for the conduction losses as a function of the input power and the peak line-voltage can be calculated for the two systems in figure 8. Using the relation between VOUT and VLine,Min, expressions for the conduction losses can be calculated. For the Buck-Boost PFC the losses are proportional to: PLoss _ BUCK − BOOST

æ P ∝ç ç Vˆ è Line , Min

ö ÷ ÷ ø

2

⋅

2.98 ADie

(5)

For the two-stage system the losses are proportional to: PLoss _ BOOST + BUCK

æ P ∝ç ç Vˆ è Line , Min

ö ÷ ÷ ø

2

æ

1.43 0.22 + x ⋅ ADie è (1 − x ) ⋅ ADie

⋅ çç

ö ÷ ÷ ø

(6)

x ∈ [0,1] As it is seen from (6), the total chip die area is shared between the two stages of figure 8b. Minimum conduction losses are achieved for x = 0.28 meaning that 72% of the total die area should be used for the PFC Boost converter and the rest for the isolated Buck converter. The ratio of (5) to (6) is the relation between the conduction losses of the two systems.

K Conduction− Loss _ ratio =

PLoss _ BUCK − BOST PLoss _ BOOST + BUCK

= 1.07

(7)

From (7) one can see that even though the power is processed by two stages the system does not generate more conduction loss per chip die are. The switching losses are assumed to be proportional to the product of the voltages and currents being switched and the switching transition-time is proportional to the chip die area. The switching losses can then be approximated with: (8) PSwithing− Loss ∝ V ⋅ I ⋅ ADie

VOUT

R

VAC

Q1

R

VOUT

b) Figure 8. a) Isolated Buck-Boost PFC. b) Two-stage PFC system comprised of a Boost PFC and an isolated Buck DC/DC converter.

B. Single-Stage PFC converters: The most severe problem with the single-stage converters is the voltage variation of the internal bus. Besides the problems with hold-up capacity the major contributor to power loss in the single-stage converters is the increased semiconductor stress. The biggest problems arise when the application is targeted for the universal input voltage. In order to reduce the voltage variation, a voltage-doubler version of the Single-Stage topology presented in [5] was proposed in [6] (Fig. 9a). The converter was designed for a 5V, 90A output. When analyzing the current-shaper block in Fig. 9a one will find that this configuration is very efficient and the stress imposed on the switches in the 2-Switch Forward is moderate. If allowing the use of a range-switch, other Boost derived topologies would perform just as good as the scheme shown in Fig. 9a. An example of such a converter could be the half-bridge Boost PFC converter with range-switch presented in [7]. N1 VIN

N1

VOUT

NS

NP

2-switch Forward

Current-shaper

a)

Current-shaper

NS

NP

VOUT

2-switch Forward

The switching loss ratio is given by:

K Switching − Loss _ ratio =

PLoss _ BUCK − BOST PLoss _ BOOST + BUCK

Voltage step-up regulator

= 1.21

(9)

Again, the two-stage solution does not increase the switching losses.

b) Figure 9. a) Single-stage PFC converter proposed in [6]. b) A reduced component stress version.

Components

2-Switch Forward:

2-Switch Forward:

DC-DC Boost:

VIN: 235V-375V

VIN: 375V

VIN: 235V-375V

1

Switches

3 ARMS, 375V

1.88 ARMS, 375V

1.3 ARMS, 375V

2

Diodes

69 AAverage, 21V

50 AAverage, 15V

1.3 AAverage, 375V

3

Transformer

No difference

No difference

-

4

Inductors

3.45 V·s/fSwitch, 100ADC

2.5 V·s/fSwitch, 100ADC

88 V·s/fSwitch, 2.12 ADC

5

Capacitors

* See below in text

* See below in text

* See below in text

Table 4. Comparison of the two output sections of Fig. 9.

The voltage at the input-terminals of the 2-switch Forward in Fig. 9a varies from 235V to 375V at full power for the universal-line range 90VAC-265VAC. From the observations made in section II, it is clear that the voltage variation at the input of the 2-switch Forward will increase the component stress. As an example of the effects of the input voltage variations, it will be shown that adding an extra stage to cope with this, will actual reduce the overall stress and thereby improve efficiency. The configuration of Fig. 9b uses an extra switch to perform the step-up action. Again, to keep the comparison fair the same total chip die-area (ADie) is available for the two configurations. In order for the 2-stage output section to have less conduction loss than in the case with the single-stage output section the following equation has to be true: 2 4 ⋅ I RMS , Forward , Single− Stage

x ∈ [0,1]

ADie

≥

2 4 ⋅ I RMS , Forward ,Two − Stage

x ⋅ ADie

+

2 I RMS , Step− up

(1 − x ) ⋅ ADie

Solving the above equation and minimizing the conduction losses in the two-stage configuration will result in a value of x = 0.67. Using the data of table 4 one finds that the Singlestage configuration increases the switch conduction losses with 40% even though the voltage variation is moderate compared to other Single-Stage converters. The switching losses can found to be about the same in the two cases (7% increase in switching losses when using the single-stage configuration). The output diodes in the single-stage configuration are also subjected to an increase of 40% in both blocking voltage and current rating which in this case where the output current is high will have an impact on the efficiency. The diode added in the step-up converter is subjected to an average current of 1.33A, which will not affect the efficiency noticeable. The worst-case transformer stress is at the duty-cycle D = 0.5 and in both cases the transformer stress is the same. The output inductor stress in the two-stage case is less than for the single-stage case but an extra inductor is needed in the stepup converter. The overall inductor stress is higher in the twostage configuration because a single-ended Buck derived

topology is used. The magnetic stress would be the same if half-bridge or full-bridge isolated converters were used. In case of the capacitor the two-stage solution offer a clear advantage with respect to hold-up capacity. The energy is stored at a high voltage and since the step-up converter is inserted between the current-shaper and the 2-Switch Forward all the energy stored at the output of the currentshaper can be utilized. V. CONCLUSION The two-stage approach secures a minimum total stress on the circuit components. Further research in PFC systems should be directed towards optimizing the PFC stage and/or the DC/DC stage. It is misunderstood that reducing the number of stages and/or processing less power automatically achieves higher efficiency. Proper design and proper power processing achieve high efficiency. In general low component stress can be translated into high efficiency, small physical size and low cost. In the low power range some of the alternative solutions can have an advantage in cost compared to the two-stage solution but the efficiency will be sacrificed.

REFERENCES [1] [2] [3]

[4]

[5]

[6]

[7]

Bruce Carsten, “Converter component load factors; A performance limitation of various topologies”, PCI 1988, Munich O. Garcia, J.A. Cobos, R. Prieto, P. Alou, J. Uceda, “Power Factor Correction: A survey”, PESC Proc. 2001 O. Garcia, J.A. Cobos, P. Alou, R. Prieto, J. Uceda, S. Ollero, “A new family of single stage AC/DC power factor correction converters with fast output voltage variation”, PESC Proc.1997. J.G. Kassakian, M.F. Schlect and G.C. Verghese, “Principles of Power Electronics”, Addison-Wesley Publishing Company, Inc. 1991. J. Sebastian, M.M. Hernando, P. Villegas and J. Diaz, A. Fontan, “Input current shaper based on the series connection of a voltage source and a loss-free resistor”, APEC Proc. 1998, pp 461-467. J. Zhang, F.C. Lee and M.M. Jovanovic, “Design and evaluation of a 450W single-stage power-factor-correction converter with universal line input”, APEC Proc. 2001, pp 335-341. R. Srinivasan, R. Oruganti, “Analysis and design of power factor correction using half bridge boost topology”, APEC Proc. 1997, pp 489-499.

High Efficient Rectifiers

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-204-

Appendix A4

Lars Petersen, Robert W. Erickson, "Reduction of voltage stresses in buck-boost-type power factor correctors operating in boundary conduction mode", APEC 2003, pp. 664670.

-205-

High Efficient Rectifiers

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-206-

Reduction of Voltage Stresses in Buck-Boost-Type Power Factor Correctors Operating in Boundary Conduction Mode Lars Petersen

Robert W. Erickson

Institute of Electric Power Engineering Technical University of Denmark Building 325, 2800 Lyngby, Denmark [email protected]

Colorado Power Electronics Center Department of Electrical and Computer Engineering University of Colorado at Boulder Boulder, CO 80309-0425, USA

Abstract-In this paper a new converter is proposed for universal line PFC operated in Boundary Conduction Mode. The proposed Modified SEPIC enables the use of lower voltage rated semiconductors compared to other single-switch buck-boost derived topologies with a resulting performance comparable to the boost topology. The operation and the design procedure is described in detail and the proposed converter is experimental verified with a 210V, 100W prototype for the universal line input (90Vac-270Vac).

II. MODIFIED SEPIC

I. INTRODUCTION The Boost topology is often used for PFC applications because of its superior performance (efficiency, cost). In some cases the buck-boost topology is preferred because of the ability to generate output voltages less than the line peak voltage. This can be an advantage for the downstream converter since lower voltage rated devices and/or more costeffective topologies can be used. The problem for the buckboost family of converters (especially for the universal line range) is the high voltage and current stresses. Typically the voltage rating of the semiconductors are in the 800V range which impairs the performance dramatically compared to boost-type converters. [1-4] A new converter is proposed that addresses all of the needs described above. The benefits of the proposed converter are:

The standard PFC SEPIC for the univerasal line application requires high voltage (800V) semiconductors [2] which adds to the converter cost and impairs the efficiency compared to the Boost converter. The Modified SEPIC shown in Fig. 1a can be forced into operation modes where the voltage stress is reduced to a level compareable with that of the PFC Boost [5]. The major difference between the Modified SEPIC and the SEPIC is the diode D2 added in series with L2 in Fig. 1a. The diode effectively blocks the current path from the input through L1, C1, L2 and D2 that in normal SEPIC operation secures the volt-second balance of L1 and L2 by adjusting the voltage on C1 to be equal to the input-voltage. With this diode in series with L2, the voltage on C1 is now govern by the power-equality (PIN=POUT). If the inductor L1 and L2 is operated in DCM, the voltage on C1 can be controlled by the inductance ratio L1/L2. Further more, the C1 voltage will go towards a DC-voltage if large bulk capacitors are used. L1

C1

VIN

D1

C2

L2

Q

R Load VOUT

D2

• • • •

Low voltage stresses (500-600V devices) Single switch Small magnetics Simple control

The proposed converter is targeted for the low power range (50-200W) and operated in the Boundary Conduction Mode (BCM). The BCM operation is often preferred in the lower power range because it facilitates zero-current switch turn-on, minimizes the reverse recovery problem of the freewheeling diode and tends to reduce the overall magnetic size. The paper will include: analysis, design guidelines, comparison with previous approaches, experimental data and a prototype schematic.

a)

IL2 IL1

t1 b)

t22 t21

Figure 1. a) The proposed Modified SEPIC. b) Current waveforms of the inductors L1 and L2. Down-ramp time of the inductor L1 is dependent on the instantaneous line voltage.

t 21 = t1 ⋅

t 22 = t1 ⋅

VOUT

V IN (t ) + VC1 − V IN (t )

VC1 VOUT

(1)

(2)

Since PF = 1 is not at all necessary to comply with EN61000-3-2 the operation mode #2 described above is the preferred operation, mainly because of the zero-current switch turn-on, but there are other advantages that will be explained later. The disadvantage is the implementation of the zerocurrent detection of L2. B. Steady-state analysis

A. Operation modes When operating the Boost PFC converter in BCM the following key points characterizes the operation: • • • •

Variable frequency operation Small magnetic size Switch turned on under Zero-current condition Theoretical PF = 1

In case of the Modified SEPIC converter we will consider two different operation modes, both based on the BCM Boost PFC.

In order to obtain the capacitor voltage VC1, the power equality is used (PIN=POUT): PIN = 2 ⋅ f line ⋅

∑ (V

POUT = 2 ⋅ f line ⋅

∑V

ˆ

  

)

⋅ sin (ω ⋅ t ) ⋅ t1 ⋅ (t1 + t 21 (t )) 2 ⋅ L1 2

AC

(4)

ˆ ⋅ sin (ω ⋅ t )⋅ t  V ⋅t 1 AC ⋅ t 21 (t ) ⋅VOUT + C1 1 ⋅ t 22 ⋅ VOUT  2 ⋅ L1 2 ⋅ L2 

(5)

,where t21 and t22 is defined as in (1) and (2), t1 is the constant switch on-time. Setting PIN = POUT:

Mode #1: The input section of the Modified SEPIC is similar to the boost converter so the control-method used in the BCM Boost PFC can be adopted directly. Since the PFC Boost BCM control detects zero-current in the input inductor (L1), the zero-current condition is not always met for the current in Buck-Boost inductor (L2). The down-ramp time of the input inductor L1 (shown in Fig. 1b as t21) determines the switch turn-on action. The zero-current switch turn-on condition is only met when t21 is larger than the down-ramp time of the inductor L2, t22. By manipulating (1) and (2) one can find that the zero-current switch turn-on condition is satisfied when:

VIN (t ) > VC1

(3)

Mode #2: One of the very nice features of the BCM operation mode is that the losses associated with the diode reverse recovery is greatly reduced. If this feature and the zero current turn-on of the switch is to be maintained during all operation of the Modified SEPIC-converter, current sensing in both inductors L1 and L2 has to be implemented. While maintaining the zerocurrent switch turn-on, the power factor can no longer reach the theoretical value of 1. The reason for this is that the L1 inductor-current will no longer be in BCM when the L2 inductor-current determines the switch turn-on. The following key points characterizes this operation mode: • • • •

Variable frequency operation Small magnetic size Switch turned on under Zero-current condition Theoretical PF < 1

∑ (Vˆ

L1 = L2

)

⋅ sin (ω ⋅ t ) ⋅ (t1 + t 21 (t )) − 2

AC

∑Vˆ

AC

⋅ sin (ω ⋅ t ) ⋅ t 21 (t ) ⋅ VOUT

VC1 ⋅ VOUT ⋅ t 22

(6)

Using (1), (2) and (6):

L1 L2

∑ (Vˆ

AC

=

2

 V  OUT

 VOUT + VC1  ˆ + V − V ⋅ sin (ω ⋅ t )  C1



AC

VC21

∑ Vˆ

AC

−

)

⋅ sin (ω ⋅ t ) ⋅ 

⋅ sin (ω ⋅ t ) ⋅VOUT

 ⋅ V  OUT

(7)  VOUT + VC1  + V − Vˆ ⋅ sin (ω ⋅ t )  C1

AC



VC21

There is no closed form solution to (7) when solving for VC1, but (7) can very easily be solved numerically. For a given output voltage and line voltage, the capacitor voltage VC1 only depends on the inductance-ratio, L1/L2. This is only true because both inductors L1 and L2 are operated in BCM/DCM. Going into CCM operation the load will also influence the VC1 voltage. III. PERFORMANCE OF THE PROPOSED CONVERTER For the universal line application (90VAC-270VAC), the maximum semiconductor stress occurs at high line (270VAC). Fig. 2a displays the inductance-ratio as a function of the maximum voltage stress for 180V, 210V and a 240V outputvoltage. The reason for using a Buck-Boost type converter is in most cases a necessity of generating an output voltage less than the line peak voltage, typically in the area of 200V. If the semiconductor voltage stress of the Modified SEPIC

5

L 1/L 2

1 0.8

4

fN(90VAC) 0.6 fN(270VAC) 0.4

Vo=180 3 Vo=210 Vo=240

2

0.2

a) 1

0

0

0.002

0.004

0.006

tLine

0 350

[s]

1.5

400

450

a) [V]

0.008

500

550

600 1.2

Vstress

IIN (90VAC) 0.9

200

ISinusoidal

0.6 0.3

150

b) V C1

0

0

0.002

100

0.004

0.006

tLine

0.008 [s]

1.5

50

1.2 IIN (270VAC)

0

50

100

b)

150

200 V AC

250 300 [V RM S ]

ISinusoidal

0.9 0.6 0.3

Figure 2. a) The inductance ratio as a function of the maximum semiconductor stress. b) VC1-voltage as a function of AC-line voltage, L1/L2=3, VOUT=210V.

converter should be comparable with a boost converter (∼400V) the inductance ratio value should be chosen to be in the area of 3 (Fig. 2a). This would facility the use of 500V rated semiconductors with a margin of 100V for the 100/120 Hz capacitor voltage ripple and overshoots. Fig. 2b shows the capacitor voltage, VC1, as a function of the line voltage. At low-line the VC1 is about 20V and increases with the line voltage to 190V at high-line. The BCM control is a variable switching frequency control method but for the Modified SEPIC using the operation mode #2 described in section II, the frequency operation can be divided into parts: • •

VC1 < VIN(t) => Variable switching frequency VC1 > VIN(t) => Constant switching frequency

When VC1 is below the instantaneous line voltage the L1 inductor current down-ramp time determines the switch-on action, which varies with the line voltage supporting the variable frequency. When VC1 is above the instantaneous line voltage the L2 inductor current down-ramp time determines the switch-on action. Since VC1 is considered constant the down-ramp of the L2 inductor current will also be constant supporting constant frequency operation. The greatest impact of the operation mode #2 is found at high line. Fig. 3a shows how the variable frequency range is

c)

0

0

0.002

0.004

0.006

tLine

0.008 [s]

Figure 3. a) Normalized frequency with respect to the (constant) switch ontime. b) Normalized line current at VAC=90V. c) Normalized line current at VAC=270V.

greatly reduced compared to the operation mode #1 where the normalized frequency would go all the way up to 1. The impact of the constant frequency operation on the line current is depicted in Fig. 3c. The dashed line is the normalized ideal sinusoidal line current and one can see that the actual line current is somewhat distorted in the region of the constant frequency operation. The power obtained from the line in the area of the line voltage zero-crossing is small which only give rise to a slight increase of peak-current in the actual line current. At low line the difference between the ideal and the actual line current is insignificant (no visual difference in Fig. 3b).

IV. COMPARISON Besides the reduced voltage stress, the Modified SEPIC converter also reduces the stress on the magnetic components leading to smaller magnetic size compared to the classical SEPIC. Because of the reduced component stress the performance of the Modified SEPIC is even comparable with the BCM Boost PFC. When comparing the Modified SEPIC with the boost converter one should keep in mind the

difference in output voltage. The comparison can never be ideal because of this difference. Nevertheless the comparison is carried out to demonstrate that the increase in component stress is not that significant when choosing a medium output voltage (using the proposed topology) instead of a high output voltage (boost topology). The comparison will include the following converters: • BCM SEPIC [1] • The proposed BCM Modified SEPIC • BCM Boost [4] The comparison is carried out assuming that the converters are satisfying a minimum switching frequency of 20 kHz and an input power of 110W. For the SEPIC and the Modified SEPIC, the output voltage is 210V, and for the Boost converter, 400V. The Modified SEPIC uses an inductance ratio of 3, so that the maximum voltage stress is 400V. A. Inductor stress

The minimum switching frequency (20 kHz) and the Power level determines the inductor sizes for the BCM operated converters. Table 1 sums up the results for the three converters in this comparison.

L1

L2

Energy storage

SEPIC

1.5mH

1.5mH

9.1 mJ

Proposed M. SEPIC

750uH

250uH

4.8 mJ

Boost

1.25mH

-

7.5 mJ

VAC = 90V

VAC = 270V

SEPIC

Proposed M. SEPIC

Boost

SEPIC

Proposed M. SEPIC

Boost

IRMS [A]

1.74

1.61

1.21

0.74

0.75

0.2

Voltage[V]

337

229

400

592

400

400

Table 2. RMS-current- and voltage-stress.

Note that the SEPIC converter would require semiconductor devices rated at least 700V. The proposed approach can produce a 210Vdc output using semiconductor devices having same voltage rating as in a conventional boost converter. V. PRACTICAL DESIGN CONSIDERATIONS One of the nice features of the SEPIC converter is the inherent capability of limiting the inrush-current. The series capacitor is a relatively low value capacitor, which means that under start up conditions the capacitor will charge very fast to the line peak voltage and thereby reducing the inrush-current. Since a large capacitor is used in the Modified SEPIC converter, the issue of inrush-current has to be addressed. The following key-points have been considered during the circuit design: • Inrush current • Current limiting • Zero-current detection (both L1 and L2) • Output voltage measurement A. Inrush current

Table 1. Inductor-size comparison.

For the same minimum frequency the energy storage needed in the BCM Boost PFC converter is about 50 % larger than for the BCM Modified SEPIC PFC. Since the boost topology only uses one magnetic component compared to two in the Modified SEPIC it is not entirely fair only to use the energy storage as a measure of magnetic size - practical implementations should also be taken into account.

In low-power boost PFC converters the inrush current during start-up is usually bypassed by a heavy-duty diode that circumvents the branch with the inductor and the fast output diode, charging the output capacitor to the line peak voltage. DBypass L1

VIN

C1

D1 C2

L2

Q

RLoad VOUT

D2

B. Switch stress

At high line the performance of the Boost converter is superior. However, the boost converter is incapable of producing the required 210Vdc output. At low-line the Boost converter also exhibits the lowest stress in terms of rms current-stress, but the voltage that the Boost converter is switching is still the output voltage whereas for the Modified SEPIC this voltage is almost reduced with a factor of 2. Table 2 summarizes the results.

a) DBypass L1

VIN

D1 L2

Q C1

C2

RLoad VOUT

D2

b) Figure 4. a) Standard inrush scheme for boost converters. b) adopted scheme for the Modified SEPIC.

D4 2A05

D1 DIODE

L1 740uH D8 2A05

VAC1

D3 2A05 R15 6

Q1 IRF840

1N4148?? D13 D12 2A05

D11 2A05

R14 0.1

R7 1 D10 R8 1

VOUT D9 DIODE

R3 560k

R4 470k ZERO

C1 22uF + C4 22uF

R5 560k

+ 1N4148

R16 150k R6 470k

R11 560k

R1 150k

R12 470k

U1

MC33260

1N4744 D7 Q4 2N5961

+ C2 47uF

D2 DIODE

R10 12

R2 1

R9 8.2k

L2 250uH

L3 1

C3 0.33uF

VAC2

Feedback

Q3 2N5961

Q2 2N5961

Vcontrol

R13 22

D5 DIODE

Vcc

C9

Gate Drive

CT

GND

+ C8 47u

D6 Rsense

C6 2.7nF

C5 2.7nF

220nF

SYNC

1N4744

C7 220nF

Figure 5. Circuit diagram of the proposed converter prototype.

This is done to protect the fast output diode. Since the proposed converter operates with and output voltage that can be lower than the line voltage this scheme cannot be adopted directly (Fig. 4a). To solve this problem, the capacitor C1 is placed in the return path instead. Now it is no longer the output capacitor C2 that is charged to the line peak voltage but both C1+C2 (Fig. 4b). Using this scheme shown in Fig. 4b, give rise to another problem – measuring the output voltage. B. Output voltage measurements

The output voltage is no longer referenced to the ground potential but biased by the C1 capacitor voltage. In order to measure the correct output voltage a differential measurement has to be implemented. The complete schematic of a prototype of the proposed converter is shown in Fig. 5. The control chip (MC33260) used for this prototype has an internal reference currentsource that is used to control the output voltage. The output voltage is converted in to a current by the resistors R3 and R4 and compared internally with the reference current. Because of the biased output voltage a contribution from the VC1 voltage is added to the current through R3 and R4. This current is effectively subtracted by the current-mirror at the feedback pin (pin 1) implemented by Q2 and Q3 where the resistors R5 and R6 convert the VC1 voltage to the mirror current.

C. Current limiting

When the Rsense pin on the control chip (pin 4) is pulled below the ground potential (pin 6), an over current condition has occurred. This is a standard method for most BCM control ICs. For the Modified SEPIC converter an over current condition can also occur in the loop consisting of C1, D2, L2 and Q1. In order to solve this problem, a resistor, R14, is added in this loop. An over current condition can then be detected at the junction of R14 and C1 through the diode D10 connected to the Rsense pin. The control IC will react when the voltage drop over R14 becomes greater than the threshold voltage of D10. D. Zero current detection (both L1 and L2)

The control IC has an extra feature intended for synchronizing the PFC converter with the down-stream dc/dc converter. When the synchronize function is enabled the gate drive is disabled until both the zero-current condition has occurred and a synchronizing signal has been detected (pin 5). For the proposed converter, the synchronizing signal is generated when the zero-current condition of L2 occurs. When current is flowing through L2, the potential at the junction between D2 and D9 is clamped to the VC1 voltage through D2. When the zero-current condition for L2 occurs, a step in this potential follows (clamped through D9 to the output voltage). An extra branch in the current-mirror consisting of R11, R12 and Q4 detects this step. Zero current detection for L1 is achieved using the standard method for BCM boost PFC (sense resistor in the return path).

VAC=90V

VAC=270V

VAC=180V

Figure. 5. VC1 voltage and VOUT+VC1 Voltage at VAC=90V, 180V and 270V Measured data VAC VC1 (Mean) Max. Voltage stress VC1 (Mean) 90V 18V 240V 19V 180V 88V 315V 86V 270V 192V 420V 190V Table 3. VC1 capacitor voltages and Maximum semiconductor voltages. Measured and theoretical data.

Theoretical data Max. Voltage stress 229V 296V 400V

VI. EXPERIMENTAL RESULTS Efficiency versus AC-input voltage

A 210V, 100W prototype for the universal line input (90Vac-270Vac) has been tested to verify the performance of the Modified SEPIC. The full circuit schematic is shown in Fig. 5. In the steady-state analysis it is assumed that the capacitor voltage VC1 is constant during the line period. This is not through at low line voltage where the VC1 voltage has a very large ripple (±16V!) compared to the DC value (18V) (Fig. 5).

96 [%] 95 94 93 92 91 80 100 120 140 160 180 200 220 240 260 280 300 VAC

[V]

Figure 7. Efficiency of the experimental converter as a function of the ACline voltage.

This ripple will cause a slight decrease in PF and an increase in the switch rms-current but the large ripple voltage has little effect on the overall converter performance. a)

b) Figure 6. Experimental line currents. POUT=100W. a) VAC=120V, PF=0.998, THD=5.8%. b) VAC=270V, PF=0.968, THD=22.5%.

The line current distortion at high line is larger than expected by theoretical predictions. This is due to the fact the energy is transferred back to the input when the L2 inductor current down-ramp time is larger than the L1 inductor current down-ramp time. The energy is stored in the capacitance present at the rectifier-bridge at a voltage equal to the VOUT+VC1 voltage. The efficiency of the prototype for the full line range is shown in Fig. 7. Compared to other single-switch buck-boost type PFC converters reported in the literature, the efficiency achieved with the proposed converter is significantly higher (e.g. [1]). Normally the buck-boost type converters achieve efficiencies in the range of 80-90%.

The worst-case efficiency of 92.8% is achieved at low line (90VAC). In the area where the peak line voltage is close to the output voltage the performance is very good achieving efficiencies of over 95%. At high line the efficiency drops again, mainly because of the higher switching losses.

ACKNOWLEDGMENT Lars Petersen would like to say thanks to all at CoPEC for a wonderful stay during the spring of 2002. REFERENCES

CONCLUSION The BCM Modified SEPIC PFC converter is analyzed and experimental verified. The voltage stress can be reduced to a level comparable with the Boost PFC converter facilitating the use of low voltage rated semiconductors compared to other single-switch Buck-Boost derived converters. While the rms-current stress is still higher in the Modified SEPIC converter compared to the Boost converter, the switching stress is comparable. Comparing the magnetics of the above converters shows that the Boost converter needs more magnetic storage capability than the Modified SEPIC. The efficiency achieved with the experimental converter is comparable with the performance of the Boost converter but superior to other single-switch Buck-Boost derived converters.

[1] [2] [3] [4]

[5] [6]

J. Chen, C. Chang, “Analysis and Design of SEPIC Converter in Boundary Conduction Mode for Universal-Line Power Factor Correction Applications”, PESC 2001 record, pp.742-747. C.K. Tse, M.H.L. Chow, “Single Stage High Power Factor Converter Using the Sheppard-Taylor topology”, PESC 1996 record, pp.1191-1197. G. Spiazzi, L. Rossetto, “High-Quality Rectifier Based on Coupled-Inductor Sepic Topology”, PESC 1994 record, pp.336341. J.S. Lai, D. Chen, “Design Consideration for Power Factor Correction Boost Converter Operating at the Boundary of Continuous Conduction Mode and Discontinuous Conduction Mode”, APEC 1993 record, pp.267-273. L. Petersen, “Input-Current-Shaper Based on a Modified SEPIC Converter with Low Voltage Stress”, PESC 2001 record, pp.666671. J. Chen, D. Maksimovic, R. Erickson, “A New Low-Stress Buck-Boost Converter for Universal-Input PFC Applications”, APEC 2001 record, pp.343-349.

High Efficient Rectifiers

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Appendix B

B.

MathCad spreadsheet of the power-loss calculations of the experimental EWiRaC using average current mode control.

-215-

High Efficient Rectifiers

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Calculated losses for the experimental EWiRaC Pin := 530

Vac := 90

Vout := 185

3

fswitch := 70⋅ 10

EMI-filter: The losses in the EMI filter mainly in the conduction losses in the common-mode filter. The filter is realized as a double pi-filter using the leakage of the common mode choke as the differential mode inductance. Common mode choke: 2 stk. (2*2.7mH, 8A, Rdc= 22mOhm, Siemens) Pemi := 2 

530 

2

 ⋅ 0.022  90 

Pemi = 1.526

Bridge-rectifier: Bridge rectifier: GBU8J(8A-600V), Vto = 0.75, Rd = 20mOhm 

Pbrec := 2⋅  0.02⋅  

530 

2

 530⋅ 2 ⋅ 2     90⋅ π  

 + 0.75⋅ 

 90 

Pbrec = 9.34

Inductor: Inductor: Group Arnold A-083081-2, 81nH/N^2, single layer winding, N=60, Cu-diameter = 0.95mm. The hysteris losses are caluted, assuming that the mean voltage applied to the inductor, is 50V half time and 25V the other half (see Chapter 8, Fig.8.18). The flux change in these two cases are equal to 56mT and 23mT Rdc := 0.07

Pconduction := 0.07⋅ 

Phys56mT := 0.5 ⋅ 1.05

530 

2

  90 

Phys23mT := 0.5 ⋅ 0.26

Pinductor := Pconduction + Phys56mT + Phys23mT

Pinductor = 3.083

MOSFETs: Q1: STW45NM50, Rds=1.75*80mOhm (100C), g=20, Vth=4, Qgd=42nC, Ciss=3700pF, Rgate=6ohm, Vgate:14V

Rg := 6

Vgate := 14

−9

−9

Qgd := 42⋅ 10

Ciss := 3.7 ⋅ 10

g := 20

Vth := 4 I( n) :=

Pin Vac

 n⋅ π    1000 

⋅ 2 ⋅ sin

Vgate − Vth

Eturn_on1( n) := 0.5 ⋅ Vout⋅ I( n) Rg⋅ Ciss⋅ ln

 I( n)   Vgate − Vth −  g  

Qgd

Eturn_on2( n) := 0.5 ⋅ Vout⋅ I( n) ⋅ Rg⋅

Vgate − Vth −

I( n) g

Qgd

Eturn_off1( n) := 0.5 ⋅ Vout⋅ I( n) ⋅ Rg⋅

Vth +

I( n) g

 Vth + I( n)  g Eturn_off2( n) := 0.5 ⋅ Vout⋅ I( n) ⋅ Rg⋅ Ciss⋅ ln Vth 

Pturn_on := fswitch⋅

∑

( Eturn_on1( n) + Eturn_on2( n) ) 

∑

( Eturn_off1( n) + Eturn_off2( n) ) 

1000 1 

1000 

  

n = 1

Pturn_off := fswitch⋅

1000 1 

1000 

   

Pturn_on = 0.92



 

n = 1

Pturn_off = 2.06

∑

2 1000   1 π   90⋅ 2 π   530⋅ 2    ⋅ Pconduction := 0.08⋅ 1.75⋅ ⋅ sin n⋅ ⋅ sin n⋅    ⋅ 1 −  Vout  1000  90  1000     1000    n=1  

Pconduction = 2.02 PQ1 := Pturn_on + Pturn_off + Pconduction

PQ1 = 5

Q2+3: SPP20N60S5, Rds=1.75*190mOhm (100C) (Always on at 90Vac)



∑

2  π    90⋅ 2 π   530⋅ 2   ⋅ sin n⋅ ⋅ sin n⋅    ⋅   1000  90  1000    Vout  1000    n=1  

Pconduction := 0.5 ⋅ 0.19⋅ 1.75⋅ 

1

1000

⋅

PQ23 := Pconduction

PQ23 = 3.367

Transformer: The transformer losses are confied to the conduction losses of the two parallel primary windings. Transformer:RM12/N41, 6.5uH/N^2, N=43, bifilar wound, cu-diameter = 0.75mm, Rdc=50mOhm.

∑

2 1000   1 π    90⋅ 2 π   530⋅ 2    Ptransformer := 0.05⋅ ⋅ sin n⋅ ⋅ sin n⋅ ⋅   ⋅   1000  90  1000    Vout  1000    n=1  

Ptransformer = 1.013

Diode: The diode used is one half of a tandem diode from ST: STTH806TTI, Vth=1.3V, Rd=75mOhm (Maximum values at 25C) Vth := 1.3 Pdiode :=

500 185

Rd := 0.075

∑

2  π    90⋅ 2 π   530⋅ 2   ⋅ sin n⋅ ⋅ sin n⋅   ⋅   1000  90  1000    Vout  1000    n=1  



⋅ Vth + Rd⋅ 

1

1000

⋅

Pdiode = 5.032

High Efficient Rectifiers

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Appendix C C1.

Schematic of the circuit used for the simulation of the current in the EWiRaC during the mode transition

C2.

Schematics of the experimental EWiRaC using average current mode control with dc-shifted carriers

-221-

High Efficient Rectifiers

Blank page

-222-

Appendix C1

Schematic of the circuit used for the simulation of the current in the EWiRaC during the mode transition

-223-

High Efficient Rectifiers

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1k

R44

0

59k

R45

-

+

V21

10

V

60

+

2.8

-

-

+

-

0.01

0

1k

V16

V15

V2

+

0

R2

R14

7

R27

-

+

1meg

R10

8n

1.6n

2k

C5

-

+

S1

V

0

1k

5

VOFF=0.0V 0 VON=1.0V

C4

0

1k

100u

L1

S3

S4 -

V

0 V

VOFF=0.0V VON=1.0V

D3Dbreak

-

+

DbreakD4

0 VOFF=0.0V VON=1.0V + + +

-

+

0

V4 1

CLR

0

1k

4

R31

4 PRE

CLK

D

10k

3

2

TX2

6

5

-

+

1000u

C24

7474

Q

Q

U1A

5

0

V

2

V9

-

+

0

V11

Dbreak5000u C1 R7

D5

R22

R30

20

0

1k

40k -

+

-

0

V20 +

0

V17

PRE

1

CLR

3 CLK

2 D

4

6

5

7474

Q

Q

U4A

5

-

+

0

1k

5

0

V18

R36

0

1k

5 -

+

0

V23

4 PRE

R37

1

CLR

3 CLK

2 D

R38

6

5

0

8n

2

1

2

1

U7A

U6A

7432

7432

Revision:

-

Cadence Design Systems, Inc. 13221 S.W. 68th Parkway, Suite 200 Portland, OR 97223 (503) 671-9500 (800) 671-9505

0

1k

7474

Q

Q

U5A

3k

C21

3

3

V

January 1, 2000

V

Page 1

of

Page Size:

1

B

High Efficient Rectifiers

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Appendix C2

Schematics of the experimental EWiRaC using average current mode control with dcshifted carriers

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High Efficient Rectifiers

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5

4

3

2

1

D

2

D

D1 Zener_200V

2

D2

21

2 D3 Zener_200V

Gate Q3 R1 10

DIODE

C

21

1

1

C

1

1 C4 0.33u/630V

2

21

3

JP2

Q3

2 1

3

R3 5.6k

TX3

2

2 Q4

1

D4 DIODE

Source Q3

1

2

R2 100

Q2

2 1

1

Auto trafo (IN) 3

2

2

D5 DIODE

1

L1 Source Q2 1

300uH JP8

1

2

1

1

10

O/I

Gate Q2

1

3

Auto trafo (OUT)

R6 1

D6 DIODE

JP3

3

Gate Q1

B

R4 10

JP4 1

2 1

Vout GND OUT

1

Power IN

Q1 MOSFET N GDS

C OUT

2

R5

2

2 1

2

Inductor low

2

B

2*1000uF

2 47m

+ 2

Rsense

1

TX1

A

1

A

2*2.7mH

CX2 0.33uF

VAC

3

TX2 2*2.7mH

Title POWER

4 -

2

2

1 CX1 0.47u

D10 BRIDGE

Size A4 Date:

5

4

3

2

Document Number Tuesday, September 02, 2003

R ev Sheet

1 1

of

3

C44 100n 1

D

2

2

1

C43 100n

2

1

C41 VCC5 C42 100n 100n 1

1

C40 100n

2

5Vreg

2

2

2

2

2

C17

3

Vout

1

C100

390k

VAC

1

2

2

270k 1

V-

-

1

2

2

1

2 1 2 CAOUT

R29 120k 1

R30 120k

R31 120k

2

2

1

PWM Low R35 470

R36 470 1

R37 1

2

1

MC33078/MC

Disable A

D7 BZX79-B4V7

10k

Disable Title

D11 BZX79-B3V6

Size A4

Document Number

R ev

Rsense Date: 5

B

1

4

1

120k

470

1

1

8 V+

+

R23 1.8k

1

1

Q5 Q6 QbreakP QbreakP

Vout

2 2

2 1

U2A

OUT

2

2

470

O/I

1N4141

D13 2

A

R38 3.3k

R27 1

PWM High

VCC R34 270

2

R26

2

R32 12k

VCC5

3

TL1451A VCC5

JP9 1

120k 1

2 R22 120k

R21 120k

2

100n

R33 2.2k

2

1 R28

C56 1

390k

CAOUT

R18 DTC2

R13 15k

1

1

2

1u 2 100n

2

2

R20 120k

R12

1

1

VCC5 16 15 14 13 12 11 10 9

CT REF RT SCP 1IN+ 2IN+ 1IN2INOUT1 OUT2 DTC1 DTC2 Pwm1Pwm2 GND VCC

2

2

C55

1

DTC1 2

1

2

1

O/I

C49 470n

1 2

2

1

1

R16 120k

R17 120k 1

1 120k

B

1 2 3 4 5 6 7 8

Disable

C54

2

R25

C

U8

1

2

R19

R24

1 1

100n

Rsense

JP7

1

2 12k

C51 100n

1

R14 3.9k

C53

R9 47k

1 R11

2

C52

2

R103 1.2K

2

UCC3817

2 1

1

2 R15 1u 33k

1u

R102 1.5k

R10 6k

1

0.47n

1

DTC2

1

2.2n 2

C47

2.2n

2

C48 1.5n

1

2

16 GND DRVOUT C46 15 LMT VCC 14 1 CAOUT CT 13 CAI SS 12 2 MOUT RT 11 IAC Vsense 10 VAOUT OVP/EN 9 VFF VREF

1

12kC50 1

1 2 3 4 5 6 7 8

R101 2.7K

2

C45 1 1

2

C

DTC1

VCC

U11 R8

D12 BZX79-B4V7

120k

R100 1.5k

100u

Clock

2

3.9k

CAOUT

1

2

2

2

1

2

2

1

R99

2

100u/25V (921-233) R7

2

2

+

2

1

AUX.Supply

C39 100n

JP6 VCC

2

C38 100n 1

1

C37 100n

2

C36 100n

2

1

C35 100n

1

C34 100n

1

C33 100n 1

2 1

1

VCC

JP5 VCC GND

2

D

3

GND

4

1

5

4

3

2

Tuesday, September 02, 2003

Sheet

1 1

of

3

5

4

3

2

1

D

D

D8 VCC 1

100u/25V (921-233)

2

VCC5 1

VCC5

C57 100n

C30

+ 2

U9

1

2

DIODE

4

9 10 11 12 13

2

C

D

U13A 5

Q

6

CLK Q 1

1 3

CLR

3

Clock

PRE

U14A

PWM Low

2

VDD VB HIN HO SD VS LIN VCC VSS LO COM

74AC32

6 7 5 3 1 2

Gate Q2 VCC

C

Source Q2 Gate Q1

IR2110

74AC74

VCC5 U13B 4 6 5

PWM High

74AC32 D9

10

VCC5

DIODE

B

8 VCC5

C58 100n

+

C32

2

U10

1

Q

CLK Q 13

74AC74

D

100u/25V (921-233)

2

2

11

VCC1 9

1

B

CLR

VCC5 12

PRE

U14B

9 10 11 12 13

Disable

VDD VB HIN HO SD VS LIN VCC VSS LO COM

6 7 5 3 1 2

Gate Q3 VCC

Source Q3

IR2110

A

A

Title Size A4 Date: 5

4

3

2

Document Number Tuesday, September 02, 2003

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Appendix D Input-fields in the database.

Fig. D.1. Input interface to the "Data-table".

Below is a complete list of the input-fields in the data-base together with an explanation of these. -233-

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Data tabel: Reference ID: This is the unique identification number that each reference is assigned. In order for the database to work there can only be one reference per reference ID. Title: The title of the original input material Abbreviated title: The abbreviated title is mainly a help in the process where the link between the Data table and the Author table has to be established. ”Conference”: In the this database all of the references is taken from either APEC, PESC or INTELEC. This information is used when the original material is sought. ”Year of publication”: Publication year Pages in proceeding: Since the references in this database is taken from conference proceedings the information is helpful when the original material is sought. Analysis done by: In case of multiple users, information of who put in the data is useful. Summary: A short description of content. It is very useful to use words that characterize the approaches used. E.g. if the reference is describing a an interleaved boost converter, the word interleaved should appear in the summary. This facilitates a powerful search opportunity! Circuit diagram: A simplified circuit diagram of the approach described can be pasted into this field. Usually a scanned picture of the diagram from the original material is used. Even though this process is very time consuming, the outcome is very useful. Insert figure: This figure number refers to the figure number in the original material. Input line voltage: This refers to whether the design was intended for the high-line(185VAC270VAC), low-line(90VAC-135VAC) or for the universal input range(90VAC-270VAC). Power range: Low: In some applications a minimum load power is required – e.g. some single-stage configurations where the control of the voltage on the DC link capacitor is dependent on the load. -234-

Power range: High: Maximum output power. Max efficiency: Low-line: The efficiency of the converter at the lowest input voltage and at maximum output power. Max efficiency: High-line: The efficiency of the converter at the lowest input voltage and at maximum output power. Isolated: Does the approach secure galvanic isolation between the input- and the output voltage. Current waveform: Original when this database was started the Class D of EN61000-3-2 was dependent on the actual current waveform. So one of the possibilities of input in this field is whether it is a class D waveform, a class A waveform, ohmnic or sinusoidal. The ohmnic waveforms are the standard approach where the line voltage is used to shape the input current. If the line voltage is not a pure sinusoidal, the input current will also not be sinusoidal. If an internal sinusoidal reference is used, the waveform is of course sinusoidal. PF: Low-line: The Power Factor at low line. PF: High-line: The Power Factor at low line. Power switches: The number of power switches, e.g. 1 for all the single-stage single-switch approaches. Power rectifiers: The number of high frequency power rectifiers. Mains rectifiers: The number mains rectifiers. If a diode bridge is used the number will be 4, but if the approach is one that uses active rectifiers in stead of the passive bridge-rectifier the number will be 0. Magnetic components: The number of magnetic components, not including EMI filter components.

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High Efficient Rectifiers

Bandwidth: The band-width of the outer voltage loop. Low bandwidth is synonymous with a bandwidth much lower than the line frequency which is necessary not to regulate on the pulsating input power. High bandwidth is associated with regular fast response dc-dc converter. Acoustic noise: This field can be used to indicate whether the design is can give rise to problems regarding acoustic noise, e.g. switching frequencies in the audible area. Control complexity: An assessment of the complexity of the control circuit. Type of control: What kind of control is used. Switching frequency: Whether the switching frequency is constant or variable. Switching frequency: Min:: In case of variable frequency, the minimum switching frequency is noted. Switching frequency: Max:: In case of variable frequency, the minimum switching frequency is noted. Input topology: How can the input be characterized, e.g. boost, buck... Output topology: How can the input be characterized, e.g. boost, buck... Output voltage: Min: The minimum output voltage. In some case the output voltage is varied as a function of the load or the input voltage for example. Output voltage: Max: The maximum output voltage. In some case the output voltage is varied as a function of the load or the input voltage for example. Number of outputs: The number of output in case of multiple output converters Filter requirement: An assessment of the filter requirements. A buck-like input topology would require much larger input filter compared to a boost topology for example. Control-side: In the case that the approach is an isolated type, it is possible to state whether the controller is situated on the primary or the secondary side. -236-

Aux-supply needed: Is it simple to generate the auxiliary supply or does this require a separate converter. Level of finish: How well is the performance of the approach documented. Is by simulation or is the converter in production. Data complete: Just a reminder whether some of the data is incomplete Author complete: Just a reminder whether the authors are in the author table. DA-link complete: Just a reminder whether the Authors have been linked to the correct reference. Last edited:

Author: Author ID: Each author is assigned a unique identification number. First name: Middle name: Blank if there is none Last name: Place of work: Affiliation

DA-link: Reference ID: The reference ID from the data table Author ID: The author ID from the Author table.

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Author number: The number of which the authors are organized in the original material. Blank page

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Appendix E

CD-ROM:


The data-base (Microsoft Access)




PDF-version of all the references in the data-base




Thesis in PDF format

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ISBN 87-91184-25-8