CASE-STUDY: OVERCOMING RETURN-PATHDISCONTINUITY IN DDR3/GDDR5 MEMORY-CONTROLLER PACKAGES
Attiya
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Romi
Davy
Hany Fahmy High-Speed-Digital App. Expert Agilent Technologies Charles Jackson & Charlie Shu & Chen Wang Sr. Managers-SIEMC Nvidia Corporation Amolak Badesha Sr. R & D Manager Avago Technologies Ahmed M. Attiya Associate Prof. King Saud University Electrical Engineering Dept. Romi Mayder Sr. Signal Integrity Engineer Xilinx Inc. Davy Pissoort Prof. FMEC-KHBO, K.U. Leuven
Copyright © 2011 Agilent Technologies October 24, 2011
AGENDA A Typical HSD system Why do we need RF-tools for HSD? GHz Age for HSD Common SI/PI/EMI Problems for a Memory-Channel Design MOM best modeling technique for Packages & PCBs Return-Path-Discontinuity in Memory Controller Packages State of the Art EMI Workflow for: Trace-Emission from Packages: Memory Data-bus & PCB-Edge-Emission from PCBs: Memory SSO Noise
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Dramatic increase in HSD Gigabit Rates THANKS “STEVE JOBS” FOR APPLE-INNOVATIONS A look at Apple Macbook pro USB 3.0 HDMI DVI DP PCIe SATA DDR3
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Increased Density High-speed everywhere Pressure to Reduce cost
4.8 Gb/s 5 Gb/s 8 Gb/s 8.6 Gb/s 5 Gb/s 3 Gb/s 0.8-2.133 Gb/s
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Components of DDR3 System Memory Channel for Mobile applications (Notebook, Netbooks & Tablets) SODIMM R/C-F
SODIMM R/C-F
Memory-Controller-Hub PKG
MB for 2SODIMMs/channel in a Daisy-Chain topology
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Are we in the GHz Age? Not ICE-AGE!!! THANKS “XILINX INC.”
For DDR3-1333-2133Mb/s Models up to 15/20GHz 5
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On Controller-PKG: Break-out to Main TL Impedance Discontinuity & Tight-Coupling
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On MB: Vias & Via-Stub Discontinuity
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On MB: Surpentine for length-matching of bytelanes on MB: Real X-talk vs. pre-layout x-talk
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HOW CAN WE MODEL MULTILAYER PCB & PACKAGES DC UP TO 20-GHZ? BUILDING CONFIDENCE LEVEL
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Do MOM correlate to VNA measurements? THANKS “NVIDIA CORP. & GIGATEST LABS”
Courtesy of Gigatest
S-parameter modeling of PCB & package interconnects
N1930B Physical Layer Test System (PLTS) 1010
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PACKAGE MODELING FOR DATA-NETS CAPTURING: RETURN-PATH-DISCONTINUITY { RPD= REFERENCE-PLANE TRANSITIONS, SIGNAL/GND-PTH & ROUTING OVER VOIDS} BREAK-OUT/IN, SERPENTINE, VIA-STUBS, IMPEDANCE DISCONTINUITY & X-TALK
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What is Return-Path-Discontinuity?
Changing Reference-Planes
Overcoming the RPD with Stitching vias: How many? How far from Signal-vias? 12
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Is that all of Return-Path-Discontinuity?
Traces passing by Slots or Splits
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Routing of DQ signals from Bumps-Top to Layer-3 running as Symmetric-SL sandwiched between GND on Layers 2 & 4 DQ signals on Layer-3 as Symmetric-SL
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DQ signals @ Die-Bumps
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Moving from Layer-3 to Layer-6 through Signal-PTH to pickup the Balls DQ signals on Layer-6 routed between GND on layers 5
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DQ signals on Layer-3
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Impact of GND-PTH stitching: Proximity & # Original-Package: PKG1 with 15-GND-PTH
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Impact of GND-PTH stitching: Proximity & # New Proposal-Package:PKG2 with ONLY 3-GNDPTH
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Impact of GND-PTH stitching: Proximity & # Test-case Package: PKG3 with 0-GND-PTH
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Do we have traces crossing slots in the GND-plane?
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Eric Bogatin’s Blog: “When two adjacent signal lines transition from one signal layer, through a pair of planes, to another signal layer, the return current flows between the cavity formed by the planes. The impact of the return path discontinuity is strongest on which S-parameter term?” P1 P3
S11 S21 S31 P4 P2
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Impact of GND-PTH stitching on Insertion-Loss 0.5 dB delta @ 3GHz
PKG1: 15-GND-PTH PKG2: 3-GND-PTH PKG3: 0-GND-PTH
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Impact of GND-PTH stitching on Return-Loss 0-dB delta @ 3GHz
PKG1: 15-GND-PTH PKG2: 3-GND-PTH PKG3: 0-GND-PTH
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FEXT with 20dB delta for 0-GND-PTH and 10dB for 3-GND-PTH @ 3GHz PKG1: 15-GND-PTH PKG2: 3-GND-PTH PKG3: 0-GND-PTH
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NEXT with 30dB delta for 0-GND-PTH and 10dB for 3-GND-PTH @ 3GHz PKG1: 15-GND-PTH PKG2: 3-GND-PTH PKG3: 0-GND-PTH
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Comparison of Return-current on GND-L2
Original-PKG: 15-GND-PTH
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PKG3: 0-GND-PTH
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Comparison of Return-current on GND-L3 & L4
Original-PKG: 15-GND-PTH
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PKG3: 0-GND-PTH
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Comparison of Return-current on GND-L4
Original-PKG: 15-GND-PTH
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PKG3: 0-GND-PTH
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Comparison of Return-current on GND-L5
Original-PKG: 15-GND-PTH
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PKG3: 0-GND-PTH
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WHAT IS THE IMPACT OF THE MCH-PKG FOR DDR3 TWO-SODIMMS/CHANNEL
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SODIMM SURFACE-MOUNT CONNECTOR Sparameter measurements AND/OR EMpro modeling
• 86100C DCA-J/TDR
EMPro Modeling of a USB Connector
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LINEAR-AC Analysis for the PKG3 with 0-GND-PTH Compared to PKG1 with 15-GND-PTH Excite one-bit & Watch others @ SDRAM on DIMM2 PKG1: ORIGINAL PACKAGE
PKG3: RPD IMPACT ON X-talk
5dB difference @ 1.33GHz in x-talk between 15-GND-PTH & 0-GND-PTH 31
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What is the eye-mask for DDR3 SDRAM device?
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Comparison of Original-PKG (15-GND-PTH) with Test-PKG (0-GND-PTH) @ 1.33GB/s 15-GND-PTH
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0-GND-PTH
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Setup/Hold DDR3-1.33GB/s margins
15-GND-PTH Worst-case Setup-Margin is 95ps
0-GND-PTH FAIL-FAIL-FAIL-FAIL
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Lack of GND-PTH on test-PKG FORCES Down-bining R/C-F_F Configuration down to 1.067GB/s operation Medium-2-High-Risk @ 1.067GB/s as worst Margin is -30ps
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Cost-Reduced Package of 3-GND-PTH enables operation @ 1.33GB/s worst-case Setup-Margin is +55ps (loss of 40ps compared to Original Package)
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INNOVATIVE EMI WORKFLOW USING TOP-NOTCH H/W & S/W TECHNOLOGY
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Current Solution! Put on band-aid to stop the radiation…. It is hardly optimal, does not always work, and costs lot of money
Copper band-aid
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R4N Suppressor band-aid
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of EMI EComplexity M I SYSTEM B U Dproblem GET Trace-Emission PCB-Edge Emission due to PDN noise Cable Emission carrying common-mode noise
Connectors
High-speed PCB
High-speed IC
* From EM-Scan Measurement of GPU Board
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TRACE EMISSION DUE TO RPD ON PACKAGE 40
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PKG-Antenna-Parameters Comparison of PKG1 (15-GND-PTH) vs. PKG3 (3-GND-PTH)
15-GND-PTH
3-GND-PTH
Radiated Power: 37-uwatts vs. 220-uwatts (6X) Maximum Intensity: 5u-watts/Steradian vs. 42-uwatts/Steradian (8X) Angle of U-max: 165-degrees vs. 140-degrees Antenna-Gain of -19dB vs. -11dB (8dB difference) 41
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PCB-EDGE EMISSION DUE TO SSO NOISE Copyright © 2011 Agilent Technologies 42
October 24, 2011
Combining Measured Icc(t) SSO Noise Source Extraction
with FDTD simulations to study the critical on-boarddecaps Power Delivery Network
Current Probe @ VddQ pins
Drivers
Channel
Receivers
• SSO
current is obtained by a combined simulation of the power delivery network model and the memory IO channel model Copyright © 2011 Agilent Technologies 43
October 24, 2011
SSO Noise Source on Top Layer
Noise sources
IC
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Decaps on Bottom Layer
decaps
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Current Density at 0.5 GHz (1)
Without Decaps 46
With Decaps Copyright © 2011 Agilent Technologies October 24, 2011
Far-Field Radiation at 0.5 GHz
With Decaps
Without Decaps
Reduction of 3-4 dB 47
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Far-Field Radiation at 1GHz
With Decaps
Without Decaps
Reduction of 3-4 dB 48
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Simulation Time With CUDA (GPU-Acceleration)– oneGPU card: half-a-day With Four-GPU cards: 1-2 hours Without CUDA – more than one week (estimated) 49
Copyright © 2011 Agilent Technologies October 24, 2011
Conclusive Remarks & NEXT-STEPS No Single Methodology/Technique can do it all: MOM is best for S-parameter modeling of PCBs and Packages VNA Measurements & FEM-Modeling for Connectors/Cables Combine all models (simulated and measured) with I/O-Models (BSIM4, , Encrypted Hspice, IBIS, IBIS-AMI) using Transient-Convolution for DDR eye-diagram compliance testing
Antenna-Gain Parameter for developing EMI-Guidelines of PCBs & Packages FDTD is best for wide-band phenomena like SSO noise Emission
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