Fundamentals of Computer Systems

Fundamentals of Computer Systems A Single Cycle MIPS Processor Stephen A. Edwards and Martha A. Kim Columbia University Fall 2012 Illustrations Copy...
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Fundamentals of Computer Systems A Single Cycle MIPS Processor

Stephen A. Edwards and Martha A. Kim Columbia University

Fall 2012 Illustrations Copyright

© 2007 Elsevier

The Datapath The lw Instruction The sw Instruction R-Type Instructions The beq Instruction The Controller Instruction Encoding The ALU Decoder The Main Decoder The j Instruction Processor Performance The Critical Path

Let’s Build a Simple Processor

Supported instructions: É

R-type: and, or, addu, subu, slt

É

Memory instructions: lw, sw

É

Branch instructions: beq

Version 2.0: É

I-type: addiu

É

J-type: j

MIPS State Elements This is the programmer-visible state in the ISA

CLK

CLK

PC'

PC

32

32 32

A

RD

Instruction Memory

5 32 5

5 32

A1 A2

CLK WE3

RD1 RD2

WE 32 32

32

A3 WD3

Register File

32

A

RD Data Memory WD

32

ALU Interface and Implementation A

B N

A

N

ALU

B N

N

3F

N

Y

0

1

N

F2

N

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

A&B A|B A+B A&B A|B A−B A < B (slt)

Cout

+ S

[N-1]

N

N

N

N

0

0 0 0 0 1 1 1 1

1

Func.

2

F0

3

F1

Zero Extend

F2

2 N

Y

F1:0

Datapath Elements for the lw Instruction Fetch instruction from instruction memory: Send the PC to the instruction memory’s address

CLK

CLK PC'

PC

Instr A

RD

Instruction Memory

A1

CLK WE3

WE

RD1 A

A2 A3 WD3

RD Data Memory WD

RD2 Register File

lw rt, offset(base) LW 100011

base

rt

offset

Datapath Elements for the lw Instruction Read the base register

CLK

CLK 25:21

PC'

PC

A

RD

Instr

Instruction Memory

A1

CLK WE3

WE

RD1 A

A2 A3 WD3

RD Data Memory WD

RD2 Register File

lw rt, offset(base) LW 100011

base

rt

offset

Datapath Elements for the lw Instruction Sign-extend the immediate

CLK

CLK PC'

PC

A

RD

Instr

25:21

A1

CLK WE3

WE

RD1 A

Instruction Memory

RD Data Memory WD

A2 RD2 A3 Register WD3 File

SignImm

15:0

Sign Extend

lw rt, offset(base) LW 100011

base

rt

offset

Datapath Elements for the lw Instruction Add the base register and the sign-extended immediate to compute the data memory address ALUControl2:0

PC

A

RD

Instr

25:21

Instruction Memory

A1

WE3

RD1

A2 RD2 A3 Register WD3 File

SrcB

CLK Zero

SrcA

ALU

CLK PC'

010

CLK

ALUResult

WE A

RD Data Memory WD

SignImm 15:0

Sign Extend

lw rt, offset(base) LW 100011

base

rt

offset

Datapath Elements for the lw Instruction Read data from memory and write it back to rt in the register file RegWrite CLK PC'

PC

A

RD

Instr

Instruction Memory

25:21

20:16

A1 A2 A3 WD3

ALUControl2:0

1 WE3

010

RD1 RD2

SrcB

Register File

CLK Zero

SrcA

ALU

CLK

ALUResult

WE A

RD Data Memory WD

ReadData

SignImm 15:0

Sign Extend

lw rt, offset(base) LW 100011

base

rt

offset

Datapath Elements for the lw Instruction Add four to the program counter to determine address of the the next instruction to execute RegWrite CLK PC

A

RD

Instr

Instruction Memory

25:21

A1 A2

20:16

A3 WD3

+

PC'

ALUControl2:0

1 WE3

010

RD1 RD2

SrcB

Register File

CLK Zero

SrcA

ALU

CLK

ALUResult

WE A

RD Data Memory WD

ReadData

PCPlus4

4

SignImm 15:0

Sign Extend

Result

lw rt, offset(base) LW 100011

base

rt

offset

Additional Elements for sw Read rt from the register file and write it to data memory

RegWrite CLK PC'

PC

A

RD

Instr

Instruction Memory

25:21

20:16 20:16

A1 A2 A3

+

WD3

ALUControl2:0

0 WE3

010

RD2

SrcB

ALUResult

WriteData

Register File

MemWrite CLK

Zero

SrcA

RD1

ALU

CLK

1 WE

A

RD Data Memory WD

ReadData

PCPlus4

4

SignImm 15:0

Sign Extend

Result

sw rt, offset(base) SW 101011

base

rt

offset

Additional Elements for R-Type Instructions Read from rs and rt Write ALUResult to rd (instead of rt)

PC'

PC

A

RD

Instr

Instruction Memory

25:21

20:16

A1

RegDst

1 WE3

A2

0 SrcB

RD2

+

WriteReg4:0

CLK

Zero

1

15:11

MemWrite

varies SrcA

A3 Register WD3 File

PCPlus4

0

RD1

20:16

4

ALUSrc ALUControl2:0

1

ALU

RegWrite CLK

CLK

MemtoReg 0

0 WE

ALUResult

WriteData

A

RD Data Memory WD

ReadData

0 1

0 1

SignImm 15:0

Sign Extend

Result

addu rd, rs, rt SPECIAL 000000

rs

rt

rd

ADDU 00000100001

Additional Elements for beq Determine whether rs and rt are equal Calculate branch target address PCSrc

CLK PC'

PC

A

RD

Instr

Instruction Memory

25:21

20:16

A1

WE3

A2 RD2 A3 Register WD3 File

0 SrcB 1

15:11

Sign Extend

ALUResult

WriteData

0

MemtoReg x

WE A

RD Data Memory WD

ReadData

0 1

0 1

SignImm 15:0

MemWrite CLK

Zero