Fujitsu 90nm Technology Introduction. Fujitsu Limited

Fujitsu 90nm Technology Introduction Fujitsu Limited. 2005.08 Leading-edge Technology Fujitsu 90nm Fujitsu Advanced Technology 1 All Rights Rese...
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Fujitsu 90nm Technology Introduction Fujitsu Limited. 2005.08

Leading-edge Technology

Fujitsu 90nm

Fujitsu Advanced Technology

1

All Rights Reserved, Copyright FUJITSU LIMITED 2005

Leading-edge Technology

Fujitsu 90nm

Fujitsu CMOS Technology Roadmap

Physical Gate Length (nm)

1000 180-nm 180-nm

500 200

130-nm 130-nm

90-nm 90-nm

65-nm 65-nm

45-nm 45-nm

CS80 / 80A CS90A

100

CS100/CS100A (90nm) „ L actual=40-80nm „ SiOC(k:2.9) low-k „ Dual Damascene Cu

CS100A CS200A

CS90

50 CS100HP

20 10 1998 2000

CS200

2002

2004

2006

2008

CS200/CS200A (65nm) „ L actual=30-50nm „ NCS (Nano-Clustering Silica) 2010

Year (Production Start) 2

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Operating Frequency

90nm Technology Lineup

CS100HP High-End MPU

CS100A_LL Mobile

CS100A_G*

Graphics

Network

Consumer

FPGA *Supply *Supply only only technology technology

Power Consumption Fujitsu Proprietary and Confidential

4

Leading-edge Technology

Fujitsu 90nm

Proven track records of 90nm complex design and products (1) - In House Application -

3

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Leading-edge Technology

Fujitsu 90nm

Proven track records of 90nm complex design and products (2) - COT Customers Chip Size (mm2)

High performance products ¾ PC CPU (Transmeta) ¾ Large scale FPGA (Lattice) etc Low power products ¾ Multimedia Processor ¾ Digital AV product etc

High End

350-450

Low Power

250-350 200-250 100-200 50-100 20-50 0

5 10 Tape Out Number

30 30 Product Product Taped Taped Out Out 200 200prototype prototypewafers wafersdelivered delivered 4

All Rights Reserved, Copyright FUJITSU LIMITED 2005

Leading-edge Technology

Fujitsu 90nm

„

„

Fujitsu 90nm - Key Features

High Performance Transistors „

Advanced Lithography and Etch technology to achieve 40nm Gate Length

„

Low Temperature Process for Shallow Junction

„

Process Optimization for High Carrier Mobility

High density 6T SRAM „

sub-1um2 cell is available

„

*Dual Damascene Cu + Full Low-k

„

*Assy and packaging technology „



Full Low-K + Pb free bump + Large pin count + Large die size**

* High performance and high reliability. ** This combination can realize by only Fujitsu in the world. 5

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Leading-edge Technology

Fujitsu 90nm

Ultra-Thin Gate Insulator / Mobility Improvement

1nm-thick Gate Oxide Normalized gm (∝ mobility)

Poly-Si

Surface Cleaning 2.0E-3

40% increase

1.5E-3

Nitrided-SiO2

After optimize

1.0E-3

5.0E-4

Si substrate

Before 0.0 -0.5

1.5

3.5

5.5

Electric Field [MV/cm]

6

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Leading-edge Technology

Fujitsu 90nm

Advantage of Fujitsu 90nm technology Fujitsu is the World’s No.1 Leading Edge Process Technology Supplier

„

One customer’s benchmark results show Fujitsu’s technology has higher performance and low power consumption compared with one of the standard foundry technologies

Speed and Power Comparison

Foundry A

Fujitsu

Speed

100

125

Active Power

100

75

Stand-by Power

100

21

7

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Leading-edge Technology

90nm LL Transistor Benchmark

Fujitsu 90nm

* for nMOS transistor

100

UHS

Standby Current

small

Ioff(nA/um)

big

10

HS

1

Foundry A

Low-Vt

90LP, 1.2V

0.1

CS100A_LL, 1.2V Std-Vt

0.01

Fujitsu

STD LL

Hi-Vt 0.001 0

200

400

600

800

1000

Ion(nA/um) slow

Switching Speed

fast

CS100A_LL process covers a broad range of requirement for both high performance and low leakage current.

8

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Leading-edge Technology

Fujitsu 90nm

Power/Delay estimation result Assumption Logic : 1.7Mgate, SRAM : 8Mbit Assumption 400 Delay Time

500

350

400

300

300

250

Delay Time [psec]

600

POWER [mW]

・Logic : 1.7Mgate, SRAM : 8Mbit

200

200 Stand-By power Operation power

100 0

・Delay time: Tj=25℃, VDD=1.2V, Process Typical ■Active power is dominant for total power consumption. Roughly half of 130nm node with 90nm node.

150

■Total power benefit by evolution.

100

■Excess Low Leak targeting costs delay time penalty.

CS90A CS100A A-company 130nm node

・Power: Tj =85℃, VDD=1.3V, Process Typical

90nm node

9

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Leading-edge Technology

Fujitsu 90nm

Cu/Low-k Integration Technology ‹Fourth-generation Cu wiring LSI ‹Leading-edge Low-k technology

Wiring Pitch (um)

1.0

0.5 0.4 0.3 0.2

0.1

CS80 *Cu-6 Layer *FSG(k=3.6)

0.18um

CS90A *Cu-7 Layer *Partial Low-k

0.13um

CS100/100A *Cu-10 Layer *Full Low-k

90nm

CS200/201 *Cu-11 Layer *Full Advanced Low-k

65nm

Technology Node 10

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Leading-edge Technology

Fujitsu 90nm

6T SRAM Cell





1.88

4.18um2

1.40

1.20

1.65

2.22

Conventional Type:Symmetrical Type: For Bigger size Verified

(um)

1.20

0.95

0.655

1.98um2

1.14um2

0.917um2

16 - 512Kbit

32K - 8Mbit

11

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Leading-edge Technology

Fujitsu 90nm

90/65nm 300mm New Fab.

Outlook of new fab.

Mie New Fab. Milestone

World first semiconductor fab. with a micro vibration control & seismically isolated structure

„

Apr. 21, 2004 Ceremony for sanctifying ground

„

Nov. 20, 2004 Completion of construction

„

Apr. 1, 2005 Formal operation starts

„

Sept. 9, 2005 Volume shipment

鉛プラグ (径φ120∼φ150)

積層ゴム

ベースポット

すべり面(テフロン加工)

内部ゴム(基礎の回転角を吸収) ベース (ベースポットにはめ込み式)

1FL

すべり板

12

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Leading-edge Technology

Fujitsu 90nm

300mm foundry capacity for 90nm/65nm Mie Mie 300 300 mm mm Fab Fab Advanced Advanced technology technology production production 2005/2H~ 2005/2H~

Akiruno Akiruno TC TC 200mm 200mm Advanced Advanced technology technology development development and and production production

300mm Fab Akiruno TC

30000

15000

10000 20000

5000 10000

Capacity (300mm/month)

Capacity (200mm/month)

40000

0 2004/2H

2005/1H 2005/2H

2006/1H

2006/2H 2007/1H

2007/2H

Year 13

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Leading-edge Technology

Fujitsu 90nm

„ „

Extensive IP line up

Customers are satisfied with the Si verified IP. Fujitsu provide extensive IP line up.

High Speed I/O STD I/O

SRAM

I/F (USB 2.0 etc) PLL

AD/DA

* Chip photo is not related on each IP. 14

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Fujitsu Foundry Services

15

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Fujitsu launched pure foundry business Fujitsu announced “ Fujitsu launched pure foundry business as primary to keep pace with market shift from ASIC to foundry . Fujitsu made foundry business division to focus the foundry business in 2004 June.

This advertisement is published in “Nikkei electronics 2004 12-6, page 100-101” , which is one of the major magazine of electronics in Japan. In 2005 April, Fujitsu has released the similar advertisement in U.S.A.

16

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Changing Business Environment ‹Customers’ needs are changing with evolution in LSI development Customers Customers require require integrated integrated design design and and engineering engineering and and flexible flexible manufacturing manufacturing capabilities capabilities

Strong Appeal as New IDM Vendor System System Design Design

System System Design Design

Logic Logic Design Design

Logic Logic Design Design

Physical Physical Design Design

Foundry Foundry

SoC SoC

ASIC ASIC Manufacturing Manufacturing Technology Technology

New business opportunity

Fujitsu’s conventional LSI business

(Technology & Engineering Service) 17

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Full Turnkey Foundry Service option Customer can select service and biz model. Wafer process

Sort test

Sort test Wafer process

Packaging

Packaging

Mask making

Mask making

Lsi Test

Lsi Test

Backend Design Service Turnkey Foundry Service

Traditional Foundry Service 18

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EDG in Japan FIM (Miyagi) Assembling

Iwate Plant [Memory, Microcomputer, Logic]

FIM (Aizu) Assembling & Test

Akiruno TC (Tokyo) R&D (90nm∼)

Aizu Wakamatsu Plant

FIM (Gifu) Assembling & Test

*:300mm FAB 90nm/65nm

FIM (Kagoshima) Assembling & Test

FIM : Fujitsu Integrated Microtechnology

Mie Plant

19

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SiExpressTM SiExpressTM is a pre-production service where customers save cost by sharing mask sets and wafer, called multi-projectwafer. SiExpressTM service provides completely consistent samples which enable your real product’s performance evaluation. Sample forms •Bare Chips •Package chips 20

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Fab information system ~FF -eSERVE ~FF-eSERVE FJ-WAN

Secured accessibility for world wide customers

Iwate

Wakamatsu Akiruno Mie

Fire wall

FJ foundry

Internet

Fire wall

Customers can access FJ foundry information through the Internet with high security 21

World wide customers

All Rights Reserved, Copyright FUJITSU LIMITED 2005

Fab information linked customer’s PO

FF -eSERVE FF-eSERVE

Received Received PO PO

The fab information system of your own

•• Engineering Engineering docs docs Query

•• Lot Lot history history •• Daily Daily WIP WIP •• Inprocess Inprocess data data •• WAT WAT data data •• SORT SORT data data •• Wafer Wafer Map Map •• Wafer Wafer Shipping Shipping info info •• Assembly Assembly WIP WIP •• LSI LSI Shipping Shipping info info

Info

Customer

Customers can get FJ foundry information linked PO 22

All Rights Reserved, Copyright FUJITSU LIMITED 2005

Why Fujitsu foundry? Fujitsu launched foundry biz. Provide 300mm capacity for “Foundry Customer” Customer can enjoy the Fujitsu’s high performance and low leakage 90nm technology. Matured 90nm device production From high end to low power devices Higher yield than other fab. Extensive IP line up

23

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Leading-edge Technology

Fujitsu 90nm

EDA tool vendor’s support

Cadence Foundry Program http://www.cadence.com/partners/foundry _program/index.aspx?lid=foundries

Synopsys SPV Cafe http://www.synopsys.com/cgi-bin/svp/lib/svp.cgi

24

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Standard Cell 1. Standard cell 1-1. CS100A_LL Tr.

LL

STD

HS

9grid

Now

Now

Now

12grid

Now

Now

Now

HiVT

STD

HS

3Q / 2005

3Q / 2005

NA

Cell Height

1-2. CS100HP Tr. Cell Height 9grid

LL : Low-Leak Tr. , STD : Standard Tr. , HS : High-Speed Tr. , HiVT : High-Vth Tr.

Fujitsu Proprietary and Confidential

2

I/O Cell 2. I/O cell 2-1. CS100A_LL Interface

Status

Note

3.3V LVCMOS

Now

(63cells)

for 3.3V Process

3.3V PCI

Now

( 5cells , 66/33MHz)

for 3.3V Process

SSTL-2

Now

( 5cells , 400Mbps)

for 3.3V Process

LVDS

4Q / 2005

( 5cells , 333MHz)

for 3.3V Process

2-2. CS100HP Interface 2.5V LVCMOS

3Q / 2005

Fujitsu Proprietary and Confidential

Status

Note

( TBD )

for 2.5V Process

3

Memory 3. SRAM / ROM / Register File CS100A_LL Type

1RW SRAM 2RW SRAM ROM 1R1W Reg. File 2R2W Reg. File

Tr. Type ( Cell / Peripheral ) LL / LL LL / STD LL / HS LL / LL LL / STD LL / HS LL / LL LL / HS LL / LL LL / STD LL / HS LL / LL LL / STD LL / HS

CS100HP Status Now Now Now Now Now Now Now Now Now Now Now Now Now Now

Tr. Type ( Cell / Peripheral ) HiVT / HiVT HiVT / STD HiVT / HS HiVT / HiVT HiVT / STD HiVT / HS HiVT / HiVT HiVT / STD HiVT / HiVT HiVT / STD HiVT / HS HiVT / HiVT HiVT / STD HiVT / HS

Status On demand On demand On demand On demand Now *1 On demand On demand On demand On demand On demand On demand On demand On demand On demand

*1 : Virage’s IP LL : Low-Leak Tr. , STD : Standard Tr. , HS : High-Speed Tr. , HiVT : High-Vth Tr.

Fujitsu Proprietary and Confidential

4

I/F Macro, ARM I/F Macro Macro

Functions

Specifications

Design completion

Evaluation completion ( SiliconProven )

1

USB2.0 Device

USB2.0(HS) Device PHY

Now

2005/5/E

2005/8/E

Development

2

USB2.0 Host

USB2.0(HS) Host PHY

TBD

TBD

TBD

Development

3

USB2.0 OTG

USB2.0(HS) OTG PHY

Now

2005/7/E

2005/8/E

Procurement

4

IEEE1394.a

IEEE1394.a AV-protocol only (LINK + PHY)

Now

2005/6/E

2005/11/E

Development

S-ATA 1.5G Host PHY

2005.6.30(PHY)

2005.10.31(PHY)

2006.3.31(PHY)

Procurement

S-ATA 3.0G Host PHY

TBD

TBD

TBD

PCI-Express 2.5G Endpoint PHY

2005.5.31(PHY)

2005.10.31(PHY)

2006.3.31(PHY)

Development

DDR2 400~533Mbps x 32

2005/5/E

2005/6/B

2005/9/E

Development

DDR2 400~533Mbps x 16

2005/5/E

2005/8/B

2005/11/E

Development

DDR2 ~800Mbps x 16

2005/9/B

2006/4/B

2006/8/E

Development

UWB

TBD

TBD

TBD

Specifications

Design completion

5 6 7

S-ATA PCI-Express

8 9

DRAM Controller

10 11

UWB

Note (Procurement or Development)

TBD

Joint Development

ARM Macro 1 2 3 4

ARM

Functions ARM7TDMI-S

Now

ARM926EJ-S

Now

ARM946E-S

Now

ARM1176JZF-S

Now

Fujitsu Proprietary and Confidential

Evaluation completion ( SiliconProven )

Note (Procurement or Development)

We will deliver the library two months after the business fixation.

5

PLL, DLL Macro

Functions

Specifications

Design completion

Evaluation completion ( SiliconProven )

Note (Procurement or Development)

1

Fout:100-150MHz, Fin:12.5-150MHz, N=1-8, Power:1mW

NOW

NOW

NOW

Development

2

Fout:150-200MHz, Fin:10-200MHz, N=1-15, Power:1mW

NOW

NOW

NOW

Development

3

Fout:200-230MHz, Fin:10-200MHz, N=1-16, Power:1mW

NOW

NOW

NOW

Development

4

Fout:100-300MHz, Fin:8-150MHz, N=2-38, Power:3mW

NOW

NOW

NOW

Development

5

Fout:250-600MHz, Fin:8-200MHz, N=2-66, Power:4mW

NOW

NOW

NOW

Development

6

Fout:400-800MHz, Fin:10-50MHz, N=12-40, Power:6mW

NOW

NOW

NOW

Development

7

Fout:500-900MHz, Fin:6.25-150MHz, N=6-96, Power:6mW

NOW

NOW

NOW

Development

8

Fout:600-1200MHz, Fin:6-80MHz, N=6-80, Power:7mW

NOW

NOW

NOW

Development

Fout:20-32MHz, Fin:0.3-50MHz, N=30-66, Power:4mW

2005/6/E

2005/6/E

2005/11/E

Development

10

Fout:50-62MHz, Fin:0.3-50MHz, N=12-66, Power:4mW

2005/6/E

2005/6/E

2005/11/E

Development

11

Fout:90-150MHz, Fin:1.5-50MHz, N=32-66, Power:4mW

2005/6/E

2005/6/E

2005/11/E

Development

12

Fout:1200-1500MHz, Fin:24-100MHz, Power:10mW

2005/12/E

2005/12/E

2006/3/E

Development

13

Fout:1500-1800MHz, Fin:24-200MHz, Power:12mW

2005/12/E

2005/12/E

2006/3/E

Development

14

Fout:24.576MHz, Fin:24KHz, N=1024, Power:10mW (High Multiply)

2005/6/E

2005/7/E

2005/12/E

Development

15

Fout:150-300MHz, Fin:18.75-37.5MHz, N=8, Power:15mW (SSCG) (The available Fout[MHz]/Fin[MHz] pair is only five cases or 150/18.75,192/24,200/25,266/33.25,300/37.5)

2005/8/E

2005/8/E

2005/9/E

Development

Specifications

Design completion

Evaluation completion ( SiliconProven )

NOW

Now

Now

9

PLL

*Analog Capacitor is 3.3V Poly-Diffusion capacitor. Macro 1 DLL(Analog)

Functions Number of TAP:16, DQS≦133MHz, Power:10mW *Analog Capacitor is 3.3V Poly-Diffusion capacitor.

Fujitsu Proprietary and Confidential

6

Note (Procurement or Development) Development

ADC, DAC Macro

Functions

Specifications Design completion

Evaluation completion Note ( SiliconProven ) (Procurement or Development)

Note VDD=3.3V(typ)

1

10bit 1MS/s

now

now

now

Development

Planning of Improvement Now Designing (with Input sw)

2

10bit 1MS/s

now

now

2005.9.E

Development

With 17ch Input Switch

3

12bit 1MS/s

2005.7.E

2005.8.E

2005.12.E

Development

Single Input

4

ADC 6bit 108MS/s

now

now

2005.7.E

Development

Single Input

5

8bit 54MS/s

now

now

2005.7.E

Development

Single Input

6

10bit 30MS/s

now

now

2005.11.E

Development

Single Input

7

10bit 80MS/s

now

now

2005.10.E

Development

FMSL Differential Input

8

10bit 150MS/s

2005.7.E

2005.9.E

2006.1.E

Development

FMSL Differential Input

9

8bit 300kHz

now

now

now

Development

Voltage Output Low Power

10

8bit 1MHz

now

now

2005.7.E

Development

Voltage Output

11

10bit 300kHz

now

now

2005.7.E

Development

Voltage Output Low Power

12

10bit 1MHz

now

now

2005.7.E

Development

Voltage Output

13 DAC 10bit 30MHz

now

now

now

Development

Current Output VDD=2.5V

14

10bit 30MHz

now

now

2005.7.E

Development

Current Output With built-in resistance

15

10bit 54MHz

now

now

2005.11.E

Development

Current Output

16

10bit 110MHz

2005.10.E

2005.10.E

2006.1.E

Development

Current Output

Fujitsu Proprietary and Confidential

7

(End of Presentation)

Fujitsu Proprietary and Confidential

8