FPGAs AND ASICs FOR REAL WORLD LOW POWER APPLICATIONS ACAL offers FPGA/ASIC products from Achronix, eASIC and Actel. These products span the market from low power portable equipment, real world mixed signal operation, through to very high speed, complex telecom solutions and datapath applications. Achronix FPGAs are capable of addressing high speed applications making them particularly suitable for the telecoms and data processing markets. eASIC‟s breakthrough technology enables Nextreme‟s New ASICs to provide you with compelling low cost-ofownership both for fast prototyping and high volume production. Actel specialises in manufacturing very low power flash FPGAs and mixed signal devices in micro-miniature packaging ideally suited to battery powered portable equipment applications. ACTEL FUSION FPGAs Real world applications demand real world solutions. Actel has tackled this by offering it Fusion family of flash mixed signal FPGAs in a low power process. Actel Fusion integrates configurable analogue, large flash memory blocks, comprehensive clock generation and management circuitry, and highperformance, flash-based programmable logic in a monolithic device. Actel‟s innovative Fusion architecture can be used with the Actel soft MCU core, as well as with the performance maximised 32bit ARM Cortex-M1 and CoreMP7 cores. Fusion is the definitive mixed signal FPGA platform. Fusion supports an integrated A/D converter, eliminating the need for external mixed-signal support ICs. With resolutions up to 12 bits and sampling up to 600ksample/s, this configurable a/d converter supports a broad application space. When customers choose to use the calibration option with the Fusion device, they can achieve better than 1% accuracy, which makes it ideal for system management applications where this level of accuracy is required. Low power Built on a low-power, high performance flash process, Fusion provides industry-leading low static and dynamic power. Fusion also offers several sleep and standby modes of operation to further extend battery life in portable applications. The Fusion real-time counter (RTC) offers a wide variety of functionality: sleep, standby, periodic wake-up, and low-speed/low power operation. The addition of both a 1% RC oscillator and two-pin crystal oscillator circuit eliminates the need for expensive external clock sources. Fusion allows customers to integrate several functions into a single-chip solution with lower overall system power. In addition to an overall reduction in chip count, the integration of several functions within Fusion prevents the introduction of lower accuracy and noise that comes with a multi-chip solution. All the above factors add up to a lower power profile that lends itself

to other benefits, such as higher signal integrity and lower overall system cost. One chip is all you need Until now, system designers were forced to choose costly and spaceconsuming discrete analogue components with programmable logic or mixedsignal ASIC solutions to implement a typical system. Fixed architectures and other technology barriers prevented the integration of individual components into a single, low-cost chip that met all design requirements. Accuracy better than 1% Calibration eliminates certain errors common to A/D converters, such as offset and gain errors. If these errors are not adjusted, the measurements would be inaccurate and could impact the overall system performance. External components can be used to eliminate the offset and gain errors. However, this will add extra design complexity, noise and additional inaccuracy that in turn need to be eliminated. An ideal solution would be an integrated device that provides the high accuracy without penalty. Fusion offers several features such as the analogue quad, embedded flash, and flash programmable logic, which can be used with a software calibration scheme to provide a highly integrated solution with better than 1% accuracy. Live at power up Actel‟s programmable logic devices, based on non volatile memory technologies, store their configuration in the logic gates, making the devices available to perform critical system setup tasks such as system configuration and supervision during voltage ramp-up. Additionally, rapid operation from ultra-low-power (typically less than 25µW, even for 3million system gates) sleep mode is possible. Real world interface Fusion offers up to 30 high voltage tolerant analogue inputs enable direct connection to signals from –10.5V to +12V, eliminating the need for signal preconditioning. The Fusion A/D converter is configurable and supports resolutions up to 12bits, and sample rates up to 600ksample/s in 8bit mode. The overall a/d converter accuracy that can be achieved with the calibration solution is better than 1%. Fusion adds additional functionality with the inclusion of multiple differential input current monitor blocks, each with a built-in amplifier, increasing sensitivity and efficiency. The Fusion integrated temperature monitor circuitry allows for the monitoring of multiple remote temperatures with only an external diode. Up to 10 high current-drive outputs are ideal for mosfet control and/or pulse width modulation (PWM) functions, such as direct fan control. Dynamic system configuration

The ability of Fusion devices to support many system-level functions in a single chip makes Fusion an ideal candidate for leading edge system management protocols. Fusion‟s high performance flash memory blocks provide non volatile memory flexibility to every aspect of your design. At system start up, the flash memory can be used to initialise the system. SRAMs and registers can be automatically loaded with data from the on-chip flash memory. Prior to system shutdown, the volatile values in SRAM or registers on the Fusion device can be saved back into the on-chip flash memory, preserving the state of the device for the next system start up (SAVE and RESTORE). Fusion flash memory also enables the dynamic changing of system parameters (CONTEXT switch). System boot codes can be stored in the flash memory for both on-chip and off-chip requirements. The flash memory can be configured to emulate EEPROM operation with an available endurance extender IP. The optional soft IP Common Flash Interface (CFI) core from Actel can use part of the flash memory for file storage. Reconfiguring systems Inherent in the fabric of Fusion are the benefits of configurability and field reprogrammability based on the successful Actel ProASIC3 family of flash FPGA devices. Fusion can be securely programmed late in the manufacturing process or after it is in the field. By enabling a single hardware platform to support multiple projects and products, Fusion allows designers to leverage economies of scale in purchasing, while maintaining the ability to customise products for different markets. Both the firmware (flash memory) and hardware can be updated in a single step. Power and thermal management Fusion is an exceptional solution for power management. Unlike today‟s multi-voltage FPGA solutions, Fusion devices can be driven from a single 3.3V supply, eliminating the need for special power-up sequencers. Fusion can be configured to monitor and sequence a multi-voltage system for voltage and current. The unique combination of single-voltage operation and power management capabilities makes Fusion an excellent candidate for system/board management applications. With Fusion, temperature control is built in. Fusion supports both on-chip (internal diode) and remote temperature monitoring capabilities. The Fusion device can flag the temperature and power at programmable thresholds to indicate a warning, turn on a fan, or shut down the system. Additionally, Fusion can use external temperature sensor inputs to control heating or cooling system elements. ACHRONIX FPGAs Achronix‟ high performance FPGAs achieve around three times the throughput of FPGAs implemented at the same process node. For example,

Figure 1: Achronix‟ FPGAS compared with traditional devices Achronix Speedster FPGAs are implemented in a 65nm process and achieve up to 1.5 GHz peak performance. Achronix FPGAs consist of a conventional I/O Frame surrounding a picoPIPE logic fabric. The frame is similar to the periphery of other high-end programmable devices and includes configurable I/Os, SerDes, clocks and PLLs. The frame provides the off-chip interfaces and forms the boundary between the picoPIPE core and these interfaces. All data entering and exiting the core must pass through the frame. When considered as a „black box‟, the internal picoPIPE fabric is virtually indistinguishable from a conventional FPGA fabric. The only distinction is that the data throughput is substantially increased. The picoPIPE fabric is formed from an array of Reconfigurable Logic Blocks (RLBs, see Figure 2), connected through a programmable fabric. Each RLB is surrounded by Switch Boxes (SBs). The Switch Boxes route global signals across the picoPIPE fabric.

Figure 2: Reconfigurable Logic Blocks

Each RLB contains eight 4-input Look Up Tables (LUTs), storage elements and 128 bits of RAM. In addition to RLBs and programmable routing, the picoPIPE fabric also contains Block AMs and dedicated multipliers. The RLBs and routing are implemented using picoPIPE technology, enabling much higher throughput than non-picoPIPE-based FPGAs. The memories and multipliers operate at 1.5GHz to match the peak device performance. An important concept to highlight is the „Data Token‟. In conventional logic, a Data Token is a logic value at a clock edge. With traditional logic implementations, data is always present, but is only valid (and therefore propagated) when a clock edge is received at a storage element. Hence every time data is propagated from one storage element to the next, only a distinct, valid data value or „Data Token‟ is propagated. The picoPIPE stages are the atomic elements of the Achronix FPGA fabric. The fabric is capable of implementing any logic function. To implement a logic function, picoPIPEs use explicit Data Tokens, rather than propagating data in response to a global clock edge (see figure 3). A Data Token in picoPIPE logic can be considered as the data and the clock edge merged together. The key innovation that enables the picoPIPE fabric to operate at high frequency is this new representation of Data Tokens.

Figure 3: Data token passing in FPGAs A key component of the Speedster value proposition is the availability of a 10.3 Gbps embedded SerDes that support multiple standards. The Achronix embedded SerDes (up to 40 lanes) enable extremely high throughput while requiring very few pins. For this reason, SerDes functionality forms the basis for the datapath interface standards most commonly used in today‟s designs.

Standard high-speed serial interfaces supported by the Speedster family include:  40G/100G Ethernet  CEI-6G, both Short Range (SR) and Long Range (LR) (6.375Gbit/s)  10 Gbps backplane  XFI (10.3125 Gbit/s)  PCI-Express Gen1 and Gen2 (2.5 and 5 Gbit/s)  XAUI (3.125 Gbit/s)  Serial RapidIO (2.5, 5Gbit/s)  Infiniband (1.25, 2.5, 3.125Gbit/s)  Gigabit Ethernet (SGMII, 1.25Gbit/s)  SATA / SAS (1.5, 3 and 6Gbit/s)  Fibre Channel (1.0625, 2.125, 4.25 and 8.5Gbit/s) In addition to these standards, the SerDes also supports proprietary (nonstandard) interfaces – often used by system architects for “internal” traffic, where standards are less important, since they are hidden from system connections to the external world. Probably the most important proprietary use of SerDes technology is for backplane interconnect. In backplanes, narrow high-speed SerDes interfaces are preferred because they:  Minimise signal count  Don‟t require deskewing of a large number of lanes  Dispense with the need for a separate clock signal  Include the ability to adapt to the specific intervening channels The last feature (adaptability) is most critical for high-rate signalling across impaired channels such as backplanes, which inevitably include connectors and vias, as well as dispersive loss. Speedster SerDes provide significant adaptability: Transmitter:  Linear boost and equalisation  Digital Feed-Forward Equalisation (FFE) Receiver:  Linear boost and equalisation  Digital Decision Feedback Equalisation (DFE) These features ensure optimal error-free transmission at speeds up to 10.375Gbit/s,even across impaired channels. Built-in (optional) Physical Coding Sub-layer (PCS) support for 8b/10b-based protocols, such as PCI Express and Ethernet, are also provided. eASIC Nextreme Series eASIC‟s Nextreme Series is a new generation of ASIC devices that dramatically reduces the cost and risk of doing ASIC design. The Nextreme New ASIC Series is delivering on the promise of bringing affordable silicon customisation back to the masses. Nextreme New ASIC series delivers a number of benefits for designers of FPGAs, standard cell ASICs and ASSPs

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Standard Cell ASIC-like unit cost, power consumption performance and density Low up-front development cost Simple, FPGA-like design flow Device turnaround in only 4-6 weeks

Nextreme is a family of devices manufactured on a 90nm cmos process, using eASIC‟s patented customisation technology. They are built on a breakthrough configurable logic technology, which combines an FPGA-like logic cell, called an eCell (Figure 4), with single via customisable routing. This breakthrough technology enables Nextreme NEW ASICs to provide you with compelling low cost-ofownership both for fast prototyping and high volume production. Figure 4: eCell‟s FPGA like look up table architecture Table 1 shows a benefits comparison between FPGAs, cell based ASICs and Nextreme NEW ASICs. The programmable nature of SRAMbased FPGAs comes with severe cost and power penalties as each programming interconnect requires transistors Table 1: Technology comparisons and SRAM cells that consume both real-estate and power, even when not in use. Through utilising patented, single via customisable routing, instead of twenty year old FPGA-based programmable interconnect routing, Nextreme NEW ASICs deliver unit-cost and power consumption that are comparable to cell based ASICs, thereby relaxing the constraints on your system design.

Another advantage of Nextreme‟s via customisable routing method is the deployment of only a single via layer (via 6). This via layer can be implemented using Direct-write e-Beam (electron beam) and therefore eliminates the need for custom mask charges, which can easily be in the region of $1million for 90nm ASICs. Nextreme NEW ASICs also allow designers to implement sophisticated IP cores such as a soft ARM926EJ and Tensilica Diamond Standard Processors and leverage an industry standard ISA and peripherals to get to market quickly. You need no longer be locked into an FPGA vendor‟s limited proprietary soft processor offering. Once you hand off your design to eASIC, Nextreme NEW ASIC Figure 5: Nextreme SL prototypes can be delivered in a few weeks instead of months as with traditional Cell-based ASICs. You can use these prototypes to demonstrate working solutions to your customers or go into mass production, as the prototyping and production devices are identical. This means Figure 6: Nextreme VL you no longer need to perform costly and risky conversions from FPGAs to cell-based ASICs. With Nextreme NEW ASICs you truly get the best of both worlds – unit cost and power consumption approaching that of a cell-based ASIC, coupled with no mask charges, minimum order quantity and fast turnaround as with FPGAs. Optimal solutions for fast-prototyping or mass production There are two configurations to meet your time-to-market and mass production constraints

Nextreme SL In the SL device (see Figure 5), the LUT configuration is performed by loading a bit-stream into SRAM. This device is suited to providing the shortest turnaround time and the maximum flexibility, and is ideal for providing your customers with fast prototypes. Nextreme VL In the VL device (see Figure 6), the LUT is hard configured using a via layer. Nextreme VL devices do not require an external flash memory for configuration and are therefore „instant on‟, unlike SRAM-based FPGAs. Furthermore, Nextreme VL devices are less susceptible to soft errors and not subject to high „in rush‟ current seen with SRAM based FPGAs Multiple projects per wafer The interconnect in both Nextreme products can be customised quickly and inexpensively using a maskless lithography approach: the Direct-write e-Beam. Writing with an electron beam directly on the wafer eliminates the need for custom masks and hence, it prototypes allows removing for design A the associated tooling cost and prototypes shortening the for design B turnaround time. low volume for design C

Moreover, using e-Beam technology allows for wafers to be mid shared among volume for multiple design C customers or various projects, by writing different patterns on the same wafer (see Figure 7: Multiple projects per wafer with direct write eBeam Figure 7). The advantages of no mask charges, short cycle time and no minimum order requirement, make Nextreme NEW ASICs an ideal solution for prototyping as well as high volume production.

Unlike the traditional programmable routing inside FPGAs, Nextreme NEW ASICs use a patented technique of metal routing with a single via layer. This silicon efficiency directly translates into dramatically lower costs and lower power consumption. Conclusions The foregoing provides solutions to the special needs dictated by modern electronic equipment. Low cost and power addresses the consumer market whose fast evolution in hand-held applications demand innovative and leading edge solutions. Time to market is vital if companies are to compete with new innovations offered by a rapidly emerging world communications explosion. This also demands faster connection and data throughput and a combination of any of the above technologies can provide that leap forward.

FOR MORE INFORMATION ABOUT THE FPGAS DESCRIBED IN THIS WHITE PAPER, CONTACT: BRIAN HATCHER EUROPEAN PRODUCT MANAGER ACAL TECHNOLOGY WWW.ACALTECHNOLOGY.CO.UK TEL: +44 118 902 9630