IC Design

"I know HDL. Is that all I need to know for my career in digital ASIC/FPGA designs development?" Copyright © S3 Group

Jan Kovalsky Group Manager VUT Brno, 29-11-2012

Contents  Hassle with more languages to know  Design, programming and scripting languages in Design Flow  Specifics of design, verification and implementation  Support languages and tools used for simplification and automation of Design Flow

 Conclusion  Q&A

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Hassle with more languages  What languages do you know ?  Is it possible to use just 1 language only for both design and verification ?  Is it possible to finish the design and verification through GUI only ?

VHDL

Verilog

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Ideal ASIC/FPGA world  One design / verification engineer in a team  One design only written from scratch  No documentation needed  Unlimited budget

 Unlimited time  No re-use  No 3rd party IP blocks Copyright © S3 Group

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Reality If you work in a company providing ASIC/FPGA development services or as a sub-contractor or in a company with own products’ line you have to deal with:       

Wide team of design and verification engineers Customer designs in different languages Number of 3rd party IP blocks Each design is unique Internal flow and processes Limited knowledge Definite set of experiences

IP blocks

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Contents  Hassle with more languages to know  Design, programming and scripting languages in Design Flow  Specifics of design, verification and implementation  Support languages and tools used for simplification and automation of Design Flow

 Conclusion  Q&A

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Design Flow  In which phases of the flow can we use GUI and/or Scripting ?

Synthesis

Timing Analysis

Verification

Map

P&R

Bitstream Generation

Floorplanning and P&R

PV + PA

Scripting + GUI

GDS2 + ATPG

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Scripting

Formal Verification

GUI + Scripting

STA

GUI + Scripting

Logical Synthesis + DfT

Scripting + GUI

ASIC Flow

Scripting / GUI

Scripting + GUI

Design

Scripting + GUI

Scripting + GUI

Design Spec / Reqs

FPGA Flow

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Design  Used languages  Netlist: gate level design  RTL: Verilog, VHDL  Abstract: SystemVerilog, SystemC, C, IP-XACT (xml), Matlab, VisualBasic etc.  Encryption: proprietary IPs encrypted

 Challenges    

Mixed language design Mixed-signal designs Re-targeting between ASIC/FPGA and Prototyping on FPGA Parts of design are generated by 3rd party tools – CPUs, interconnects, memories  Number of models has to be integrated in the design (pads, analog IPs)

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Design (contd.)  Used languages examples  Netlists at gate level are usually auto-generated  Verilog, VHDL and SystemVerilog used for RTL design  SystemC and C describing CPU or more complex blocks  IP-XACT (xml) generic description language which can be used for description of blocks, register banks etc.

 Matlab can be used for generation of modeled blocks in VHDL etc.  VisualBasic macros integrated in documentation can be used for register map generation

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Design (contd.)  SoC designs are getting too complex for RTL design approach  According to EDA vendors (Verification Futures Conference, Munich, 22nd Nov 2012) SoC world ran out of RTL designs and is moving to more abstraction level (C-based designs)

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Verification  Used languages  Languages: Verilog, VHDL, SystemVerilog, e/Specman, Vera, SystemC, VerilogAMS, ASM, C, IP-XACT (xml), Matlab, VisualBasic, UPF/CPF etc.  Frameworks: VMM, OVM, UVM, customized derivatives  Encryption: proprietary VIPs encrypted

 Challenges    

More wild environment to live in Constrained Random Verification vs. Directed Tests approach Assertion based verification and coverage driven verification Verification of complex SoC & Mixed-signal designs (verification models in VerilogAMS etc.)  Low-Power features verification  Re-targeting verification to bench platform with FPGA & emulation on platforms like Palladium or ZeBu  Usage of encrypted VIPs & Number of verification models used (pads, analog IPs) Copyright © S3 Group

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Verification (contd.)  Used languages example  Verilog and VHDL used for TB and direct test cases development in combination with coverage driven verification  SystemVerilog, e/Specman, Vera and SystemC used for more constrained random verification using OOP approaches  ASM and C languages used for CPU boot code or user application development

 VerilogAMS used for analog IP blocks description  IP-XACT (xml) and VisualBasic used for automated generation of verification models of register bank etc.  VMM/OVM/UVM providing verification framework

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Implementation  Used languages  Languages: TCL, CPF/UPF, SDC, VisualBasic, TCF/VCD, WGL/STIL etc.

 Overview  PD tools support standard scripting interface (CLI) for support of TCL etc.  Particular steps of the PD flow can be fully scripted and automated  Some steps have to be done manually (PV, Floorplanning, manual routing, RDL/bumps etc.) through GUI

 Used languages example    

CPF/UPF describing low-power techniques used in the design SDC – Synopsys timing constraints TCL used for scripting of particular steps in the flow/tools VisualBasic used for example for generation padring definition acceptable by PD tools

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Design Flow Scripting  Used languages  Languages: Makefile, Perl, TCL, sh, unix, Python etc.

 Overview  Scripting used for design flow development (automated or semi-automated flow)  Supportive scripts development:  Block-level synthesis  Power Analysis  Header files generation

 Makefile based flow allows for easy extension of the design flow and can include:  Verification flow – single test or regression execution  PD flow execution (FPGA implementation, particular steps from ASIC implementation flow)

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Contents  Hassle with more languages to know  Design, programming and scripting languages in Design Flow  Specifics of design, verification and implementation  Support languages and tools used for simplification and automation of Design Flow

 Conclusion  Q&A

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Support Languages / Tools  Design tools (primarily 3rd party specific)  CPU configuration and compilation tools  Memory compilers  IP blocks compilers (like Xilinx CoreGen etc.)

 CM tools     

Team work requires appropriate configuration management in place Configuration management has to be applied by all team members Allows for co-operation between number of teams in various locations Brings some challenges in split databases management and synchronization Examples are SVN, CVS, ClearCase, Git etc.

 Bug reporting tools  Bugzilla or proprietary tools  Allows for co-operation between number of teams in various locations  Has to be appropriately used Copyright © S3 Group

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Contents  Hassle with more languages to know  Design, programming and scripting languages in Design Flow  Specifics of design, verification and implementation  Support languages and tools used for simplification and automation of Design Flow

 Conclusion  Q&A

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Conclusion  Why to learn more languages  It’s reasonable to learn more languages and technologies for your future career  ASIC/FPGA development world is not ideal  Advantage and big differentiator on a job market  Much faster ramp-up on a new position and in a new environment  More effective design and verification techniques  Ability to develop/maintain automated design flow

 Why to know various tools  Gives you ability to look for more efficient processes  Allows you to see the world from bird’s perspective  Enables more effective co-operation between team members and teams

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Conclusion  Why to automate the design flow      

Time to market is a key factor in any new design Compute farm and resources have to work while we relax Tools & Licenses cost has to be shared between number of projects Much efficient resources utilization Much mature development processes Good tools can be ineffective with poor processes

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Contents  Hassle with more languages to know  Design, programming and scripting languages in Design Flow  Specifics of design, verification and implementation  Support languages and tools used for simplification and automation of Design Flow

 Conclusion  Q&A

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Q&A

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Thank You • [email protected]

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