FPGA based Telecommand Receiver Module for Microsatellites

OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE Volume 1, Number 1, MAY 2014 OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE FPGA based Telecommand Receiver...
Author: Shawn Lester
23 downloads 0 Views 590KB Size
OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE Volume 1, Number 1, MAY 2014

OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE

FPGA based Telecommand Receiver Module for Microsatellites Salman Sadruddin* and Muhammad Saad Sohail National University of Science and Technology (NUST), H-12, Islamabad, Pakistan. *Corresponding author: [email protected]

Abstract: A reconfigurable, low cost, and resource efficient design of a microsatellite telecommand receiver using FPGA is presented. The proposed system uses a digital Costas loop for carrier recovery and an improved early late gate timing recovery algorithm for bit synchronization. Loop filter is designed and implemented without using embedded multipliers. The Bit Error Rate (BER) performance of the designed receiver is almost identical to theoretical values with negligible difference due to implementation losses. The designed receiver can compensate doppler shifts up to ± 200 KHz. Keywords: Field Programmable Gate Arrays (FPGAs); Bit Error Rate (BER); Binary Phase Shift Keying (BPSK); Signal to Noise Ratio (SNR)

1. INTRODUCTION Advent of FPGA has ushered the new era in the field of space technology. Traditionally, digital circuits for space missions are dedicated for a particular application. Therefore, it is often difficult to modify or upgrade them. Small size and light weight FPGAs combined with high computational power have caused a paradigm shift in the space industry. FPGAs reconfigurable nature and small size has dramatically reduced the sizes of space missions. The capability to reconfigure FPGA distantly with an updated functionality reduces the hardware requirement in space craft [1]. Microsatellites are increasingly becoming popular due to their low cost and short development process. It makes them a suitable platform for technology evaluation and demonstration. But small size satellites suffers from several design constraints such as less area, mass and limited available power for satellite payload. This makes the task more challenging than usual large satellites. FPGA proves to be viable solution to these problems. Their compact size, versatile characteristics and adaptability to changing design requirements makes them a favourable choice over other digital systems. Telecommand receiver is a one of the most important module of a satellite. It establishes the communication channel between earth station and satellite. It receives and demodulates the telecommand signals from the ground station. Conventionally, discrete component based telecommand receivers are being used in large and mini satellites. However, they are not appropriate for microsatellites due to their large size and weight. This paper presents a highly efficient implementation of a Microsatellite telecommand receiver module 74

FPGA based Telecommand Receiver Module for Microsatellites

Figure 1. Block diagram of Telecommand Receiver

using FPGA. The proposed module uses Costas loop for carrier recovery and demodulation of BPSK signal. Timing recovery is performed using early late gate algorithm. The Literature review reveals that the Maya, J.A et al. [2] BPSK receiver and our design have same specifications. So, it was taken as a benchmark for fair resource utilization. The designed system consumes less resources and has Bit Error Rate (BER) almost equal to theoretical, with slight degradation due to implementation losses. The paper is organized as follows. Section 2 explains the design and functionality of Telecommand receiver. In Section 3, gives the detailed implementation of the proposed receiver for microsatellite. Section 4 shows the hardware co-simulation results. Section 5 presents the conclusions drawn from the results.

2. TELECOMMAND RECEIVER The Telecommand link uses BPSK modulation. Coherent demodulation scheme is adopted due to its high Signal to Noise Ratio (SNR) performance and good BER as compared to non-coherent [3]. The designed receiver shown in Figure 1 , contains following sub modules: Carrier recovery, integration, bit-synchronization and data sampler block.

2.1 Carrier Recovery The first step is to establish the method for removing offsets from receivers LO and achieve carrier synchronization [4]. Costas loop is an optimal technique to attain carrier recovery for BPSK signals [5]. It provides an excellent performance for BPSK and is one of the most efficient binary data modulation schemes in terms of noise immunity per unit bandwidth [6, 7]. Traditionally, Costas loop is realized using discrete components. But their performance is severely affected by phase imbalance, direct current zero excursion and complexity to debug [8]. These shortcomings can be overcome by implementing Costas loop in digital domain as shown in Figure 2 . It comprises of mixers, low pass filters, phase detector, loop filter and Numerically Controlled Oscillator (NCO). Then input signal xi (t) is BPSK modulated as shown in equation (1). xi (t) = Ai m(t) sin(ωit + θi )

(1)

NCO generates two orthogonal sinusoid signals xo1 (t) and xo2 (t), as shown in equation (2) and equation 75

OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE

Figure 2. Costas Loop

Figure 3. Implementation of Costas Loop

(3) respectively. The arm connected the in-phase signal from NCO is called as In-phase or I channel and the arm connected to quadrature phase signal is called as Quadrature phase or Q-channel. xo1 (t) = A0 sin(ωit + θ0 )

(2)

xo2 (t) = A0 cos(ωit + θ0 )

(3)

These signals are multiplied with the received BPSK modulated signal by the mixers of I and Q channels. The multiplication yields signals shown in equations (4) and (5). xd1 (t) =

Ai A0 m(t)[cos(θi − θ0 ) − sin(2ωit + θi + θ0 )] 2

(4)

Ai A0 m(t)[sin(θi − θ0 ) + sin(2ωit + θi + θ0 )] (5) 2 The low pass filters of I and Q channel removes the high frequency components of equations (4) and (5) to get the signals xI (t) and xQ (t) as shown in equation (6) and (7) respectively. The phase detector estimates the phase difference between both arms and produces xd (t) as shown in equation (8). xd2 (t) =

76

FPGA based Telecommand Receiver Module for Microsatellites

Figure 4. Low Pass Filter Implementation

xI (t) =

Ai A0 m(t) cos(θi − θ0 ) 2

(6)

xQ (t) =

Ai A0 m(t) sin(θi − θ0 ) 2

(7)

[Ai A0 m(t)]2 sin[2(θi − θ0 )] 8

(8)

xd (t) =

The loop filter removes the unnecessary spikes from the error signal xd (t) and adjusts it to control the frequency and phase of the NCO output signal. By using small signal approximation [9], the output of loop filter is shown in equation (9). x f (t) =

[Ai A0 m(t)]2 (θi − θ0 ) 8

(9)

Equation (9) implies that loop filter output is directly proportional to the phase difference. If the Costas loop is not in the locked state, the phase detector will send the phase difference to loop filter which is then used to adjust the NCO output. If the Costas loop is in the locked state, the phase difference would be zero or very close to zero, hence the loop filter will extract the carrier signal [10]. The demodulated signal can be obtained at the output of I-channel.

77

OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE

Figure 5. Integrate and Dump

Figure 6. Peak detect Module using Early-Late-Gate Sampler

2.2 Integrate and Dump Demodulated signal from the output of Costas loop is applied at the input of integrate and dump module. It is an integrator with the capability of resetting itself. The resetting of the integrator took place at the moment of bit transition. Due to this, the value of the bit is easily determined by knowing the prefix of the accumulated sum. The resetting of integrator is crux of this process and needs to be performed carefully. The integrate and dump filter produces a triangular waveform.

2.3 Bit Synchronization and Data Sampler This stage accurately determines the timing and sampling of received data bits. It consists of three processes; Peak detect, Preamble match and Data sampler. First, the signal is applied to peak detect block. It uses early late gate sampling algorithm to detect the peak of the signal. After the successful detection of peak, the signal is sent to preamble match block. This module samples the data and compares the recovered bits with the pre-stored sequence of data bits. When the received bit pattern matches with the pre- stored preamble, the data sampler starts sampling the output of integrate and dump filter and recovered data bits appear at the output. 78

FPGA based Telecommand Receiver Module for Microsatellites

Figure 7. Preamble Match Module

3. IMPLEMENTATION The design, concepts and algorithms of the telecommand receiver are validated by using high level system design tools (such as MATLAB/Simulink). These tools expedite the design process and provide ease in debugging and editing of each functional module of the system. The design is realized on FPGA by Xilinx System generator, a system level design tool for FPGA. In order to simulate and verify the design, a BPSK modulator is created in Simulink. The AWGN noise is added and signal levels are adjusted to emulate the real satellite communication channel. The telecommand receiver data rate is 1 Mbps and carrier frequency is 4 MHz. The Doppler shift due to the relative motion of the satellite with respect to earth is considered to be ± 200 KHz. Figure 2 shows the Costas loop implemented using Xilinx System generator. The input signal is first level shifted and down sampled to reduce the resource requirement for the system. NCO is realized by using Direct Digital Synthesizer (DDS) compiler 4.0 with 96 dBc spurious free dynamic range. The DDS accumulator size is of 18 bits and output word is of 14 bits. The mixers are realized by 14 x 14 bit multipliers. The mixed signals are filtered by fifth order low pass filters of I and Q channels. The low pass filters are designed with discrete blocks using Direct Form Symmetric architecture as shown in Figure 4 . This architecture takes the advantage of symmetry in the coefficients of filter and consumes half the adders and multipliers as compared to other schemes. In addition to that, one of the multiplication operation is realized by using shift left operation which further decreases the resource requirements. The filtered I and Q channel signals are applied at the input of Phase Detector (PD). The PD estimates the phase difference between both signals and produces an error signal. This error signal is filtered and fine-tuned by the loop filter. Loop filter is implemented without using the built-in multipliers of FPGA. The loop filter output is then used to correct the output frequency and phase of NCO. The designed Costas loop has a loop band width of 400 KHz i.e. it can demodulates signals with Doppler shifts up to ± 200 KHz. When the loop is locked, the demodulated signal appears at the output of I-Channel. The demodulated signal is applied at the input of integrate and dump (I&D) module. It is implemented using an accumulator of 13 bits with a resetting circuitry which consist of a 6-bit counter and relational operators as shown in Figure 5 . In addition to Integrate and dump operation, this module also calculates the threshold value which is used by data sampler module. The integrate and dump module output and threshold value (Th) are applied to the Bit synchronizer and data sampler module. This module passes the signal through three stages; Peak detect, Preamble match and data sampler. The peak detect module uses the early-late-gate sampling algorithm. We have implemented this algorithm without using multipliers as shown in Figure 6 , thus reducing the resource consumption. It uses three samples to determine the peak. The samples are termed as Early (E), Present (P) and Late (L). As the peak is detected, the peak detect 79

OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE

Figure 8. Hardware Co-Simulation of Telecommand receiver

signal goes high. The algorithm implemented is as follows: i f ((|E| < |P|) AND (|L| < |P|) & (|P| ≥ Th )) Peak detect == 1 The peak detects signal enables the data sampler and preamble match modules. The preamble match module is consists of relational and logical operators as shown in Figure 7 . The pre-stored sequence is stored in the Block RAM. Once the preamble is matched with the received bit sequence, the data sampler will start sampling. The data sampler uses the integrate and dump output for sampling rather than Costas loop demodulated output. It has been observed during simulations, the sampling of integrate and dump filter output gives good BER performance than sampling of demodulated output from Costas loop. The complete system design is pipelined to yield good timing performance.

4. RESULTS The proposed microsatellite telecommand receiver is realized on FPGA by using Xilinx system generator. The designed system was Hardware Co-simulated with Spartan 3E XCS3E500E-4FG320 FPGA as shown in Figure 8 . Hardware co- simulation incorporates hardware into simulation to make it a real time implementation. The data is processed in the hardware and the results are displayed in software (i.e. Xilinx system generator). The results of hardware in-the-loop simulation are shown in Figure 9 . It can be seen in the results, the outputs: (a) Sync lock and (b) Received bits of system generator are similar to (d) Sync lock and (e) Received bits form hardware co-simulation. The designed system was tested with frequency shifts up to ± 200 KHz. The Incoming signals frequency is shifted to 4.2 MHz and 3.8 MHz, while the NCO is running on 4.0 MHz. In both the cases NCO successfully tracked the incoming signal frequency in less than 10 us as shown in Figure 10 and Figure 11 . The BER calculation of the system is obtained by using “bertool” of MATLAB. The BER analysis of the receiver is performed by using Monte-Carlo simulation as shown in Figure 12 . It is evident from Figure 12 ; the BER performance of the designed telecommand receiver is very close to the theoretical BER with exception of the implementation losses. The proposed receivers resource 80

FPGA based Telecommand Receiver Module for Microsatellites

Figure 9. Output of Scope a) Sys gen SynLock b) Sys gen Received Bit c) Transmitted Bits d) HWCOSIM Received Bits e) HWCOSIM SynLock

Figure 10. Loop Filter Output with incoming signal at 4.2 MHz

consumption on FPGA and its comparison with Maya, J.A., et al [2] is presented in Table 1 . The designed receiver utilizes 50% less multipliers, 5% less 4- input LUTs and 1% less slices as compared to [2]. The timing recovery module of the designed system consumes about 60less slices as compared to [2] and is implemented without using multipliers.

5. CONCLUSIONS This paper presents a resource efficient design for a microsatellite telecommand receiver. This optimized BPSK receiver utilizes less FPGA resources as compared to [2]. The implemented system uses a proficient Costas loop in terms of resource utilization and an improved timing recovery algorithm. The system can 81

OPEN JOURNAL OF COMMUNICATIONS AND SOFTWARE

Figure 11. Loop Filter Output with incoming signal at 3.8 MHz

Figure 12. BER analysis

Table 1. RESOURCE UTILIZATION COMPARISON OF DESIGNED RECEIVER WITH [2] Logic Utilization

82

Carrier Recovery Timing Recovery Utilization Total Avail. Percentage % Used Used This work [2] This work [2] This work [2]

Slice

553

607

155

387

4,656

15

16

Slice flipflops

759

732

158

651

9,312

9

13

4-input LUTS

677

973

136

503

9,312

8

13

RAMB16s

1

2

1

0

20

10

10

MULT18x18

3

2

0

4

20

15

30

BUFGMUXs

1

1

1

1

24

4

8

FPGA based Telecommand Receiver Module for Microsatellites

successfully recover the signal with frequency shifts up to ± 200 KHz. The hardware foot print of the design is low enough to allow the use of a low end FPGA which reduces the cost of the overall system. The BER performance of the system shows minor difference with respect to theoretical limits. It has been concluded that the small size, light weight and excellent BER makes the designed telecommand receiver an ideal choice for Microsatellites and space missions. The future work would include real time measurements by interfacing the Antenna along with the RF down conversion chain connected with FPGA.

References [1] M. Caffrey, M. Echave, C. Fite, T. Nelson, A. Salazar, and S. Storms, “A space-based reconfigurable radio,” 2002. [2] J. A. Maya, N. A. Casco, P. Roncagliolo, and J. Garcia, “A high data rate bpsk receiver implementation in fpga for high dynamics applications,” pp. 233–238, 2011. [3] Z. Zhao, Y. Shen, and Y. Bai, “Design and implementation of the bpsk modem based on software defined radio,” in Instrumentation, Measurement, Computer, Communication and Control, 2011 First International Conference on, pp. 780–784, IEEE, 2011. [4] P. Krivic and G. Stimac, “Fpga implementation of bpsk modem for telemetry systems operating in noisy environments,” in MIPRO, 2011 Proceedings of the 34th International Convention, pp. 1727– 1731, IEEE, 2011. [5] X. Z. Jiancai Song and X. Yang, “Application technology research of costas loop on wireless spread-spectrum positioning system,” Inertial technology journal in china, vol. 2, no. 14, pp. 56–60, 2008. [6] J. G. Proakis, “Digital communications,” pp. 356–357, 2001. [7] B. P. Lathi, Modern digital and analog communication systems, pp. 187–188. Oxford University Press, Inc., 1990. [8] J. Feigin, “Features-featured technologies:-signal processing-practical costas loop design-designing a simple and inexpensive bpsk costas loop carrier recovery circuit.,” RF design, vol. 25, no. 1, pp. 20–36, 2002. [9] B. Shamla and K. Gayathri Devi, “Design and implementation of costas loop for bpsk demodulator,” in India Conference (INDICON), 2012 Annual IEEE, pp. 785–789, IEEE, 2012. [10] Z. Yang, Y. Bai, and Z. Zhao, “Design and implementation of the digital costas loop based on software defined radio,” in Instrumentation, Measurement, Computer, Communication and Control, 2011 First International Conference on, pp. 687–690, IEEE, 2011.

83