Overview F
F
Operating Systems
(done)
– processes – files
(done) (done in cs4513)
Manage Devices – processor – memory – disk
Memory Management (Ch 8.1 - 8.6)
(done) (next!)
Simple Memory Management
Simple Memory Management F F
Provide Services
Small, protected OS, drivers – DOS
One process in memory, using it all – each program needs I/O drivers – until 1960
RAM
I/O drivers
RAM
User Prog
Simple! Partion 3
F
F
OS (a)
• Unequal queues
Partion 1
F
• Waste large partition • Skip small jobs
Hey, processes can be in different memory locations!
Link Time Load Time – relocatable code
OS (b)
Compile Time
Source Compile Object
– dynamic or static libraries
Partion 2
300k 200k
OS
– maybe absolute binding (.com)
500k Partion 1
User RAM Prog
Address Binding
Partion 4 Partion 3
Partion 2
RAM User Prog
ROM
“Mono-programming” -- No multiprocessing! F Early efforts used “Swapping”, but slooooow
Multiprocessing w/Fixed Partitions 900k
User Prog
OS F
Partion 4
Device Drivers
OS ROM
F
Link Load Module
Run Time – relocatable memory segments – overlays – paging
Load RAM Binary Run
1
Logical vs. Physical Addresses Compile-Time + Load Time addresses same F Run time addresses different F
Logical Address
CPU
346
Relocation Register
14000
Relocatable Code Basics F F
Allow logical addresses Protect other processes Limit Reg
Physical Address
14346
Memory
+
F
User goes from 0 to max Physical goes from R+0 to R+max
physical address
F
Addresses must be contiguous!
Review
Static solutions – compute ahead of time – for predictable situations
F
Memory
error
Design Technique: Static vs. Dynamic F
+
no
MMU F
yes
1/2 N holes!
– Fifty-percent rule – Fundamental:
125k Process 9
adjacent holes combined u adjacent processes not combined u
OS 50k
process 3
process 3
90k
process 8
process 8
60k
Cost of Compaction process 1
process 3 process 2
process 2
Solution?
process 1 50k
process 3
process 3
90k
process 8
process 8
60k
process 2
100k process 2
128 MB RAM, 100 nsec/access è 1.5 seconds to compact! F Disk much slower! F
process 8
100k process 2
OS
F
Want to minimize external fragmentation – Large Blocks – But internal fragmentation!
F
Tradeoff – Sacrifice some internal fragmentation for reduced external fragmentation – Paging
4
Paging
Paging F F
Address generated by CPU divided into: – Page number (p) - index to page table
Logical address space noncontiguous; process gets memory wherever available
u
– Divide physical memory into fixed-size blocks
page table contains base address of each page in physical memory (frame)
– Page offset (d) - offset into page/frame
size is a power of 2, between 512 and 8192 bytes u called Frames u
– Divide logical memory into bocks of same size u
CPU
p d
f
d
called Pages
physical memory
f
page table
Paging Example
Paging Example
Offset
0 1
3
Page 2
4
Page 1
Page 1
1 4
Page 2
2 3
Page 3
3 7
Logical Memory
5 6
Page Table
7
Page 3 Physical Memory
Page 0
Page 0
Page 1
Page 0
2
010 011
00 01
Page 2
1
100
01 11
100
101
10 00
101
110
11 10
001
0 Page
0
1
0
1
001
1
010
Frame
011
110 111
111
Page Table Physical Memory
Logical Memory
Paging Hardware address space 2m F page size 2n F page offset 2m-n
000
000
Page 3
Page size 4 bytes F Memory size 32 bytes (8 pages) F
0
Paging Example
F
phsical memory 2 m bytes
F
Consider: – Physical memory = 128 bytes – Physical address space = 8 frames
How many bits in an address? F How many bits for page number? F How many bits for page offset? F Can a logical address space have only 2 pages? How big would the page table be? F
F
page number p
page offset d
m-n
n
note: not losing any bytes!
5
Page Table Example 0
0 3
Page 0
page number p
page offset d
m-n=3 Page 0
0 1
Page 1
1 4
n=4
3
Page 0B
4
Page 1A
F
Page 1B
Page Table
F F
avg: 1/2 page per process
u
small pages!
u
page table / process (context switch + space)
u
lookup (especially if page to disk)
Implementation of Page Table
Consider:
Page table kept in registers Fast! F Only good when number of frames is small F Expensive! F
– 8 bits in an address – 3 bits for the frame/page number
F
u
– overhead
Another Paging Example
F
consider: 2048 byte pages, 72,766 byte proc – 35 pages + 1086 bytes = 962 bytes
Physical Memory
F
u
5
7
F
Disadvantages – internal fragmentation
6
Process A
Advantages – no external fragmentation (no compaction) – relocation (now pages, before were processes)
2
Page Table
Process B
F Page 0A
1
1 7
Page 1
Paging Tradeoffs
b=7
F
How many bytes (words) of physical memory? How many frames are there? How many bytes is a page? How many bits for page offset? If a process’ page table is 12 bits, how many logical pages does it have?
Registers Memory Disk
Implementation of Page Table F F
Page table kept in main memory Page Table Base Register (PTBR)
Associative Registers logical address p d
0
1 4
1
Page 1
2
Page 0
CPU Page 0
0 1
Page 1
1 4
Logical Memory F F
PTBR
Page Table
page frame number number
hit
f
d
physical address
3 Physical Memory
Page Table Length Two memory accesses per data/inst access. – Solution? Associative Registers
10-20% mem time
associative registers
miss
physical memory
f page table
6
Associative Register Performance Hit Ratio - percentage of times that a page number is found in associative registers Effective access time = hit ratio x hit time + miss ratio x miss time F hit time = reg time + mem time F miss time = reg time + mem time * 2 F Example: F
Protection Protection bits with each frame Store in page table Protection Bit F Expand to more perms F F
Page 0 Page 1 Page 2
– 80% hit ratio, reg time = 20 nanosec, mem time = 100 nanosec – .80 * 120 + .20 * 220 = 140 nanoseconds
Typical logical address spaces:
v
2 3
v
Page 1
1
Page 0
2
i
3
Page 2 Physical Memory
10
page offset d 12
10
...
Page 0 ...
Page table may have:
...
– 2 32 / 212 = 2 20 = 1million entries
...
...
Each entry 3 bytes => 3MB per process! F Do not want that all in RAM F Solution? Page the page table F
Logical Memory
...
Outer Page Table
– Multilevel paging
Page Table
Inverted Page Table
Multilevel Paging Translation F
Page table maps to physical addresses
page offset d CPU
pid
p
d i
search
page number p1 p2
0
Page Table
Typical page size: – 4 Kbytes = 2 12 bits
F
1 0
Multilevel Paging page number p1 p2
– 4 Gbytes => 232 address bits (4-byte address) F
v
3 0
Logical Memory
Large Address Spaces F
0 1
p1 p2 d outer page table
inner page table
desired page
F F
d
i pid
p
Physical Memory
Still need page per process --> backing store Memory accesses longer! (search + swap)
7
Memory View F F
Segmentation
Paging lost users’ view of memory Need “logical” memory units that grow and contract
F F
– base - starting physical location – limit - length of segment
subroutine
ex: stack, shared library
main
• Solution?
stack
F
Hardware support – Segment Table Base Register – Segment Table Length Register
symbol table
• Segmentation!
Logical address: Segment table - maps two -dimensional user defined address into one-dimensional physical address
Segmentation logical address s
d
CPU main
limit base +
< no
yes
physical address
Operating Systems
stack
error
Software Signals physical memory
Software Interrupts F
SendInterrupt(pid, num) – type num to process pid, – kill() in Unix
F
HandleInterrupt(num, handler) – type num, use function handler – signal() in Unix
F
Typical handlers: – – – –
ignore terminate (maybe w/core dump) user-defined (Hey, demos!)
Unreliable Signals F
Before POSIX.1 standard:
signal(SIGINT, sig_int); ... sig_int() { /* re-establish handler */ signal(SIGINT, sig_int); } F Another
signal could come before handler re-established!
8
Memory Management Outline F
F
F
Basic
4
– Fixed Partitions – Variable Partitions
4 4
Paging
4
– Basic – Enhanced
4 4
Specific
←
Memory Management in WinNT F
– Upper 2GB shared by all processes (kernel mode) – Lower 2GB private per process
Page size is 4 KB (212, so offset is 12 bits) F Multilevel paging (2 levels) F
– 10 bits for outer page table (page directory) – 10 bits for inner page table – 12 bits for offset
– WinNT – Linux F
Virtual Memory
Memory Management in WinNT F
Each page-table entry has 32 bits
Memory Management in Linux F
– only 20 needed for address translation – 12 bits “left -over” F
Characteristics
Page size: – Alpha AXP has 8 Kbyte page – Intel x86 has 4 Kbyte page
F
– Access: read only, read-write – States: valid, zeroed, free … F
32 bit addresses (232 = 4 GB address space)
Multilevel paging (3 levels) – Makes code more portable – Even though no hardware support on x86!
Inverted page table
u
“middle-layer” defined to be 1
– points to page table entries – list of free frames
Memory Management in Linux Buddy-heap Buddy-blocks are combined to larger block F Linked list of free blocks at each size F If not small enough, broken down
Object Module Information required to “load” into memory Header Information F Machine Code F Initialized Data F Symbol Table F Relocation Information F (see SOS sample)
F
F
F
F
8 KB 16 KB 8 KB
8 KB 4 KB 4 KB
9
Linking an Object Module Combines several object modules into load module F Resolve external references F Relocation - each object module assumes starts at 0. Must change. F Linking - modify addresses where one object refers to another (example - external)
Loading an Object F
Resolve references of object module On Disk
In Memory
Header
Executable Code
Executable Code
Initialized Data
Initialized Data
Uninitialized Data
F
Normal Linking and Loading Printf.c
gcc
Printf.o
Static Library
Printf.c
Main.c
gcc
ar
Load Time Dynamic Linking
Main.o Linker
ar Dynamic Library
Loader Memory
Memory Linking Performance Comparisons Linking Disk Load Method Space Time
gcc
Printf.o
Dynamic Library
a.out Loader
• Save disk space. • Libraries move? • Moving code? • Library versions? • Load time still the same.
Main.c
gcc
ar
Main.o Linker
Memory
Run-Time Dynamic Linking Printf.c
gcc
Printf.o X Window code: - 500K minimum - 450K libraries
a.out
Main.c
gcc
Main.o Linker a.out Loader
Run-time Loader
Save disk space. Startup fast. Might not need all.
Run Time (4 used)
Run Run Time Time (0 used) (2 used)
Static
3Mb 3.1s 0
0
0
Load Time
1Mb 3.1s 0
0
0
Run Time
1Mb 1.1s 2.4s
1.2s
0
Memory
10