Finite state automation-Definition of data communication line control procedures by DINES BJ0RNER IBM Research San Jose, California

METHODOLOGY

INTRODUCTION

We shall describe the definitional approach through an example and will use a "multilevel iteration, topdown technique"4 whereby we first describe the total system, then its major subsystems and subsequently the components in each of these. We finally give the complete (character oriented) logic of each component. Exactly what we mean by this hierarchy will be apparent as we go along. We may also refer to this presentation technique as one demonstrating "layers of abstraction. "5 Needless to say, we would like to see such a methodology applied in other areas. Our example is that of a TWO WAY ALTERNATE (or: half duplex) NONSWITCHED MULTIPOINT data communication system with CENTRALIZED OPERATION. (See Ref. 3 sections 5.5 and 6.4-5 and Ref. 1, page 20, transparent-text mode.)

The notions of finite state automata, state transition graphs and tables and the set of regular languages being accepted (generated) by such automata are well known. But for some reason these notions have not been rigorously applied in the definition of data communication line control procedures. It is the objective of this paper to do so and to show the naturalness of this approach. We claim that we thereby arrive at a complete, precise and unambiguous definition. Others have attempted this before us. They have, however, not used the descriptional tool of finite state automata.1,2,3 Anyone or all of these references thus form the basis on which we will compete and we shall use essentially the line control procedures which these documents set out to define. It is shown how a multilevel hierarchical definition of data communication line control procedures by means of finite state automaton graphs leads to easily understandable communication standards, complete and unambiguous specifications, well-structured relations between the syntactic, semantic and pragmatic issues and embodies straightforward extensibility features. It IS further shown how the definition is the basis for an automatic conversion int~ all conceivable schemes of implementation: active hardware logic, microprogram controls or software procedures. We specifically mention the duality of implementing the generator (transmitter) and acceptor (receiver). We finally show the suitability of our technique to that of specifying the proper interlocking of asynchronously operating full-duplex schemes, this latter scheme has applications to the well-behaved, rather than well-policed, control of systems of many parallel processes.

SPECIFICATION HIERARCHY

First level As our first level we show Graph 1 on Figure 1. C denotes the state of the" system in which the central device c, e.g., a computer data transmission control unit is communicat£ng a sequence of characters u (a word, a sentence) to one or more remote devices r, e.g., keyboards and displays. The communicated sequence u in turn transfers the system to state R. In state R zero or one remote device is communicating another sequence of characters v to the central device. This in turn brings the system back to state C. We note that while c is send£ng (or transmitting) u, r is receiving u and vice versa-r is sending v which is received by c.

477

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GRAPH 1 u

v Figure I-GRAPH 1 First level data communication system. C: Central- and R: Remote System State

Yet another equivalent characterization is that each of the two components, the central and the remote subsystem, can take on either of two mutually exclu~ive first level states or modes-receiving or transmittmg. Note that no device can simultaneously be receiving and sending. This half duplex or two-way alternate scheme is truly reflected by the state transition graph approach. A final note in this section concerns the nature (format, structure) of words uE U and vE V, where U and V are languages. It is the precise definition of U and V that concerns us. We start out by defining an alphabet ~ (vocabulary), a finite set of (terminal) symbols (where the use of the word terminal has no connection with the fact that we often call remote devices terminals). An n bit coding allows for up to 2n symbols. In our example the alphabet is: ~=

and r can be grouped in two major classes: Pollingand Select-transactions. In polling one remote device r is asked by the central device c-through the use of a polling sequence p-to communicate to the central device whatever polling message pm or termination sequence t it might wish to transfer. p brings the system from state Ci to state Rp. The system goes to state Cp upon c receiving pm and c sends back appropriate polling message replies pmr. If these are erroneously received (i) by the system in state Rp the remote device sequences a request reply rr to c. The system then transfers to state Cpo Each of the words p, pm, pmr, t and rr may range within corresponding well defined languages: Lp, Lpm, Lpmr, Lt and Lrr. In selection one or more remote devices are requested by the central device to enable themselves for subsequent selection messages sm communicated to them, either one-by-one or on a broadcast basis, from the central device. The selection process consists of one or more selection sequences s each in turn followed by an initial selection reply isr. These sequences bring the system back and forth between states Rs and Ci with the last such isr bringing the system to state Cs; whereas sm and their replies, the selection message replies

GRAPH 2

{eot, enq, soh, stx, dIe, syn, itb, etx, etb,ack, .nak} U~aU~a=bcc

Underlined character triplets denote one symbol, and except for bcc (block check character set, which may take on any bit coding whatsoever), they are all control symbols as distinguished from ~a and ~a. ~a denote symbols a allowed in either prefix, header or t~xt sequences. For reason of simplicity we omit a specIfic breakdown of ~a in sub-subalphabets. ~a denote all other symbols of even or odd bit parity. A string is a sequence of symbols. The (infinite) set of all finite length strings including the null string over ~ is denoted by .~*. U and V are true subsets of ~*.

ucL:*,

vcL:*

From the next sections it will now be clear exactly how words in U and V are defined.

Second level (See Graph 2 on Figure 2) The subsystem r denotes one or more (but a finite number of) remote devices. Transactions between c

Figure 2-GRAPH 2 Second level data communication system p: polling- and s: selection state

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Finite State Automation

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Figure 3-GRAPH 3 Third level data communication system. Transition from errorrecovery states 37 and 38 to initial system state 1 not shown

smr, cause transitions between Cs and Rs. The system in Cs finally terminates selection mode by sending a t word to the remote devices causing a transition from Cs to Ci. Like in polling we may speak of well defined languages Ls, Lisr, Lsm, Lsmr, Lrr and Lt.

rejection (acceptance). After is a, a A will bring us to either state 22 or 23 depending on whether or not the central device wishes to select more than one device. The (2) nondeterministic A transitions from state 21 are thus resolved by conditions in c which are combined with A. States Rpm (Csm). Polling (selection) messages may be blocked or nonblocked. A series of blocked submessages, pmb (smb ), will cycle us around the 4 state loop 5-6-8-9-5 ... (23-2426-27-23 ... ). The last blocked submessage or a nonblocked message is here referred to as pmt (smt) , t denoting text. pmb's and pmt's (smb's and smt's) are either (1) accepted pma (sma), (2) rejected pmr (smr) , or either (3) the message transmitting (remote or central) device cannot interpret the reply (i) or (4) the message receiving device has not been able to detect the end of the message block thus causing a timeout (i). In case of an i-type reply the message transmitting device may choose either to communicate a request reply rr or enter some error recovery procedure erp. This latter choice may also result from repeated message reject replies. After suitable error recovery procedures the system goes to state 1. After the last message block has been acknowledged-or if in polling the polled device has no message to send-a termination sequence t brings the system to state 1.

Fourth level

We now first expand the message generating/ recognizing super state Csm and Rpm, which like Cpmr and Rsmr or Csrr and Rprr can be treated by

Third level (See graph 3 on Figu;e 3)

We now proceed to explode substates Ci, Cs, Cp, Rs and Rp into submachines. In Graph 3 we have clearly marked these and their relation to Graph 2. First we cover some omissions from Graph 2 and subsequently we subdivide further the Second Level Languages.

GRAPH 4

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1. When e.g., s in Graph 2 causes a transition from

Ci to Rs, then we actually mean to show: an s sequence of transitions in Ci followed by a lineturnaround transition A from Ci to Rs. We shall later explore this latter type of transition in depth. 2. States Rsir (substate of Rs). isr (is a) denote an initial selection reply sequence indicating a

479

Csm Rpm

Figure 4-GRAPH 4 Fourth level message transfer subsystem

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GRAPH 43

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Figure 5-GRAPH 41 Fourth level message transfer subsystem

showing one graph. One then substitutes these graphs into the less detailed third level graph. The latter and remaining superstates are subsequently treated in depth. In Graph 4 (Figure 4) the fourth level state 1 (4.1) equals either 3.23 or 3.5, 3.24=4.7=3.6 and 3.25= 4.9=3.7. Graph 4 is identical to the regular expression: (soh a+(etbUstx a+(etbUetx)) Ustx a+(etbUetx) )bcc. Graph 4 shows that our messages may be of either of five constructions. (pmb/smb)

soh a+ etb bcc

or

(pmb/smb)

soh a+ stx a+ etb bcc -soh a+ stx a+ etx bcc

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(pmt/smt) (pmb/smb) (pmt/smt)

stxa+ etb bcc -stxa+ etx bcc.

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4.S -142.7. 42.S. 42.9f 4.6 i!I 42.15 4.7-42.17

Figure 6-GRAPH 42 Fourth level message transfer subsystem. Detailed version distinguishes between transparent and non-transparent texts

~------------

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Figure 8-GRAPH 44 Fourth level establishment reply subsystem

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43.1

Finite State Automation

481

GRAPH A

42.111-4U

42.18-48.11

Figure ll-GRAPH A Fourth level line turnaround subsystem idealized

(punch) or keyboard (printer) within a 1050 system (enq = enquiry) . LINE TURNAROUND

Figure 9-GRAPH45 Fourth level delivery termination and terminate subsystem

text mode a dIe itb signals a return to nontransparent text mode (dIe == data link escape). For the sake of completeness we next show the detailed content of each of the remaining superstates: Ci, Rsir, Cpmr or Rsmr and Csrr or Rprr. al ap, as denote the set ~a excluding both ap and as, as (ap) is the character in an a+ enq sequence which designates it as a selection (polling) establishment sequence (request). A speQific installation will use individual a symbols in the string a+ ap a* enq (a+ as a* enq) to select one (one or all) remote device(s)-and to further select which subdevice is being addressed-such as either card or paper tape reader

GRAPH 46

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• •• denote 2!!l system state - - - a I

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We have so far shown the line turnaround function just by the transition A, see Graph A, Figure 11. If we address ourselves to a specific system implementation we may then show A far more explicitly, e.g., by either of two half-duplex extremes shown in Graphs Al and A2 (Figure 12). In the first scheme (Graph AI) the transmitting device terminates each communication by 2 or more syn patterns subsequently followed by· a mark condition; after. at least two received syn patterns the receiving device now becomes the transmitting device and first sends at least 2 syn patterns. While this device was in receive mode it constantly held its send line in mark condition.

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Figure lO-GRAPH 46 Fourth level invalid reply subsystem

Figure l2-Fourth level line turnaround subsystem Graph AI: Conventional half duplex Graph A2: Synchronous transmit/receive

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Fall Joint Computer Conference, 1970

Bit versus byte oriented definition GRAPHS 60 character tr."sition:

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corresponding USASCII bit transition:

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GRAPHS 151 character trntion:

~

We may break the level four graphs down even further; our next more detailed level may take a bit as the smallest indivisible token (see Graphs 50 and 51, Figure 13). We choose however not to go to the fifth level for several reasons. One is that we tend to think of line control procedures as character oriented. Another is that in our implementation we decompose the fifth level bit-to-character assembly out of the general graph and implement it as a simple shift register (serializerdeserializer) from which characters are read/decoded in parallel over all bits.

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Alternating replies

In certain line control schemes text messages are acknowledged on an alternating basis, i.e., either ackO

for even-numbered blocks and ack1 for odd-numbered or ackn where n ranges over 0-9. We have not shown this in our graphs but will now do so using Graphs 42 and 45 (Cpmr) (See Graph 6, Figure 14).

becomes:

GRAPH 6

Figure 13-GRAPHS 50 and 51 Fifth level character subsystem

In the latter scheme (Graph A2) a device in receive mode always transmits syn patterns and a shift to transmit mode can thus be effected immediately after receipt of the last character before syn.

CHARACTERIZATIONS We now pause to characterize the type of transition graph that we have so far produced.

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G42 n

Scope of definition

The graph(s) on level four define all valid (correct) sequences which we may encounter on a data communication link under control of a TWO WAY ALTERNATE NONSWITCHED MULTIPOINT system WITH CENTRALIZED OPERATION. The definition uses a line character as its 'smallest' indivisible token.

Figure 14-GRAPH 6 Simplified fourth level alternating acknowledgment subsystem

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Finite State Automation

Instead of showing repeated instances of the same graph G42°- n , G45o- n ) one can decompose Graph 6 into one single instance of Graphs 42 and 45 combined with a single counter (O-n). Again this is the way we would implement such a system. But even on Graph 6 or on the suggested decomposed graph we have not quite shown the fact that a nak response often requires the error-free retransmission of the same block, characterby-character as was erroneously communicated. Here perhaps an English worded definition is superior to a graph description. One could suggest that the latter would make use of a queue or buffer into which we put characters as we generate them. The buffer or queue content would be reused if a nak response was received. Otherwise it would be overwritten during the next transmission.

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It is well known that the transition graphs we have shown so far can be interpreted in a mechanical way as either hardware implementable sequential circuits or soft-ware implementable tables. First, however, some words on syntax, semantics and pragmatics. The graphs represent the syntax or the grammar defining all valid character sequences. In the implementation one is also interested in:

• What to do with invalid character sequences? • How to react to any sequence, valid or invalid? So far our graphs show only generative capability but we can easily augment the graph or its corresponding tabular representation to show the answers to both of the above questions. Take for example Graph 42 shown on Table 1 (Figure 15). To give informally stated examples of what we mean and imply by actions/semantics we list a few examples: a; Start-of-header; set up suitable (hardware) buffer, initialize (hardware) variables.

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18 45.4

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15

The graph definition implementation

itb

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14

Definition, implementation, syntax, semantics and pragmatics

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8

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Half duplex

dIe 10 c

3

13

The graph definition truly depicts the half duplex nature of our line usage. We shall return later with thoughts on how a transition graph definition might be used to define full duplex line control procedures.

483

15

17

The letters denote appropriate actions, i.e. semantics. Unspecified (blank) entries all have next state transition to the error state 19 with some appropriate action, suitably depending on the present state.

Figure 15-TABLE I Tabular representation of state transition graph 42. The letters denote appropriate actions, i.e., semantics. Unspecified (blank) entries all have next state transition to the error state 19 with some appropriate action, suitably depending on the present state

b. Start-oj-text; no header, set up out device/text buffer, initialize text variable. c. Start-oJ-transparent-text; no header, no nontransparent text, set up out device/transparent text buffer, initialize transparent text variable. d. First header character, hardware count: = 1. e. Subsequent header character, hardware count: = hardware count 1; buffer full? or output in character to out device. f. End-oj-header, store hardware count, interpret header; start-oj-text, set up text buffer and initialize text variable. g. End-oj-header, ... , start-oJ-transparent-text, so far no nontransparent text, set up out device/ text buffer and initialize variable, disable parity check. h. First text character; text character: = 1; output in character to out device/buffer. j. Subsequent text character; text character: = text character 1; ....

.+

+

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Fall Joint Computer Conference, 1970

k. End-of-transmission-block, no text, interpret header, wait for block check .character, disable parity check. q. Transparent text data, use as such. r. End-of-transparent-text-data, start-of- (nontransparent) -text reinitialize variables. We have and shall not define the pragmatics of line control procedures rigorously (formally). Some of the pragmatics here are concerned with the length of prefixes, headers, and text data and with the principles of retransmission and error recovery procedures. Through this augmentation we have converted our graph from a generator into a transducer: a machine accepting and transducing (controlling the translation of) the generated sequences. This machine can be implemented either strictly in wired logic, as a micro program in a general purpose transmission control unit or as a software table switching/look-up mechanism. We shall comment further on this. Completeness

We wish to demonstrate the COMPLETENESS of our definition. That is, we can prove that we have considered all possible character sequences and rigorously defined syntactically and semantically which are correct and what to do with valid as well as invalid sequences. Our definition and our implementation is therefore unambiguous, each taken separately or both taken together. The argument goes somewhat like this: (1) There is a finite number of states (nodes) in our graph. (2) In each state only a finite number of valid input (transducer/recognizer) or output (generator) characters is possible. Thus we only have to make a finite number of decisions in building our graph. The graph is the proof. The design style and structure that the graph approach imposes on us is appealing. Specification changes

munication transactions we can mention the possibility of letting both phases be software or hardware controlled through the same graph in both the master (c) and remote (r) systems. That is, the total collection of state transition Graphs 42-46 coimected as shown by Graph 3 is present in either type of device. Subgraphs Ci, Csm, Csrr, Cst and Cpmr will be used by system c as generators whereas any device in system r will use them as transducers and vice versa-subgraphs Rsir, Rsmr, Rpt, Rpm and Rprr will be used by system c as transducers whereas anyone device in system r will use them as generators. To use a graph as a generator may not seem to have a practical meaning in any particular instance of a transaction. The generator generates all correct transactions, not a particular one. But somehow, someone (be it a human being at a terminal or the automatic program in a CPU at the central system) generates a particular instance based on a few parameters (v) such as (1) poll or select, (2) device address, (3) header/no header, text/no text just header, (4) possible embedded transparent text segments, (5) blocked/nonblocked messages, (6) length of prefixes, headers and text segments and (7) pointers to prefix (p), header (h), and text (t) segment buffers. What we mean by the generator generating a particular instance should now be more clear. Let us visualize a system (Figure 16) where c selects r and sends messages to r. Gc is the generator {Ci, Csm, Csrr, Cst}, Tc is the transducer {Rsir, Rsmr}; Tr is the transducer {Ci, Csm, Csrr, Cst} and Gr is the generator {Rsir, Rsmr}. Gc uses parameters v and subsequently also link parameters from Tr while stepping through the appropriate transition graphs (sequential machines, micro programs or software tables). Gr uses link parameters from Tr in its stepping through appropriate graphs. By link parameters we mean the information shown in Graphs 42-46 relating the outcome (final state) of some graph (say 42.16) to one or more initial states in connected graphs (here 45.1).

Changes in the definition of line control procedures can be readily effected. The graph approach immediately reflects all nodes which may be affected by a change. This is true for generators as well as for recognizers/transducers. Generator and recognizer duality

N ow that we have seen that the graphs represent both the generation and the transduction of data com-

Figure 16-Two way alternate non-switched multipoint system with centralized operation of subsystems r from subsystem c

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Finite State Automation

GRAPH 70

Input:

G--. }; ~{d,s,p,e J

GeneratOr IG)

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Figure 17-GRAPH 70 ALGOL 60 number generate graph. Fourth level

'f.he stepping process thus uses the parameters in order to resolve next generator output in cases where more than one next output character is correct. For example, in Graph 4, state 1, if the v parameter indicates 'header,' then soh is output and the generator graph action directs the control to fetch pointer to and length of header buffer from v and to start outputting header information. The header characters are matched against the a's, i.e., a state transition from 4.2 to 4.3 and then recursively to 4.3 occurs unless the header buffer contains invalid information, i.e., characters different from, say, a. When the header buffer is exhausted the control again looks at v to see whether any text transmission is required, etcetera. Note here that we use the generator graphs in two ways. In between prefix, header and text segments as a generator, otherwise as a check (recognizer) on the correctness of these segments. If, e.g., a header segment contained 'stx' then a transition to state 4.4 would occur. Depending on implementation we could either

GRAPH 71

485

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next state

present state

output S={1,2,3,4,5,6,7}

Figure 19-TABLE II Fourth level tabular representation of Graph 71, Figure 18

use this transition to signal error, or the graph, when the header buffer subsequently became exhausted, would signal error because of the repeated attempt to output stx (from state 4.5).

Rec09l'lizer I R) 1: = { d,s,p,e } denote input,

e-

THREE BASIC IMPLEMENTATION SCHEMES

A = {+,-,+ } denote output, +

As pointed out in above, the generator definition equals the transducer implementation. In this section we show three such. The first is based on Graphs 70, (Figure 17) and 71 (Figure 18). The equivalent tabular representation is shown in Table 2, Figure 19 (Table 2 defines ALGOL-60 {numbers )'s). The three schemes are:

denotes error output.

1. Hardware sequential machine or automaton

Figure 18-GRAPH 71 ALGOL 60 number recognize graph. Fourth level

using logic gates and flip-flops. 2. Micro program in read-only/writable control store. 3. Software program in main core.

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Fall Joint Computer Conference, 1970

486

Input: X Input el:

1

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01

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0

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110

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100

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Yn

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present state eS

next state eS

State Register R

Figure 20-First Niveau sequential machine model

Scheme 1: A Finite State Machine (FSM)

The model of a hardware implemented fsm is given in Figure 20. C maps ~XS into AXS. The mapping is given in Table 2. The number of flip-flops needed in R is n ~ Log2 (the number of states in S) , n suitably being the smallest integer larger than or equal to Log2 ( I S I ) • We choose n = 3; and let + == -, i.e., we do not distinguish between these two symbols. In Table 3, Figure Figure 22-TABLE IV Binary tabular representation of variable Ya in Table III, Figure 21

34

Input: d=OO

5=01

p=l1

000

State:

001

0101

1:)100

0110

1010

011

1001

1110

1110

1110

3

010

0101

1110

0110

1010

2

no

1101

1110

1110

1110

6

111

1110

1110

1110

1110

7

101

1101

1100

1110

1110

5

1001

1110

1110

1010

4

Figure 21-TABLE III Fifth level binary tabular representation of Table II, Figure 19

21, we have coded 8E S as the binary number shown in Table 2. (This happens to be a 'not so good' internal state coding.) Output '+' is coded as logical '1,' '-' and '+' both as '0.' Input d='OO,' 8='01,' p='ll' and e='10.' Note that in Table 3, row 000, state 0 is undefined. We can fill entries in row 000 with whatever Y1 Y2

Figure 23-Third Niveau logic primitive implementation of variable Ya in Table IV, Figure 22

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Finite State Automation

Xl I---I-----~

Z

487

output ('controls to DF') (e.g. {+, -, + }), s' goes back to Sreg and the WC S is ready to serve another line. If the WCS is to manipulate the input (i.e., possibly store u in a TCU line buffer (lbf) , changing code structure, incrementing lbf address, decrementing character count) then (s, u) initiates a several microword subroutine via the (su) loop. Branches in this routine are determined by conditions in the DF. The last micro instruction contains s' and directs s' to Sreg whereafter the WCS is again ready to serve any line. All this is very trivial. What we should note however is that the basic flow of the microprogram, i.e., the proper sequencing of subroutines, is completely derived from (e.g.) Graphs 42-46. In other words if we change the definition of line control procedures then we can mechanically relate such changes to the microprogramming of the TC U. Scheme 3,' Software controlled recognition and transduction

clock

Figure 24-Second Niveau logic block implementation of sequential machine model of Figure 20

Y3 Z values we might find useful. From Table 3 we then compute Yi (i= 1,2, 3) and Z as a Boolean function: f(x1, x2, y1, y2, y3). Take for example Y3 or Y3 shown in Table 4, Figure 22. The logic for Y3 (C Y3 ) is indicated in Figure 23, and a typical implementation from Figure 20 is shown in Figure 24.

Let Table 2 or 3 be stored as a three dimensional array T (1: I S I , 1: j ~ I , 1: 2) where I X I denotes the number of elements in the set X. The next state part of the table is stored in T(*, *, 1) whereas the output or action label part is stored in T(*, *,2). Let INDEX (CHARACTERSET, SYMBOL) map classes of 8 bit MICRO·PROGRAM

~T~'~~,~D

t()} Ii

I

Scheme 2,' A microprogrammed transmission control unit (p,TCU)

I~

,~"

LJ=

-~-~

controls to OF

conditions to OF DATA FLOW (OF)

The p,TCU is to serve many independent lines sharing the same microprogram for their identical line control procedures. In Figure 25 we show only the principles of the line input data flow: An input character is de-Serialized in SdS, transferred in parallel to BF and when serviceable by the writable control store (WCS), the input (u E ~) and the present state (s E S) which is kept in Sreg are transferred to the WCS address decoder. If the WCS is to act only as a recognizer then just Table 2 (or some other appropriate table, e.g., Table 1) is stored in WCS. The WCS word addressed by (s, u) has value (s', 0) where s' is the next state and 0 is the

1=== I ---

I/O +- 1 - - interface bus in ~

r

1

I I I I I

~IH~ I

I

If +

I

I I I

I I

•••

Sreg

rBl

I

ne.t state:s'

LINE ADAPTER

~

Figure25-Micro-programmed data eommunication control unit. Only the input (read) data flow is shown

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488

Fall Joint Computer Conference, 1970

Program 1: PROGRAM:

PROCEDURE OPTIONS (MAIN); DECLARE

~~~~~T~~~C~~:R1~fER

(60), '''INITIALIZE PROPERLY'" INPUT_CLASS (0:60) FIXED BINARY (7), '''INITIALIZE PROPERLY'" T (l:S, 1:1:, 1:2) FIXED BINARY (15), '''INITIALIZE PROPERLY'" (INPUT. PRESENTSTATE) FIXED BINARY (15);

r

PRESENTSTATE ,. 1; GET EDIT (SYMBOL) (A(l»; INPUT = INPUT-CLASS (INDEX (CHARACTERSET .SYMBOL»; CALL ACTION (T (PRESENTSTATE. INPUT. 2»; PRESENTSTATE = T (PRESENTSTATE. INPUT. 1); L -_ _ _ _ GO TO READ;

ACTION:

EAD

:

PROCEDURE (L); DECLARE SWITCH (N) LABEL INITIAL (ACTl. ACT2 ••••• ACTN) ; GO TO SWITCH (L);

·· · . ·· · ··00 ·· · ·

ACTl :

RETURN;

ACT2:

RETURN;

actions associated with val id input sequences

ACTM~

RETURN;

schemes hitherto proposed could more appropriately either be called (termed) doubly interleaved half duplex or even just ordinary double simplex. This situation is truly reflected in the scheme next discussed. First we assume that the transmission is point-topoint or that if we have a multipoint (N) 2 station-) system. Then we assume that 2 out of N stations have been selected for point-to-point communication, and that the remaining N - 2 stations 'listen' to both of the two-way simultaneous communication. We shall not here elaborate on the selection problem. N ext we postulate that a definite full duplex data communication line control procedure exists. We finally assume that the text message, text-reply and replyrequest scheme shown in Graphs 3, 42-46 is the one used but that we interleave these in a threaded manner when going full duplex . The constraints put on (or rules defined by) the postulated procedures are therefore:

ACTM1:

GO TO EXIT;

ACTM2:

TO EXIT;

actions associated with invalid input sequences

ACTN:

GO TO EXIT;

END ACTION; EXIT: END PROGRAM;

Figure 26-Pseudo PL/l program

symbols into the set {I, 2, ... , I ~ I }. The pseudo PL/1 program on Figure 26 shows the generalized software program control statements into and around which any finite state algorithm can be arranged. 6 Conclusion

It may be argued that we have shown nothing spectacularly new. in the three schemes-the main reason we include this section is to demonstrate the clear-cut relation between definition and implementation-a relation which can be carried out mechanically, i.e., automatically. One is therefore greatly aided when having to decide whether a given scheme is to be implemented using method 1, 2 or 3. FULL DUPLEX Before describing how we would go about defining (and implementing) a full duplex scheme, the following brief remark or observation may be appropriate: It appears (at least to this author) that all full duplex

Rule 1: When one station (A) sends a 'packet' of type: 'text-block,"reply' or 'reply-request,' then the other station (B) either sends "nothing" ("null"), synchronization (syn) symbols or sends a "packet" of the same type. A termination sequence, eot, has type: text-block. 'Text-block' and 'reply-request' are packets of the same type. This corresponds to the logic of Graph 2, Figure 2. Rule 2: The exact mutual character-by-character sequence need not necessarily match. That is, any time combination of A orB beginning or ending their "packet" transmission is allowed.

Rules 1 and 2 guarantee that the two way line will never carry packets of different types at anyone time. The example shown in Figure 27 is a particular instance of a set of line transactions. Note specifically the situation after text-blocks m2 where B first sends ack1 reply to m2(A~B), then reply-request !! in response to an erroneously received ack1 = i from A; not before B has received a correct reply (either ackn or nak) can B proceed to text-block ma. Concurrently: A has received an affirmative answer to m2(A~B), so A proceeds to ma (A ~B) before it has cleared the m2(B~A) reply. In order, therefore, to synchronize these two processes properly we employ the following two indivisible operations7 which we define using a pseudo PL/l notation: S: SET:

PROCEDURE (semaphore); semaphore: = 1; END SET;

From the collection of the Computer History Museum (www.computerhistory.org)

Finite State Automation

489

EXAMPLE, Full Duplex File Transmission

A-B

•••

B-A

A-B

B-A

transmission from X toY initialization of XfromY X sends a sequence, but Y receives /3 sequence initialization of Y from X

received, this release is accomplished through S ('YB), or releases TGb through S (aB) . 4. If RRGb was initialized then a transition to state B6 will enable RRb to state B9. A completion of the request-reply recognition again releases {3A thus enabling RGa and the two corresponding components RRb and RGa are thus brought to synchronize. We point this out here, but could as well do it for the cases where TGb in state B2 enables RRb to state B9 simultaneously with TRa in state A2 ("'B2) releasing {3A thus enabling RGa in state A9 ("'B9). 5. In more general terms: The possibility that a generator G of type x E {T, R, RR} in station u E {A, B} enables a recognizer R of type y E {R, RR or T, R} (taken in corresponding order) before the type x recognizer (xRu) has reached home condition (i.e., final- or end-state) should not bother us. yRu will not receive input before xGv has reached its home condition, v¢u. We thus see that the system· of three semaphores {a, {3, 'Y} in each of two communicating stations com-

GRAPH 10

Figure 27-Example. Full duplex file transmission

H: HOLD: PROCEDURE (semaphore) RECURSIVE; IF semaphore = 1 THEN semaphore: = 0; ELSE HOLD (semaphore); END HOLD; 2!A~B~i-BiI

On Graph 8, Figure 28, we have shown the totality of generator (- G) and recognizer (- R) graphs in both stations and we have explicitly shown details concerning half of the otherwise symmetric channel traffic, in this case: text blocks mB~A. 1. While text block generator TGb in B transmits mB~A the text block recognizer TRa in A is receiving that same message. 2. When TRa has received all ef mB~A then it releases the reply generator RGa. The release is accomplished through S({3A) and may precede, coincide with or succeed the time at which TGa ends transmission, i.e., goes to state A8. 3. When the reply recognizer RRb has received the reply then it: either releases the request-reply generator RRGb because an erroneous reply was

______ . ____ . ___ _

STATION A Istatej-Aj)

Figure 28-GRAPH 8 Third level full duplex file transmission. Generator and recognizer system

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490

Fall Joint Computer Conference, 1970

pletely interlocks proper sequences. The semaphore values are initially {I, 0, O}, with respective TR's enabled. 6. One further note: observe that if xGu at time 't' goes to state j (uj) then xRv will at time 't+~' go to either the error state or vj. This is true for all state transitions. We might say that the recognizer is always one time step (~) behind its associated generator, ~ being the time it takes to serialize, transmit and deserialize a character. In this specific example we do not require the indivisibility of the Hand S semaphore operators. Thus we have not demonstrated the particular virtues of H and S. For the synchronization of more than two lines, however, one is greatly aided by such primitive operators. Our example demonstrated the notion of (two) cooperating sequential processes. As such it conceptually belongs to the field of parallel computations. This is presently being studied intensely. In fact, it is proper here to refer to the pioneering work by Petri8 and Holt. 9 Their work essentially embodies the research suggested by Lynch. 10 In fact, Graph 8 is a somewhat transformed version of a Petri net as defined by Holt. Our graph not only shows the algorithmic parallelity but in addition indicates an implementation.

Input:

State:

char

~

eoa

sot

eob

2 (1)

3

3

3

3

2

3

4 (2)

3

3

3

f: e: 3

3

3

3

3

3

4

5 (4)

3

7 (9)

6 (3)

3+

5

3

3

7 (8)

3

3

6

5 (4)

6 (5,7)

6 (5,6)

6 {3}

3+

7

5 (4)

3

8 (10)

6 (3)

3+

8

5 (4)

3

9 (11)

6 (3)

3+

9

5 (4)

3

3

6 (3)

3+

i: 1

Figure 29-TABLE V Finite state transducer

The regular expression R (G) is: ~ sel (eUcharUchar charUchar char char)

(sot ( charUsel) *Ueoa (charUchar char Uchar char char) )*eob and the mechanically constructed finite state machine top-down transducing L (G) = I R (G) I is shown in Table 5, Figure 29.

PRODUCTION SYSTEM DEFINITION As a final (although non-graphical) way of completely and compactly defining a set of line transactions we now show how the language acceptable by an IBM 1070 process communication systeml l IBM 1071 terminal control unit in text mode can be specified through a top-down LL (1) 12 grammar G: (1) (2)

w B

~

eoaB

~selM

Teob

T~TT

(3) (5) (6) (8) (9) (10) (11)

T~

sot S

T~

(4)

T~eoaA

(7)

C

S~CX

C

~

char

S~

~sel

A~charD M~charD

M~

D~charH

D~

H~

H~

2; =

char

{eoa, sel, char, sot, eob}

where char denotes a larger alphabet.

CONCLUSION

It is our hope that we will achieve the objective: that of data communication line control procedures being defined through some compact, complete and unambiguous methodology which lends itself to levels of abstraction and to well structured implementations. This results in better designed communication subsystems, be it software, hardware, firmware or all. The implications are:

1. Better control of engineering changes if any are needed. 2. A much more generalized service engineering training. 3. Systems which are easier to diagnose-visualize that we use all error state transition actions in our diagnostics, and we know a priori that we have dealt with all possibilities. 4. Much better chances of implementing new exotic line control schemes fast and efficient.

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Finite State Automation

5. Reliable techniques for evaluating and comparing different implementations software, firmware or hardware, and through the hierarchical structuring, any mix of these.

We have chosen the model of finite state graphs, rather than that of a context-free grammar. We did so because the communications control processes are of a finite state nature. The context-free grammar model is too powerful for our purposes and the finite state graph model is claimed easier to grasp. One is in particular aided by the visuality rather than the formality. The theory of (finite state) automata and formal languages has come a long way. There are scores of important results waiting to be used practically.

5

6

7

8

ACKNOWLEDGMENT The author is indebted to Akira Saito of IBM Japan for pointing out a subtle error in a first draft.

9

REFERENCES 1 IBM CORP General information, binary synchronous communication IBM Systems Reference Library (SRL) Form No A27-3004 2 J EISENBIES Conventions for data communication IBM Systems Journal Volume 6 Number 4 pp 267-302 1967 3 ANSI USA proposed standard data communication control procedures for USASCII Communications of the A CM Volume 12 Number 3 pp 166-178 March 1969 4 B RANDELL F W ZURCHER Iterative multilevel modeling, a methodology for computer systems design IFIP Congress 68 Edinburgh August 5-10 1968 and B RANDELL Towards a methodology of computer system design

10

11

12

491

NATO science committee report: Software engineering pp 204-208 Garmisch Germany October 7-111968 E W DIJKSTRA The structure of T.H.E. multiprogramming system Communications of the ACM Volume 11 Number 5 pp 341-346 May 1968 and E W DIJKSTRA Complexity controlled by hierarchical ordering of function and and variability NATO science committee report: Software engineering pp 181-185 Garmisch Germany October 7-111968 D BJ0RNER Flowchart machines IBM research report RJ685 San Jose California April 1970 E W DIJKSTRA Cooperating sequential processes Programming Languages Ed F Genuys Academic Press Chapter 2 pp 43-112 New York 1968 C A PETRI Kommunikation mit automaten Schriften des Rheinisch-Westfalischen Institut fUr Instrumentelle Mathematik Universitat Bonn Nummer 2 1962 A W HOLT Information System theory project Report Applied Data Research Inc Princeton New Jersey September 1968 and A W HOLT F COMMONER Events and conditions, An approach to the description and analysis of dynamic systems Report Applied Data Research Inc Princeton New Jersey 1970 W C LYNCH Commentary on the foregoing note Communications of the ACM Volume 12 Number 5 pp 261 and 265 May 1969 IBM CORP IBM 1070 process communication system IBM System Reference Library (SRL) Form Number A26-5780pp 14-181968 D BJ0RNER The theory of finite state syntax directed transductions PhD Thesis Laboratory for Pulse- & Digital Techniques Technical University of Denmark Copenhagen January 1969

From the collection of the Computer History Museum (www.computerhistory.org)

From the collection of the Computer History Museum (www.computerhistory.org)