Final Exam Review • Combinational Logic Building Blocks: – Decoders, Encoders, Multiplexers, Demultiplexers

– Implementing functions using decoders, multiplexers. • Combinational Arithmetic Circuits: – Adders, Subtractors, Multipliers, Comparators, shifters.

• Sequential Logic Circuits: – Latches, Flip-Flips.

• Clocked Synchronous State Machines: – State Machine Analysis – State Machine Design • Registers & Counters. EECC341 - Shaaban #1 Final Review Winter 2001 2-20-2002

Binary n-to-2n Decoders • A binary decoder has n inputs and 2n outputs. • Only the output corresponding to the input value is equal to 1.

n inputs

:

n to 2n decoder

:

2n outputs

EECC341 - Shaaban #2 Final Review Winter 2001 2-20-2002

3-to-8 Binary Decoder Truth Table: F0 = x'y'z' x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z F0 F1 F2 F3 F4 F 5 F6 F7 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1

F1 = x'y'z F2 = x'yz' F3 = x'yz F4 = xy'z' F5 = xy'z F6 = xyz'

F0

F7 = xyz

F1 X Y Z

3-to-8 Decoder

F2 F3 F4 F5 F6

x

y

z

F7

EECC341 - Shaaban #3 Final Review Winter 2001 2-20-2002

Implementing Functions Using Decoders • Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2n decoder to generate the minterms, and an OR gate to form the sum. – The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. • Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates. • Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

EECC341 - Shaaban #4 Final Review Winter 2001 2-20-2002

Implementing Functions Using Decoders • Example: Full adder S(x, y, z) = Σ (1,2,4,7) C(x, y, z) = Σ (3,5,6,7)

3-to-8 0 Decoder 1 x

S2

y

S1

z

S0

2 3 4 5 6 7

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

C 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

S

C

EECC341 - Shaaban #5 Final Review Winter 2001 2-20-2002

Encoders • If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2n-to-n, priority encoders. • The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs = 1 and the output is the n-bit binary number corresponding to the active input. • For an 8-to-3 binay encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are: Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7

2n inputs

. . .

Binary encoder

. . .

n outputs

EECC341 - Shaaban #6 Final Review Winter 2001 2-20-2002

8-to-3 Binary Encoder At any one time, only one input line has a value of 1.

Inputs

I0 1 0 0 0 0 0 0 0

I1 0 1 0 0 0 0 0 0

I2 0 0 1 0 0 0 0 0

I3 0 0 0 1 0 0 0 0

I4 0 0 0 0 1 0 0 0

Outputs

I5 0 0 0 0 0 1 0 0

I6 0 0 0 0 0 0 1 0

I7 0 0 0 0 0 0 0 1

y2 0 0 0 0 1 1 1 1

y1 0 0 1 1 0 0 1 1

y0 0 1 0 1 0 1 0 1

I0 I1

Y2 = I4 + I5 + I6 + I7

I2 I3

y1 = I2 + I 3 + I6 + I 7

I4 I5 I6 I7

Y0 = I1 + I3 + I5 + I7

EECC341 - Shaaban #7 Final Review Winter 2001 2-20-2002

Multiplexers • A multiplexer (MUX) is a digital switches which connects data from one of n sources to the output. • A number of select inputs determine which data source is connected to the output. Enable

1Y

D0

Multiplexer EN s bits Select

2Y

SEL Data output

b bits D0 b bits D1 n Data Sources

. . b bits

Y

D1 . . .

. . . bY

Dn-1

Dn-1

SEL

EN

EECC341 - Shaaban #8 Final Review Winter 2001 2-20-2002

4-to-1 MUX Truth table for a 4-to-1 multiplexer: I0 d0 d0 d0 d0

I1 d1 d1 d1 d1

I2 d2 d2 d2 d2

I3 d3 d3 d3 d3

S1 0 0 1 1

S0 0 1 0 1

Y d0 d1 d2 d3

Inputs I0 I1 I2 I3

S1 0 0 1 1

S0 0 1 0 1

Y I0 I1 I2 I3

Inputs 0 4:1 1 MUX Y 2 3 S1 S 0

I0 I1 Output

I2

mux

Y

I3 S1 S 0

select

select

EECC341 - Shaaban #9 Final Review Winter 2001 2-20-2002

4-to-1 MUX Circuit I0

I0

I1

I1 Y

I2

Y

I2 I3

I3 0 1 2 3 2-to-4 Decoder

S1 S0

S1

S0

EECC341 - Shaaban #10 Final Review Winter 2001 2-20-2002

Larger Multiplexers • Larger multiplexers can be constructed from smaller ones. • An 8-to-1 multiplexer can be constructed from smaller multiplexers as shown:

I0 I1 I2 I3

4:1 MUX S1 S 0

I4 I5 I6 I7

4:1 MUX

2:1 MUX

S2

Y

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

Y I0 I1 I2 I3 I4 I5 I6 I7

S1 S 0

EECC341 - Shaaban #11 Final Review Winter 2001 2-20-2002

Larger Multiplexers • A 16-to-1 multiplexer can be constructed from five 4-to-1 multiplexers:

EECC341 - Shaaban #12 Final Review Winter 2001 2-20-2002

Demultiplexers • Digital switches to connect data from one input source to one of n outputs. • Usually implemented by using n-to-2 n binary decoders where the decoder’s enable line is used for data input of the demultiplexer.

Demux

b bits

Select Data Input

One of n Data Sources selected

Select lines

b bits . . b bits

One of n outputs

s bits

2X4 Decoder

Input data (1bit)

One of four 1-bit outputs

Enable

1-bit 4-output demultiplexer using a 2x4 binary decoder.

EECC341 - Shaaban #13 Final Review Winter 2001 2-20-2002

1-to-4 Demultiplexer Outputs Y0 = D.S1 '.S0' Y1 = D.S1 '.S0 Data D

demux

Y2 = D.S1 .S0' Y3 = D.S1 .S0

S1 So 0 0 0 1 1 0 1 1

Y0 D 0 0 0

Y1 0 D 0 0

Y2 0 0 D 0

Y3 0 0 0 D

S1 S 0 select

Y0 = D.S1 '.S0' S1

2x4 Decoder

S0

Y1 = D.S1 '.S0 Y2 = D.S1 .S0'

E

Y3 = D.S1 .S0

D

EECC341 - Shaaban #14 Final Review Winter 2001 2-20-2002

Implementing n-variable Functions Using 2n-to-1 Multiplexers • Any n-variable logic function, in canonical sum-ofminterms form can be implemented using a single 2n-to-1 multiplexer:

– The n input variables are connected to the mux select lines. – For each mux data input line Ii ( 0 ≤ i ≤ 2n - 1): • Connect 1 to mux input line I i if i is a minterm of the function. • Otherwise, connect 0 to mux input line Ii (because i is not a minterm of the function thus the selected input should be 0). EECC341 - Shaaban #15 Final Review Winter 2001 2-20-2002

Example: 3-variable Function Using 8-to-1 mux • Implement the function an 8-to-1 mux.

F(X,Y,Z) = Σ(1,3,5,6) using

– Connect the input variables X, Y, Z to mux select lines. – Mux data input lines 1, 3, 5, 6 that correspond to function minterms are connected to 1. – The remaining mux data input lines 0, 2, 4, 7 are connected to 0. Mux Data Input Lines

0 1 0 1 0 1 1 0

0 1 2 3 mux 4 5 6 7

X Y Z

F

Mux Select Lines

EECC341 - Shaaban #16 Final Review Winter 2001 2-20-2002

Implementing n-variable Functions Using 2 n-1-to-1 Multiplexers •

Any n-variable logic function can be implemented using a smaller 2 n-1-to-1 multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variable functions) as follows: – Express function in canonical sum-of-minterms form. – Choose n-1 variables as inputs to mux select lines. – Construct the truth table for the function, but grouping inputs by selection line values (i.e select lines as most significant inputs). – Determine multiplexer input line i values by comparing the remaining input variable and the function F for the corresponding selection lines value i: • Four possible mux input line i values: – Connect to 0 if the function is 0 for both values of remaining variable. – Connect to 1 if the function is 1 for both values of remaining variable. – Connect to remaining variable if function is equal to the remaining variable. – Connect to the inverted remaining variable if the function is equal to the remaining variable inverted.

EECC341 - Shaaban #17 Final Review Winter 2001 2-20-2002

Example: 3-variable Function Using 4-to-1 mux • Implement the function F(X,Y,Z) = Σ(0,1,3,6) using a single 4-to-1 mux and an inverter. – We choose the two most significant inputs X, Y as mux select lines. – Construct truth table: Select Lines Select Lines Value i

0 1 2 3 •

X

Y

Z

F

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 0 1 0 0 1 0

Mux Data Input Lines

Mux Input i

1

1

0 1

Z Z

0

2

mux

F

3

0 X Y

Z’

Mux Select Lines

We Determine multiplexer input line i values by comparing the remaining input variable Z and the function F for the corresponding selection lines value i: – – – –

when XY=00 the function F=1 (for both Z=0, Z=1) thus mux input0 = 1 when XY=01 the function F=Z thus mux input1 = Z when XY=10 the function F=0 (for both Z=0, Z=1) thus mux input2 = 0 when XY=11 the function F=Z’ thus mux input3 = Z’

EECC341 - Shaaban #18 Final Review Winter 2001 2-20-2002

Combinational Arithmetic Circuits • Addition: – – – –

Half Adder (HA). Full Adder (FA). Carry Ripple Adders. Carry Look-Ahead Adders.

• Subtraction: – – – –

Half Subtractor. Full Subtractor. Borrow Ripple Subtractors. Subtraction using adders.

• Multiplication: – Combinational Array Multipliers. EECC341 - Shaaban #19 Final Review Winter 2001 2-20-2002

Full Adder •

Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit.

Sum S

X XY

00

C-in

01

0

Full Adder Truth Table

1

Inputs

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

1

Outputs

C-in 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

2

0

C-out 0 0 0 1 0 1 1 1

S(X,Y, C-in) = Σ (1,2,4,7) C-out(x, y, C-in) = Σ (3,5,6,7)

11 6

1

3

1

10

7

4

1

5

1

C-in

Y

S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in) S = X ⊕ Y ⊕ (C-in)

Carry C-out

X

XY

00

C-in

01

0

2

1

3

11 6

0 1

1

7

1 1

10 4 5

1

C-in

Y

C-out = XY + X(C-in) + Y(C-in)

EECC341 - Shaaban #20 Final Review Winter 2001 2-20-2002

Full Adder Circuit Using AND-OR X’ Y’

X X’

X

C-in X’ Y C-in’

Y Y’

Y

X

X’YC-in’

Sum S

X Y

C-in C-in’

C-in

X’Y’C-in

Y

C-in’ X Y C-in’

X

XY’C-in’

XYC-in

XY

Y

C-out

Full Adder

C-in

X

XC-in

C-out

C-in Y

S

C-in

YC-in

EECC341 - Shaaban #21 Final Review Winter 2001 2-20-2002

n-bit Carry Ripple Adders •

•

An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders. – Each full adder represents a bit position j (from 0 to n-1). – Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. The output of a full adder at position j is given by: Sj = Xj ⊕ Yj ⊕ Cj Cj+1 = X j . Yj + Xj . C j + Y . C j

•

In the expression of the sum Cj must be generated by the full adder at the lower position j-1.

•

The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 ∆

•

Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay

= 2 n∆ ∆

EECC341 - Shaaban #22 Final Review Winter 2001 2-20-2002

4-bit Carry Ripple Adder Inputs to be added

Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3

X3X2X1X0

C4

C-out

= 2 n∆ ∆ = 8∆ ∆

Total Propagation delay

Y3Y2Y1Y0

4-bit Adder

C0 =0

C-in

S3 S2 S1 S0

or 8 gate delays

Sum Output

Data inputs to be added X3

C4

C-out

Y3

Full C3 C-in Adder S3

X2

C-out

Y2

Full C2 C-in Adder

X1

C-out

S2

Y1

X0

Full C-in Adder S1

C1

C-out

Y0

Full C-in Adder

C0 =0

S0

Sum output

EECC341 - Shaaban #23 Final Review Winter 2001 2-20-2002

Larger Adders • Example: 16-bit adder using 4, 4-bit adders • Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position. Data inputs to be added X (X0 to X15) , Y (Y0-Y15) X3X2X1X0

C16

C-out

Y3Y2Y1Y 0

X3X2X1X0

Y3Y2Y1Y 0

4-bit 4-bit C12 C8 C-in C-in C-out Adder Adder

S3 S2 S1 S0

S3 S2 S1 S0

X3X2X1X0

C-out

Y3Y2Y1Y 0

4-bit C-in Adder

X3X2X1X0

C4

S3 S2 S1 S0

C-out

Y3Y2Y1Y 0

4-bit C-in Adder

C0 =0

S3 S2 S1 S0

Sum output S (S0 to S15)

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 n∆ ∆ = 4 x 8∆ ∆ = 32 ∆ or

32 gate delays

EECC341 - Shaaban #24 Final Review Winter 2001 2-20-2002

Carry Look-Ahead Adders

•

The disadvantage of the ripple carry adder is that the propagation delay of adder (2 n∆ ∆) increases as the size of the adder, n is increased due to the carry ripple through all the full adders.

•

Carry look-ahead adders use a different method to create the needed carry bits for each full adder with a lower constant delay equal to three gate delays.

•

The carry out C-out from the full adder at position i or C j+1 is given by:

C-out = C i+1 = Xi . Y i + (Xi + Yi) . Ci •

By defining: – G i = Xi . Y i as the carry generate function for position i (one gate delay) (If G i =1 C i+1 will be generated regardless of the value C i) – Pi = Xi + Yi as the carry propagate function for position i (If Pi = 1 C i will be propagated to C i+1)

•

By using the carry generate function G i and carry propagate function Pi , then C i+1 can be written as:

C-out = C i+1 = •

(one gate delay)

G i + Pi . C i

To eliminate carry ripple the term Ci is recursively expanded and by multiplying out, we obtain a 2-level AND-OR expression for each C i+1

EECC341 - Shaaban #25 Final Review Winter 2001 2-20-2002

Carry Look-Ahead Adders • For a 4-bit carry look-ahead adder the expanded expressions for all carry bits are given by: C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P 1.P0.C0 C3 = G2 + P2.G1 + P 2.P1.G0 + P 2.P1.P0.C0 C4 = G3 + P3.G2 + P 3.P2.G1 + P 3 . P2.P1.G0 + P 3.P2.P1.P0.C 0 where

G i = Xi . Yi

P i = Xi + Yi

• The additional circuits needed to realize the expressions are usually referred to as the carry look-ahead logic. • Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder. EECC341 - Shaaban #26 Final Review Winter 2001 2-20-2002

Carry Look-Ahead Circuit

Ci = Gi-1 + Pi-1. Gi-2 + …. + Pi-1.P i-2. …P1 . G0

+

P i-1.P i-2. …P0 . C0

EECC341 - Shaaban #27 Final Review Winter 2001 2-20-2002

Binary Arithmetic Operations Subtraction • Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed. • Subtraction Example:

X 229 Y - 46 183

-

0 0 1 0 1

1 1 0 0

1 1 1 1

1 0 0 1

1 0 1 0

1 1 1 1

0 0 1 1

0 Borrow 1 0 1

EECC341 - Shaaban #28 Final Review Winter 2001 2-20-2002

Full Subtractor •

Subtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit. This is called full subtraction.

Difference D XY

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

D 0 1 1 0 1 0 0 1

B-out 0 1 1 1 0 0 0 1

S(X,Y, C-in) = Σ (1,2,4,7) C-out(x, y, C-in) = Σ (1,2,3,7)

01

0

2

0 1

1

Outputs

B-in 0 1 0 1 0 1 0 1

00

B-in

Full Subtractor Truth Table Inputs

X

11 6

1

3

1

10

7

4

1

5

1

B-in

Y

S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in) S = X ⊕ Y ⊕ (C-in)

Borrow B-out

X

XY

00

B-in 0

01 2

0 1

1

1

3

1 1

11 6 7

10 4

1

5

B-in

Y

B-out = X’Y + X’(B-in) + Y(B-in)

EECC341 - Shaaban #29 Final Review Winter 2001 2-20-2002

Full Subtractor Circuit Using AND-OR X’ Y’

X X’

X

B-in X’ Y B-in’

Y Y’

Y

X

X’YB-in’

Difference D

X Y

B-in B-in’

B-in

X’Y’B-in

Y

B-in’ X Y B-in’

X’

XY’B-in’

XYB-in

X’Y

Y

B-out

Full Subtractor

B-in

X’

X’B-in

B-out

B-in Y

D

B-in

YB-in

EECC341 - Shaaban #30 Final Review Winter 2001 2-20-2002

n-bit Subtractors An n-bit subtracor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways: • By using n full subtractors and connecting them in series, creating a borrow ripple subtractor: – Each borrow out B-out from a full subtractor at position j is connected to the borrow in B-in of the full subtracor at the higher position j+1.

• By using an n-bit adder and n inverters: – Find two’s complement of Y by: • Inverting all the bits of Y using the n inverters. • Adding 1 by setting the carry in of the least significant position to 1 – The original subtraction (X - Y) now becomes an addition of X to two’s complement of Y using the n-bit adder. EECC341 - Shaaban #31 Final Review Winter 2001 2-20-2002

4-bit Borrow Ripple Subtractor Inputs X3X2X1X0

Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from B4 X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3

B-out

Y3Y2Y1Y0

4-bit B-in Subtractor

B0 =0

D3 D2 D1 D0

Difference Output D

Data inputs to be subtracted X3

B4

B-out Full

Y3

B-in

X2 B3

B-out Full

Y2

B-in

Subtractor

Subtractor

D3

D2

X1 B2

B-out Full

Y1

B-in

Subtractor

D1 Difference output D

X0 B1

B-out Full

Y0

B-in

B0 =0

Subtractor

D0

EECC341 - Shaaban #32 Final Review Winter 2001 2-20-2002

4-bit Subtractor Using 4-bit Adder Inputs to be subtracted Y3 X3 X2 X1

C4

C-out

Y2

Y1

Y0

X0

4-bit Adder S3

S2

S1

S0

D3

D2 D1

D0

C-in

C0 = 1

Difference Output

EECC341 - Shaaban #33 Final Review Winter 2001 2-20-2002

Binary Multiplication •

Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier. • Ex. (unsigned) X3 X2 X1 X0 11 1011 multiplicand (4 bits) x Y3 Y2 Y1 Y0 X 13 X 1101 multiplier (4 bits) __________________________ -------------------------X3.Y0 X2.Y0 X1.Y0 X0.Y0 33 101 1 X3.Y1 X2.Y1 X1.Y1 X0.Y1 11 0000 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 ______ 1011 143 1011 P7 P6 P5 P4 P3 P2 P1 P0 --------------------10001111 Product (8 bits)

_______________________________________________________________________________________________________________________________________________

• An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n-bit adders where is adder is shifted by one position. • For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits.

EECC341 - Shaaban #34 Final Review Winter 2001 2-20-2002

4x4 Array Multiplier

EECC341 - Shaaban #35 Final Review Winter 2001 2-20-2002

Combinational Comparators • Comparing two binary inputs A, B each n bits for equality (i.e A = B) is a common operation in computers. • A single output combinational circuit to accomplish this can be constructed using n 2-input XNOR gates for bit-wise comparison plus one n-input AND gate. The output = 1 if A = B • This can also be done by subtraction (A - B) and checking for a zero result using a single n-input NOR gate. • Example: 1-bit comparator: A, B 1-bit each. – The 1-bit comparison requires a single XNOR gate

Truth table:

Output

A 0 0 1 1

(A ⊕ B)’ 1 0 0 1

B 0 1 0 1

A B

(A ⊕ B)’ Output

1-bit comparator EECC341 - Shaaban #36 Final Review Winter 2001 2-20-2002

Example: 4-bit Comparator Compares A = A3 A2 A1 A0 with B = B3 B2 B1 B0 Output = 1 if A = B A3 B3

A2 B2

Comparator Output

A1 B1

A0 B0

EECC341 - Shaaban #37 Final Review Winter 2001 2-20-2002

Combinational Shift Circuits • An n-bit shift circuit (shifter) has a single n-bit data input A, and a single n-bit output R and a number of control inputs to determine the shift amount (0 to n-1). • Possible shift operations include: – Shift left or right: • Arithmetic right shift (the sign bit is shifted in), • logic shift (0 is shifted in) • Rotate left or right. • Example: Original data input A = 11011 • Shift left by one : 10110 • Logic shift right by one: 01101 • Arithmetic shift right by one: 11101 • Rotate left by one: 10111 • Combinational shift circuits are usually constructed using a number of levels of multiplexeres.

EECC341 - Shaaban #38 Final Review Winter 2001 2-20-2002

Example: Combinational 8-Bit Right Shifter Basic Building Block 2-to-1 Mux

A

B

1

0

S2 S1 S0 shift amount from 0 to 7

Mux select S

Three levels of Muxes used D A7 Connect to: 0 for logic right shift or to A7 for arithmetic right shift or to A0 - A6 for rotate right

{

A6

A5

A4

A3

A2

A1

S2 S1 S0

A0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R7

R6

R5

R4

R3

R2

R1

•

Propagation delay: 2 gate delays per level x 3 levels = 6 gate delays

•

How many Mux levels for 32-bit shifter? Propagation delay?

R0

EECC341 - Shaaban #39 Final Review Winter 2001 2-20-2002

Sequential Logic Circuits Combinational outputs

Memory outputs

Combinational logic

Memory elements

Inputs

Sequential circuit = Combinational logic + Memory Elements Current State of A sequential Circuit: Value stored in memory elements (value of state variables). State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

EECC341 - Shaaban #40 Final Review Winter 2001 2-20-2002

Sequential Circuit Buliding Blocks:

Generic Memory Elements •

A Memory Element: A logic device that can remember a single-bit value indefinitely, or change its value on command from its inputs. command

Memory element

Q

Memory Element Output: stored single-bit value

•

•

•

The output Q of the memory element represents the value stored in the memory element. This is also called the state variable of the memory elements. A memory element can be in one of two possible states: – Q = 0 (the memory element has 0 stored), also said be in state 0. – Q =1 (the memory element has 1 stored), also said to be in state 1. The commands to the memory element formed by its input(s) may include: – Set: Store 1 (Q=1) in the memory element. – Reset: Store 0 (Q=0) in the memory element. – Flip: Change stored value from 0 to 1 or from 1 to 0. – Hold value: Memory value does not change. Memory Element state transition: A change in the stored value from 0 to 1, or from 1 to 0 such as that caused by a flip command.

EECC341 - Shaaban #41 Final Review Winter 2001 2-20-2002

Sequential Circuit Memory Elements: Latches, Flip-Flops • Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. • Latches:

– The output of a latch depends on its current inputs and on its previous inputs and its change of state can happen at any time when its inputs change. •

Flip-Flops:

– The output of a flip-flop also depends on current and previous input but the change in output (change of state or state transition) occurs at specific times determined by a clock input. EECC341 - Shaaban #42 Final Review Winter 2001 2-20-2002

Sequential Circuit Memory Elements: Latches, Flip-Flops

• Latches: – S-R Latch – S-R Latch With Enable – D-Latch • Flip-Flops: – Edge-Triggered D Flip-Flop – Master/Slave S-R Flip-Flop – Master/Slave J-K Flip-Flop – Edge-Triggered J-K Flip-Flop – T Flip-Flop With Enable EECC341 - Shaaban #43 Final Review Winter 2001 2-20-2002

S-R Latch • An S-R (set-reset) latch can be built using two NORgates forming a feedback loop. • The output of the S-R latch depends on current as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change. R

Function Table

Q

QN

S

S 0 0 1 1

R 0 1 0 1

Q last Q 0 1 0

QN Last QN 1 0 0

Circuit

EECC341 - Shaaban #44 Final Review Winter 2001 2-20-2002

S-R Latch With Enable • Since the S-R latch is responsive to its inputs at all times an enable line C is used to disable or enable state transitions. • Behaves similar to a regular S-R latch when enable C=1 S

Circuit

Q Enable C

QN R

Function Table

S C

R

Q Q

S 0 0 1 1 x

R 0 1 0 1 x

C 1 1 1 1 0

Q last Q 0 1 0 last Q

QN last QN 1 0 0 last QN

Logic Symbol

EECC341 - Shaaban #45 Final Review Winter 2001 2-20-2002

D-Latch • Similar to S-R latch with an enable line, but both S, R are generated from one input D (data) and an inverter. • Stores the value of its input D when enable C =1. Function Table

D

C 1 1 0

D 0 1 x

Q 0 1 Last Q

QN 1 0 Last QN

Q C D

Q

C

Q

QN Logic Symbol Circuit

EECC341 - Shaaban #46 Final Review Winter 2001 2-20-2002

Edge-Triggered D Flip-Flop • Uses a pair of D latches and inverters. • Similar in behavior to a D latch except that output and state changes happen at the rising or falling edge of an input clock. • A D Flip-Flop triggered on the rising edge of the clock is given by: Master Latch D

D

Q

C

Q

Slave Latch QM

D

D

Q

Q

C

Q

QN

Q CLK Q

Logic Symbol

CLK

Function Table

Clock Circuit

D CLK Q 0 0 1 1 x 0 Last Q x x Last Q

QN 1 0 Last QN Last QN

EECC341 - Shaaban #47 Final Review Winter 2001 2-20-2002

Master/Slave S-R Flip-Flop • S-R latches are substituted for the D latches in the negative-edge triggered D flip flop Master Latch S

S C

R

R

CLK

Q Q

Slave Latch QM

Circuit

S C

R

Q

Q

Q

QN

Function Table

S C

R

Q Q

S x 0 0 1 1

R x 0 1 0 1

C 0

Q last Q last Q 0 1 undef.

QN last QN last QN 1 0 undef.

Logic Symbol

EECC341 - Shaaban #48 Final Review Winter 2001 2-20-2002

Master/Slave J-K Flip-Flop • Solves the problem when both S=R=1 • When J=K=1 the last state is inverted. Master Latch J

S C

K

R

Q Q

Slave Latch QM

S C

R

Circuit

Q

Q

Q

QN

CLK Function Table

S C

R

Q Q

Logic Symbol

J K x x 0 0 0 1 1 0 1 1

C 0

Q QN last Q last QN last Q last QN 0 1 1 0 last QN last Q

EECC341 - Shaaban #49 Final Review Winter 2001 2-20-2002

Edge Triggered J-K Flip-Flop • Created from an edge-triggered D flip-flop Circuit

J D

K

Q

Q

QN

CLK Q

CLK Function Table

J K x x x x 0 0 0 1 1 0 1 1

C 0 1

Q last Q last Q last Q 0 1 last QN

QN last QN last QN last QN 1 0 last Q

Logic Symbol

j k

Q CLK Q

EECC341 - Shaaban #50 Final Review Winter 2001 2-20-2002

T Flip-Flop With Enable • Changes state on every clock cycle (rising edge of T).

D

En

Q

CLK Q

T

Q

Circuit

QN

OR Function Table

EN T

j k

Q CLK Q

Q QN

T En x 0 1

Q QN last Q last QN last QN last Q

EECC341 - Shaaban #51 Final Review Winter 2001 2-20-2002

Clocked Synchronous State-Machines • Such machines have the characteristics: – Sequential circuits designed using flip-flops. – All flip-flops use a common clock (clocked synchronous). – A machine using n flip-flops (state memory) has n state variables (the outputs of the flip-flops) and 2n states. – In general, the next state and output of the machine both depend on the current state of the machine and on the current input: Next state = F(current state, input) output = G(current state, input) This type of state machine is called Mealy Machine – In some cases the next output depends only on the current state and not directly on the current input –

Next state = F(current state, input) output = G(current state) Such machines are called Moore machines.

EECC341 - Shaaban #52 Final Review Winter 2001 2-20-2002

Clocked Synchronous State-Machine Model (Mealy machine)

inputs

Next-state Logic

excitation

State Memory

current state

F

Output Logic

outputs

G clock

State memory: Usually edge-triggered D or JK flip-flops

clock

Moore Machine

EECC341 - Shaaban #53 Final Review Winter 2001 2-20-2002

Latch/Flip-Flop Characteristic Equations Device S-R latch D latch Edge-triggered D flip-flop Master/Slave S-R flip-flop Master/Slave J-K flip flop Edge Triggered J-K flip-flop T flip-flop T flip-flop with enable

Characteristic Equations Q* = S+R’.Q Q* = D Q* = D Q* = S+R’.Q Q* = J.Q’ + K’.Q Q* = J.Q’ + K’.Q Q* = Q’ Q* = EN.Q’ + EN’.Q

EECC341 - Shaaban #54 Final Review Winter 2001 2-20-2002

Clocked Synchronous State-machine Analysis Given the circuit diagram of a state machine: 1

Analyze the combinational logic to determine flip-flop input (excitation) equations: Di = Fi (Q, inputs) – The input to each flip-flop is based upon current state and circuit inputs.

2

Substitute excitation equations into flip-flop characteristic equations, giving transition equations: Qi* = Hi( Di )

3

From the circuit, find output equations: Z = G (Q, inputs) – The outputs are based upon the current state and possibly the inputs.

4

Construct a state transition/output table from the transition and output equations: – Similar to truth table. – Present state on the left side. – Outputs and next state for each input value on the right side. – Provide meaningful names for the states in state table, if possible.

5

Draw the state diagram which is the graphical representation of state table.

EECC341 - Shaaban #55 Final Review Winter 2001 2-20-2002

Basic Format:

State Diagram

State

Moore 0

Format: Arc = input X Node = state/output Q

Output

1

A 0

Input

B 1

Mealy

0, 1

1/1

0/0

A

B 0 / 1, 1 / 0

Format: Arc = input X / mealy output Y Node = state

EECC341 - Shaaban #56 Final Review Winter 2001 2-20-2002

State Machine Analysis Example Analyze the state machine: 1

Input (or excitation) equations: D0 = Q1’. X

x

D

Q

Q1

Q'

Q1'

D1 = Q1 . x + Q0 . x

2

Characteristic equations: Q0* = D0 Q1* = D1

D

CP

Q

Q0

Q'

Q0'

Find State equations: Q0* = Q1’. x Q1* = Q1 . x + Q0 . x

y

3

Output equation: y = (Q0 + Q1) . x'

This is a Mealy Machine since output = G(current state, input)

EECC341 - Shaaban #57 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 4 From the state equations and output equation, construct the state transition/output table:

Q0* = Q1’. x Q1* = Q1 . x + Q0 . x Output equation: y = (Q0 + Q1) . x'

Input

x

State equations:

Q1 Q0

0

1

0

0

00,0

01,0

0

1

00,1

11,0

1

0

00,1

10,0

1

1

00,1

10,0

Current State

Q1* Q0* , y

Next State when x =0 Output for current state when x =0

Next State when x =1

Output for current state when x =1

EECC341 - Shaaban #58 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 5

Draw the state diagram of the state machine.

state transition/output table

0/0

x Q1 Q0

state diagram

0/1

0

1

0

0

00,0

01,0

0

1

00,1

11,0

1

0

00,1

10,0

1

1

00,1

10,0

Q1* Q0* , y

00 1/0

0/1

01

1/0 10

0/1 1/0

1/0 11

Arc = input x / output y Node = state

EECC341 - Shaaban #59 Final Review Winter 2001 2-20-2002

Clocked State-machine Analysis: State Naming • State Naming:

– Optionally name the states and substitute state names S for state-variable combinations in transition/output table and in state diagram. – Example: For a circuit with two flip-flops: Q1 Q0 State Name 0 0 A 0 1 B 1 0 C 1 1 D EECC341 - Shaaban #60 Final Review Winter 2001 2-20-2002

Clocked State-machine Analysis Example: Transition/Output Table Using State Names For the last example naming The States: Transition/output Table:

Q1 Q0 0 0 0 1 1 0 1 1

State Name A B C D

Transition/output Table using state names:

x Q1 Q0

x

0

1

S

0

1

A

0

0

00,0

01,0

A

A,0

B,0

B

0

1

00,1

11,0

B

A,1

D,0

C

1

0

00,1

10,0

C

A,1

C,0

D

1

1

00,1

10,0

D

A,1

C,0

Q1* Q0* , y

S* , y

EECC341 - Shaaban #61 Final Review Winter 2001 2-20-2002

Clocked State-machine Analysis Example: State Diagram Using State Naming Q1 Q0 0 0 0 1 1 0 1 1

Naming The States:

State Diagram without state naming:

0/0 0/1 00 1/0

0/1

01

0/1 1/0

State Name A B C D

State Diagram with state naming:

1/0

0/0

10 1/0 11

0/1

A 1/0

0/1

B

0/1 1/0

1/0 C 1/0

D

Arc = input x / output y Node = state

EECC341 - Shaaban #62 Final Review Winter 2001 2-20-2002

Clocked State-machine Analysis:

State Machine Timing Diagram •

• •

•

The timing diagram for a state machine graphically shows the state machine response in terms of state variables and output signals vs. time for given time-varying input signals and a given initial state. State machine timing diagrams can be generated using transition/output tables or state diagrams. Timing diagrams can be used to account for both combinational and flip-flop propagation delays. Example: For the state machine in the previous example show the timing diagram for the following input, assuming an initial state A and ignoring propagation delays: Cycle: 0

1

2

3

4

5

6

7

1

Clock 0 Time 1

Input X 0

EECC341 - Shaaban #63 Final Review Winter 2001 2-20-2002

State Machine Timing Diagram Example Cycle: 0

1

2

3

4

5

6

7

1

Clock 0 Time 1

Input X 0 1

Q1 0 1

Q0

A

B

D

C

A

A

B

A

0

Output Y

EECC341 - Shaaban #64 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 2 Analyze the state machine: X D0

Y Q2’

D

Q

Z1

Q0

CLK Q

D1 Q0

D

Q

Q1

CLK Q

D2 Q1

D

Q

CLK Q

Q2

Z2

Q2’

CLK

Input Logic F

State Memory

Output Logic G

EECC341 - Shaaban #65 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 2 Excitation Equations D0 = X . Y’.Q2 D1 = X . Q0 D2 = Y’ + Q1

1

2

Characteristic Equations Q0* = D0 Q1* = D1 Q2* = D2

State or Transition Equations Q0* = D0 = X . Y’ . Q2’ Q1* = D1 = X . Q0 Q2* = D2 = Y’ + Q1

3

Output Equations Z1 = X . Q0 + Q1’ Z2= (Q1 . Q2)’

EECC341 - Shaaban #66 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 2 4 From the state equations and output equation, construct the state transition/output table: state name A B C D E F G H

XY Q2 0 0 0 0 1 1 1 1

Q1 Q0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

00 01 100, 11 000, 11 100, 11 000, 11 100, 01 100, 01 100, 01 100, 01 100, 11 000, 11 100, 11 000, 11 100, 00 100, 00 100, 00 100, 00

11 000, 11 010, 11 100, 01 110, 11 000, 11 010, 11 100, 00 110, 10

10 101, 11 111, 11 101, 01 111, 11 100, 11 110, 11 100, 00 110,10

Q2* Q1* Q0*, Z1 Z2 (Next State, Outputs) Transition Equations Q0* = D0 = X . Y’ . Q2’ Q1* = D1 = X . Q0 Q2* = D2 = Y’ + Q1

Output Equations Z1 = X . Q0 + Q1’ Z2= (Q1 . Q2)’

EECC341 - Shaaban #67 Final Review Winter 2001 2-20-2002

State-machine Analysis Example 2: Transition/Output Table Using State Names XY S A B C D E F G H

00 E, 11 E, 11 E, 01 E, 01 E, 11 E, 11 E, 00 E, 00

01 11 A, 11 A, 11 A, 11 C, 11 E, 01 E, 01 E, 01 G, 11 A, 11 A, 11 A, 11 C, 11 E, 00 E, 00 E, 00 G, 10 S*, Z1 Z2

10 F, 11 H, 11 F, 01 H, 11 E, 11 G, 11 E, 00 G,10

EECC341 - Shaaban #68 Final Review Winter 2001 2-20-2002

State-machine Analysis Example 2: State Diagram (incomplete) Y (11)

(11) X’ Y

B

X’ Y’ (11)

X Y’ (11)

A XY’ (11)

X Y (11)

X’Y’ (11)

C X’+Y (01)

XY’ (01)

H XY (11)

G

XY’ (11)

D X’ (01)

E

F Arc: input expression (outputs) = expression (Z1 /Z2)

EECC341 - Shaaban #69 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 3 Analyze the state machine: X J1 Y

J

Q

K

Q

Q1

Z

K1 J2 K2

Q2 J

Q

K

Q

CLK

EECC341 - Shaaban #70 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 3 Excitation Equations J1 = X K1 = X·Y J2 = X’ K2 = 0

1 2

Characteristic Equations Q*= J·Q’ + K’·Q Q1*= J1·Q1’ + K1’·Q1 Q2* = J2·Q2’ + K2’·Q2

Transition Equations Q1* = X·Q1’ + (X·Y)’ ·Q1 = X·Q1’ + X’·Q1 + Y’·Q1 Q2* = X’·Q2’ + 0’·Q2 = X’·Q2’ + Q2

3 Output Equation

Z = X·Q1 + Q2

EECC341 - Shaaban #71 Final Review Winter 2001 2-20-2002

State Machine Analysis Example 3 4 From the state equations and output equation, construct the state transition/output table: XY S

Q1 Q2

00

01

11

10

A

0

0

01,0

01,0

10,0

10,0

B

0

1

01,1

01,1

11,1

11,1

C

1

0

11,0

11,0

00,1

10,1

D

1

1

11,1

11,1

01,1

11,1

Q1* Q2*, Z Transition Equations Q1* = X·Q1’ + X’·Q1 + Y’·Q1 Q2* = X’·Q2’ + Q2

Output Equation

Z = X·Q1 + Q2

EECC341 - Shaaban #72 Final Review Winter 2001 2-20-2002

State-machine Analysis Example 3: Transition/Output Table Using State Names XY S

00

01

11

10

A

B,0

B,0

C,0

C,0

B

B,1

B,1

D,1

D,1

C

D,0

D,0

A,1

C,1

D

D,1

D,1 S*, Z

B,1

D,1

EECC341 - Shaaban #73 Final Review Winter 2001 2-20-2002

State-machine Analysis Example 3: State Diagram Arc Format: inputs xy output z

00,01 0 A 10,11 1

11 1 00,01,10 1

B

D

00,01 0

11 1

00,01 1

10,11 0 C

10 1

EECC341 - Shaaban #74 Final Review Winter 2001 2-20-2002

State Machine Design Procedure 1. Build state/output table (or state diagram) from word description using state names. 2. Minimize number of states (optional). 3. State Assignment: Choose state variables and assign bit combinations to named states. 4. Build transition/output table from state/output table (or state diagram) by substituting state variable combinations instead of state names. 5. Choose flip-flop type (D, J-K, etc.) 6. Build excitation table for flip-flop inputs from transition table. 7. Derive excitation equations from excitation table. 8. Derive output equations from transition/output table. 9. Draw logic diagram with excitation logic, output logic, and state memory elements. EECC341 - Shaaban #75 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector • Word description (110 input sequence detector): – Design a state machine with input A and output Y. – Y should be 1 whenever the sequence 1 1 0 has been detected on A on the last 3 consecutive rising clock edges (or ticks). – Otherwise, Y = 0 – Note: this is a Moore machine, that is the output, Y, depends only on inputs at previous clocks rising edges , not on the current input.

• Timing diagram interpretation of word description (only rising clock edges are shown): A

0

1

1

0

0

1

1

1

0

1

1

1

CLK Y

EECC341 - Shaaban #76 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Step1: Choosing States • Possible states (What does the state machine need to remember?): – – – – –

Initial No1s First1 Two1s ALL

: : : : :

power up, no clocks yet first 1 not found first 1 found at least 2 consecutive 1s found found 1 1 0

Y=0 Y=0 Y=0 Y=0 Y=1

• Are all the states needed? – Notice: Initial is equivalent to NO1s – We can drop the state Initial and replace it with state No1s

EECC341 - Shaaban #77 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Step 1: State/Output Table and Diagram Reset 0

State Table

1 NO1s

A S

0

1

Y

No1s

No1s

First1

0

First1

No1s

Two1s

0

Two1s

ALL

Two1s

0

ALL

No1s

First1

1

S*

State Diagram

0

First1 0

0

1 0

1

ALL

Two1s

1

0

1

0

Format: Arc: input A Node: state/output Y

EECC341 - Shaaban #78 Final Review Winter 2001 2-20-2002

Step3: State Assignment Considerations • Why does the choice of state assignment matter? – Has a big effect on the complexity of excitation and output equations and thus on the amount of combinational logic needed. • How to find the best state assignment? – The only known way is to try all assignments and determine the resulting equations. • N = 2: (22)! = 4! = 24 assignments for 2 state bits • N = 3: (23)! = 8! = 40,320 assignments for three state bits. • N = 4: (24)! = 16! = 20,922,789,888,000 assignments for 4 state bits!!! THIS IS NOT PRACTICAL APPROACH! ∴ Use heuristic guidelines for pretty good assignments. This is still an active area of research! • There is no effective way to guarantee a “best” assignment. The heuristic methods sometimes perform poorly!

EECC341 - Shaaban #79 Final Review Winter 2001 2-20-2002

State Assignment Strategies • Simplest Assignment: – Straight binary, not best; purely arbitrary assignment. • One Hot Assignment: – Redundant encoding, each flip-flop is assigned a state. – Uses the same number of bits as there are states (not useful in large designs). – Simple to assign; simple next state logic (no state decoding required) – Output logic is simple! One OR gate per Moore output! • Almost One Hot Assignment: – Almost same as One Hot, but one less state bit. – Use all 0’s to represent a state (usually INIT). – Must now decode state 0 if it is needed. • Decomposed Assignment: – Use the “structure” of the state table to simplify next-state and output logic. – An “art” which requires much practice.

EECC341 - Shaaban

#80 Final Review Winter 2001 2-20-2002

Example: State Assignment Strategies Alternative Assignments AB Q1..Q4 Q1..Q5 Q1Q2Q3 Q1Q2Q3 S 00 01 11 10 Z 0000 00001 000 000 INIT A0 A0 A1 A1 0 0001 00010 100 001 A0 OK0 OK0 A1 A1 0 0010 00100 101 010 A1 A0 A0 OK1 OK1 0 0100 01000 110 011 OK0 OK0 OK0 OK1 A1 1 1000 10000 111 100 OK1 A0 OK0 OK1 OK1 1 Almost One Hot

One Hot

Decomposed Simplest

– Example decomposition: • • • •

Initial State = all 0’s for easy RESET INIT state is different, so use Q 1 = 1 for non-INIT states; thus D1=1 Z = 1 in only 2 states, so use Q 2 =1 for states when Z = 1; thus Z = Q2 Use Q3 = 1 for state transitions caused by A having the value of 1 (all destination states cause by A = 1, i.e. states A1 and OK1); thus D3=A

THUS, simpler next state and output logic!

EECC341 - Shaaban #81 Final Review Winter 2001 2-20-2002

State Assignment Heuristic Guidelines Starting from the highest priority to the lowest: • Choose initial coded state that’s easy to produce at reset: (all 0’s or 1’s) – This simplifies the initialization circuitry. • Freely use any of the 2n state codes for best assignment (i.e.. with s states, don’t just use the first s integers 0,1,…,s-1) • Define specific bits or fields that have meaning with respect to input or output variables (decomposed codes). • Consider using more than minimum number of state variables to allow for decomposed codes. • Minimize number of state variables that change at each transition • Simplify output logic.

EECC341 - Shaaban #82 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Step 3: State Assignment • Choose state variable assignments: – Initial state all 0s – Q2 = last A, so Q2* = A – minimize number of transitions A Q1 Q2

S

0

1

Y

0

0

No1s

No1s

First1

0

0

1

First1

No1s

Two1s

0

1

1

Two1s

ALL

Two1s

0

1

0

ALL

No1s

First1

1

S*

EECC341 - Shaaban #83 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Step 4: Transition/Output Table • Step 4: Build transition/output table from state/output table by substituting state variable combinations instead of state names. A Q1 Q2

0

1

Y

0

0

00

01

0

0

1

00

11

0

1

1

10

11

0

1

0

00

01

1

Q1* Q2* =D1 D2

Step 6

• Step 5: Choose D Flip-Flops , so Q*= D • Step 6: Excitation table: – Same as Transition/output table with Q1*=D1, Q2*=D2

EECC341 - Shaaban #84 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Steps 7, 8 : Excitation/Output Equations • Step 7: Excitation equations: D1, D2 = F (A, Q1, Q2) Q1•Q2

Q1 Q2 A

D1 :

00

01

11

10

0

0

0

1

0

1

0

1

1

0

Q1 Q2 A

D2 :

00

01

11

10

0

0

0

0

0

1

1

1

1

1

Q2•A

D1 = Q1•Q2 + Q2•A

D2 = A (as planned!)

• Step 8: Output equation: Y = G (Q1, Q2) Y = Q1•Q2’ (directly read from transition table) EECC341 - Shaaban #85 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Step 9: Logic Diagram 1

D1

D CLK

A

>

D2

D CLK

>

P

Q

C

Q

P

C Q

CLK RESET_L

Q

Q1

Y

1 Q2

P = Preset C = Clear Both active low

RESET_L reset to initial state (active low)

EECC341 - Shaaban #86 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector • Word description (110/101 input sequence detector): – Design a state machine with input A and output Y. – Y = 1 when either sequence 1 1 0 or 1 0 1 has been detected on input A on the last 3 consecutive rising clock edges (or ticks). – Otherwise Y = 0 – Note: Correct sequences may overlap and still be accepted.

• Timing diagram interpretation of word description (only rising clock edges are shown): A

0

1

0

1

0

1

1

0

1

0

0

0

CLK y

EECC341 - Shaaban #87 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector

Step1: Choosing States • Possible states (What does the state machine need to remember?): – – – – – – A

Idle Got1 Got10 Got101 Got11 Got110 0

Initial state, no starting 1 yet A = 1 on last tick Sequence A = 10 on last two ticks Sequence A = 101 on last three ticks Sequence A = 11 on last two ticks Sequence A = 110 on last three ticks

1

Idle

0

1

Got10

Idle

CLK y

: : : : : :

Got1

0

1

Got10 Got101

1

0

Got11 Got101

1

Y=0 Y=0 Y=0 Y=1 Y=0 Y=1 0

0

Got101 Got110

0

IDLE

Got10

EECC341 - Shaaban #88 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector

Step 1: State/Output Table A S

0

1

Y

IDLE

IDLE

Got1

0

Got1

Got10

Got11

0

Got10

IDLE

Got101

0

Got101

Got10

Got11

1

Got11

Got110

Got11

0

Got110

IDLE

Got101

1

S*

EECC341 - Shaaban #89 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector

Step 1: State Diagram Reset 0

1 IDLE

Got1

0

0 0

0

0

Got110

Got10

1

1

0

1

0

0

1

1 Got11

Got101

0

1

Format: Arc: input A Node: state/output Y

1

EECC341 - Shaaban #90 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector

Steps 3: State Assignment • Step 3: Choose state variable assignments : – – – –

Initial state all 0s Q1 = Y Q3 = last A, so Q3* = A minimum number Q1 Q2 Q3 of transitions 0 0 0

From Step 1: A S

0

1

Y

IDLE

IDLE

Got1

0

0

0

1

Got1

Got10

Got11

0

0

1

0

Got10

IDLE

Got101

0

1

1

1

Got101

Got10

Got11

1

0

1

1

Got11

Got110

Got11

0

1

1

0

Got110

IDLE

Got101

1

S*

EECC341 - Shaaban #91 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector • Step 4: Transition/output table • Step 5: Choose D Flip-flops Q1 Q2 Q3 • Step 6: Excitation table 0 0 0 – Same as Transition table 0 0 1

Unused states?

A 0

1

Y

000

001

0

010

011

0

0

1

0

000

111

0

1

1

1

010

011

1

0

1

1

110

011

0

1

1

0

000

111

1

1

0

0

ddd

ddd

d

1

0

1

ddd

ddd Q1*Q2* Q3* =D1 D2 D3

d

EECC341 - Shaaban #92 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector

Steps 7: Excitation Equations Q1 Q2

• Step 7: Excitation equations – D1, D2, D3 = F (A, Q1, Q2, Q3) D1 = Q1’•Q2•Q3•A’ + Q2•Q3’•A

Q3 A

00

D3 = A (as planned!)

10

Q1 Q2

10

d 1

01 11

D2 :

11

00

D1 :

D2 = Q2•A + Q3

Q3 A

01

1

d d

1

d

Q1 Q2

00

01

11

10

d

00 01

1

1

d

Q3 A

D3 :

00

01

11

10

d

00 01

1

1

1

d

1

1

1

d

11

1

1

1

d

11

10

1

1

1

d

10

d

EECC341 - Shaaban #93 Final Review Winter 2001 2-20-2002

State Machine Design Example 2: 110/101 Detector

Step 8: Output Equations • Step 8: Output equation

– Y = Q1 (as planned!)

• Step 9: Logic diagram – (3) D-Flip-flops + (3) 2-input gates + (1) 3-input AND gate + (1) 4-input AND gate

– Draw the diagram.

D1 = Q1’•Q2•Q3•A’ + Q2•Q3’•A D2 = Q2•A + Q3 D3 = A

EECC341 - Shaaban #94 Final Review Winter 2001 2-20-2002

State Machine Design Using J-K Flip-Flops • State machine design step 6 (building excitation table for flip-flop inputs from transition table): – When using D flip-flops, since the next state Q* = D, the excitation table is the same as the transition table with Q* replaced with D. – In the case of J-K flip-flops, the next state is given by: Q* = J . Q’ + K’. Q – In this case we cannot rearrange the characteristic equation to find separate equations for J, K. – Instead an application (or excitation) table for J-K flip-flops is used to obtain the corresponding values of J, K for a given Q to Q* transition:

Q

Q*

J

K

0 0 1 1

0 1 0 1

0 1 d d

d d 1 0

J-K Flip-Flop Excitation Table

EECC341 - Shaaban #95 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector (Repeated Using J-K Flip-Flops)

• Word description (110 input sequence detector): – Design a state machine with input A and output Y. – Y should be 1 whenever the sequence 1 1 0 has been detected on A on the last 3 consecutive rising clock edges (or ticks). – Otherwise, Y = 0

• Timing diagram interpretation of word description (only rising clock edges are shown): A

0

1

1

0

0

1

1

1

0

1

1

1

CLK Y

EECC341 - Shaaban #96 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector

Step 1: State/Output Table and Diagram Reset 0

State Table

1 NO1s

A S

0

1

Y

No1s

No1s

First1

0

First1

No1s

Two1s

0

Two1s

ALL

Two1s

0

ALL

No1s

First1

1

S*

State Diagram

0

First1 0

0

1 0

1

ALL

Two1s

1

0

1

0

Format: Arc: input A Node: state/output Y

EECC341 - Shaaban #97 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector Using J-K Flip-flops •

Steps 1-4: No change.

Transition Table (step 4):

A Q1 Q2

0

1

Y

0

0

00

01

0

0

1

00

11

0

1

1

10

11

0

Q1 Q2

1

0

00

01

1

0

Q1* Q2* • •

Step 5: Choose J-K Flip-Flops Step 6: Excitation table: Use J-K Flip-Flop Excitation Table.

Q

Q*

J

K

0 0 1 1

0 1 0 1

0 1 d d

d d 1 0

J-K Flip-Flop Excitation Table

Excitation table (Step 6):

A

0

1

Y

0

0d, 0d

0d, 1d

0

0

1

0d, d1

1d, d0

0

1

1

d0, d1

d0, d0

0

1

0

d1, 0d

d1, 1d

1

J1 K1, J2 K2

EECC341 - Shaaban #98 Final Review Winter 2001 2-20-2002

State Machine Design Example 1: 110 Detector Using J-K FF Steps 7, 8 : Excitation/Output Equations • Step 7: Excitation equations: J1, K1, J2, K2 = F (A, Q1, Q2) Q1 Q2 A 0

J1 :

1

Q1 Q2

00

01

11

10

0

0

d

d

0

1

d

d

A

10

0

0

d

d

0

1

1

d

d

1

00

01

11

10

0

d

1

1

d

1

d

0

0

d

Q1 Q2

00

01

11

10

0

d

d

0

1

1

d

d

0

1

A

K2 :

K1 = Q2’ •

11

J2 = A

Q1 Q2

K1 :

01

J2 :

J1 = Q2•A A

00

K2 = A’

Step 8: Output equation: Y = G (Q1, Q2) Y = Q1•Q2’ (directly read from transition table)

EECC341 - Shaaban #99 Final Review Winter 2001 2-20-2002

Registers & Counters • Registers. • Shift Registers: – – – – –

Serial in, serial out shift register Serial in, parallel out shift register Parallel in, serial out shift register Parallel in, parallel out shift register Shift Register Applications

• Counters: – Ripple Counters – Synchronous Counters – Counter Applications EECC341 - Shaaban #100 Final Review Winter 2001 2-20-2002

Registers • An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits. 74LS175 1D

Q

D CLR

2D

Q

D CLR

3D

CLK

Q

Q

D CLR

4D

Q

Q

Q

D CLR

Q

1Q /1Q 2Q /2Q

Example: 74LS175 4-bit register 74LS175 CLK CLR

3Q

1D

/3Q

2D

4Q /4Q

3D 4D

1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q

/CLR

EECC341 - Shaaban #101 Final Review Winter 2001 2-20-2002

Shift Registers • Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) – Shift Left is towards MSB Q3 Q2 Q1 Q0 0

1

1

Q3 Q2 Q1 Q0

1

LSI

1

1

1

LSI

– Shift Right (or Shift Up) is towards MSB Q3 Q2 Q1 Q0 RSI

0

1

1

1

Q3 Q2 Q1 Q0 RSI

0

1

1

EECC341 - Shaaban #102 Final Review Winter 2001 2-20-2002

Serial In, Serial Out Shift Register SERIN CLOCK

D

Q

SRG n > SI

CLK

D

For a n-bit SRG: Serial Out = Serial In delayed by n clock period

Q

CLK

• • •

D

SO

4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 serout: - - - - 1 0 1 1 0 0 clock: Q

SEROUT

CLK

EECC341 - Shaaban #103 Final Review Winter 2001 2-20-2002

Serial In, Parallel Out Shift register SRG n SERIN CLOCK

D

Q

1Q

Q

2Q

CLK

D CLK

CLK

1Q 2Q • • • nQ

(SO)

Serial to Parallel Converter

• • •

D

> SI

Q

nQ

4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 101100111 2Q: - - 10110011 3Q: - - - 1011001 4Q: - - - - 101100 clock:

EECC341 - Shaaban #104 Final Review Winter 2001 2-20-2002

Parallel In, Serial Out Shift Register CLOCK LOAD/SHIFT

SERIN 1D

1Q

S

D

L

CLK

2Q

S 2D

Load/Shift=1 Di Qi Load/Shift=0 Qi Qi+1

ND

D

L

Parallel to Serial Converter

L

Q

CLK

• • • S

Q

• • • NQ D

Q

SEROUT

CLK

EECC341 - Shaaban #105 Final Review Winter 2001 2-20-2002

Parallel In, Parallel Out Shift Register CLOCK LOAD/SHIFT

SERIN 1D

S

D

L

L

Q

2Q

Q

NQ

CLK

• • • S

ND

D

L

General Purpose: Makes any kind of (left) shift register

1Q

CLK

S 2D

Q

• • • D CLK

EECC341 - Shaaban #106 Final Review Winter 2001 2-20-2002

Shift Register Applications Example:

8-Bit Serial Adder CTL CLK

x7

x6

x5

7

6

5

y7

y6

y5

7

6

5

x0 ...

Sequential Implementation of: Z[7..0] = X[7..0] + Y[7..0]

0

> y0 ...

0

> D

Q

Cin

A FA Cout

CLK CLR

B S

7

6

5

z7

z6

z5

...

0

>

CLEAR_C V

...

z0

EECC341 - Shaaban #107 Final Review Winter 2001 2-20-2002

Counters • Clocked sequential circuit with single-cycle state diagram – Modulo-m counter = divide-by-m counter S1

Sm

S2

S3

– Most Common:

n-bit binary counter, where m = 2n Ù n flip-flops, counts 0 … 2n-1 EECC341 - Shaaban #108 Final Review Winter 2001 2-20-2002

4-bit Ripple Counter Q CLK

Q0

1 bit divide-by-2

T Q Q

Q1

T

2 bit divide-by-4 Uses Minimal Logic

Q Q

Q2

T

3 bit divide-by-8

Q Q T

Q3

4 bit divide-by-16

Q

EECC341 - Shaaban #109 Final Review Winter 2001 2-20-2002

Ripple Counter Problem n • TCQ for MSB change for n-bit ripple counter => minimum clk period

CLK

1∆

Q0

2∆

Q1

3∆

Q2 7

Should be 0

1

2

EECC341 - Shaaban #110 Final Review Winter 2001 2-20-2002

Synchronous Counters • All clock inputs connected to common CLK signal – All flip-flop outputs change simultaneously tCQ after CLK – Faster than ripple counters – More complex logic – Most frequently used type of counter

EECC341 - Shaaban #111 Final Review Winter 2001 2-20-2002

Synchronous Serial Counter CNTEN

• Flip-flops enabled when all lower flip-flops = 1. • Enable propagates serially — limits speed • Requires (n-1) ∆ t < TCLK • All outputs change simultaneously tCQ after CLK

EN

CLK

Q

Q0

Q

Q1

Q

Q2

Q

Q3

>T ∆t

EN >T

∆t

EN >T

∆t

EN >T

EECC341 - Shaaban #112 Final Review Winter 2001 2-20-2002

Synchronous Parallel Counter

• • • •

CNTEN

EN

CLK

>T

Single-level enable logic per flip-flop Fastest and most complex type of counter Requires ∆ t < TCLK All outputs change simultaneously tCQ after CLK

EN

Q

Q0

Q

Q1

Q

Q2

Q

Q3

>T EN >T EN >T

EECC341 - Shaaban #113 Final Review Winter 2001 2-20-2002