ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2, April 2012.

Explore the Performance Of The ARM Processor Using Protocol Trainer Jadhav S.K., Gaikwad A.B., Mukti Awad  Abstract: Recently ,the evolution of embedded systems has shown a strong trend towards application specific, single chip solutions. The ARM processor core is a leading RISC processor architecture in the embedded domain .The ARM family of processor supports a unique feature of code size reduction.IN this paper it is illustrated using an embedded platform trying to design Protocol trainer using ARM7TDMI processor. Here the kill sotware is used for ARM programming and at base station VB is used. In this we will be incorporating various day today protocols used in the embedded industry, which will be helpful in a better understanding of the subject. Successfully putting a new application of Protocol trainer on ARM7 process.

I. INTRODUCTION

Fig.1 Generalized Block Diagram

Real-time Embedded system are a challenge to implement. An embedded environment constrain the energy consumption,the mem-ory space,and the execution time of an appl-ication. On the other hand, the complexity of the application running on an embedded pla-tform keeps increasing. Examples include next generation cell phones, portable game boys & digital assistants, smartcards and medical monitoring devices. Looking forward to new era of mod-ern education and fastest way totransfer data though different protocol by using trainer kit in the world of digital communication. The idea of combining all protocol in single kite for the understanding of working of the pro-tocols.At present the digital communica-tion uses various type of protocol like I2C, RS2-32, SPI &RS485 etc. Each protocol has its own merits & demerits that communication engineer can prefer any protocol according to the application needs engineer must know each & every protocol thoroughly. To under-stand all these protocol he must use the tra-iner kit that include all the protocol with their application.In present world to learn each protocol engineer need to buy each protocol kit that is very costly & it is very time consuming to understand various pro-tocol individually. To learn all these pro-tocol using single kit. we have deve-loping a protocol trainer kit using ARM.

The world is definitely in need of new approaches.To achieve this we need to evaluate the perforrmance of ARM processor by using protocol trainer .This is an embedded approach for the understanding of different protocol which can be useful for engineering student to understand all protocol thoroughly, and it c-an be suitable for the application of data acquisition system(DAS).It can be further modified as super visery control & data acquisition (SCADA).Fig. 1 shows generalized block diagram of ARM based protocol trainer. As any signal coming from a sensor is further processed through serial communication by using ARM processor. To learn I2C & SPI protocol , EEPROM & ADC is inter-face with the ARM respectively. similarly to interface PC with RS232 & RS485 to trans-mit serial data to PC, programming at base station using VB. II. ARM PROCESSOR An Embedded Processor is simply a micro Processor that has been “Embedded” into a device. It is software programmable but int-eracts with different pieces of Hardware.The three most important design criteria for emb-edded processors are performance, power & cost.Performance is a function of the parall-elism, instruction encoding efficiency & cy-cle time. Power is approx-imately a function of the voltage, area and switching frequency also a function of execution time. cost is a function of both area and the complexity of use (in term of Engineering cost).ARM see-ms to be leading the way in this field of pro-cessing. The processor has found this as one of its greatest markets, mainly because of the steps the company has taken to fit into the embedded market and the architecture it has adopted .

Jadhav S.K., MTech (Embedded & VLSI), Acropolis Institute of Techology Indore, [email protected] Mukti Avhad, MTech (Embedded & VLSI), Acropolis Institute of Techology Indore Gaikwad A.B. (M.E Communication), SSGB COE & TECH. Bhusaval. [email protected].

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2, April 2012. Other Embedded applications that take advantage of such processor are: disc drive controllers, automotive engine control and management systems .TV top box and internet appliances .Other products are still being modified to take advantage of it: toys watches etc. The possible application areandless.ARM can offer low cost, high performance and low power consumption, each of which is required to make a portable embedded item marketable in today’s world. Not to mention the fact that a whole subgroup of ARM architecture has been dedicate-d to function strictly to signal processors.

DB-25 DB-9

Fra

1 3 2 Transmit Data

A. Featurs Arm Processor a) On chip integrated oscillator operates with external crystal in range of 1MHz to 30MHz with external oscillator from 1MHz to 50MHz. b) Power saving modes include idle and power down. c) Individual enable/disable of peripheral function as well as peripheral clock scaling down additional power optimization. d) Two 32 bit timers/ external event counter (with four captures and four compare channels each), PWM units (six outputs) and watchdog. e) Low power real time clock with independent power and dedicated 32khz clock input. f) Multiple serial interfaces including two UART (16c550), two fast i2c (400 kbit/s) ,SPI and SSP with buffering and variables data length capabilities. g) Voctored interrupt controller with configurable priorities and vector addresses. h) Up to 47 of 5v tolerant general purpose i/o pins in tiny LQFP64 package. i) Processor wake up from power down mode via external interrupt or real time clock. j) Single power supply chip with power on reset (POR) and brown out detection (BOD) citcuits :- CPU operating voltage range of 0.3v to 3.6v(3.3V+-10%) with 5 V tolerate I/O pads.

2 3

Receive Data

5 7 Compute

7 4 8 5 1 8

6 6

Request to Send Clear to Send Carrier Detect Data Set Ready

9 22 Ring Indicator 4 20

Data Terminal

Fig. 2 Interface of RS-232 wih Personal Computer

III. PROTOCOLS A. RS-232 Interface The RS-232 interface is the Electronic Industries Association (EIA) standard for the interchange of serial binary data between two devices. It was initially developed by the EIA to standardize the connection of computers with telephone line modems. The standard allows as many as 20 signals to be defined, but gives complete freedom to the user. Three wires are sufficient: send data, receive data, and signal ground. The remaining lines can be hardwired on or off permanently. The signal transmission is bipolar, requiring two voltages, from 5 to 25 volts, of opposite polarity.

The industry custom is to use an asynchronous word consisting of: a start bit, seven or eight data bits, an optional parity bit and one or two stop bits. The baud rate at which the word sent is device-dependent. The baud rate is usually 150 times an integer power of 2, ranging from 0 to 7 (150, 300, 600 ,...., 19,200 ). Below 150 baud, many system-unique rates are used. The standard RS-232-C connector has 25 pins, 21 pins which are used in the complete standard. Many of the modem signals are not needed when a computer terminal is connected directly to a computer, and Figure 1 illustrates how some of the "spare"pins should be linked if not needed. Fig. 3 also illustrates the pin numbering used in the original DB-25 connector and that now commonly used with a DB-9 connector normally used in modern computers Specifying compliance to RS-232 only establishes that the signal levels in two devices will be compatible and that if both devices use the suggested connector, they may be able to

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2, April 2012. be connected. Compliance to RS-232 does not imply that the devices will be able to communicate or even acknowledge each other's presence.

(Common return) 8 Received Line Signal Detector 9 (Reserved for Data Set Testing)

Receive Data 17 Receiver Signal element Timing 18 Unassigned

--

--

+5V to +15V

RS-422 system software differs little from the familiar point-to-point RS- 232 communication systems. RS-422 is often used to simply extend the distance between nodes over the capabilities of RS-232. RS-422 can also be used as the master node in a four-wire master-slave network. When selecting or writing software for RS-422 systems the designer should be aware of the signals being used by the hardware in the system. Many RS-422 systems do not implement the hardware handshake lines often found in RS-232 systems due to the cost of running additional conductors over long distances.

Space

+3 Receiver input -3V Threshold

0V

Driver Output -5V to -15V

Mark

(a) Selecting RS-485 Cabling Cable selection for RS-422 and RS-485 systems is often neglected. Attention to a few details in the selection process can prevent the costly prospect of re-pulling thousands of feet of cable. (b) Number of Conductors The signal ground conductor is often overlooked when ordering cable. An extra twisted pair must be specified to have enough conductors to run a signal ground. A two-wire system then requires two twisted pair, and a four-wire system requires three twisted pair.

Fig. 3 RS 232 logic level specification

B. RS485 When a network needs to transfer small blocks of information over long distances, RS-485 is often the interface of choice. The network nodes can be PCs, microcontrollers, or any devices capable of asynchronous serial communications. Compared to Ethernet and other network interfaces, RS-485’s hardware and protocol requirements are simpler and cheaper. The RS-485 standard is flexible enough to provide a choice of drivers, receivers, and other components depending on the cable length, data rate, number of nodes, and the need to conserve power. Several vendors offer RS-485 transceivers with various combinations of features. Also, there are options for methods of terminating and biasing the line and controlling the driver enable inputs.

(c) Shielding It is often hard to quantify if shielded cable is required in an application or not. Since the added cost of shielded cable is usually minimal it is worth installing the first time. (d) Version Of RS 485 RS 485 exists in two versions i) single twisted pair ii) double twisted pair i)

Single Twisted Pair In this version all devices are connected to a single twisted pair so all the signals of rs485 must have drives with tristate o/p(including the master).the communication procedure over the single line in both direction

Table I RS232 Interface Signal Pin Description Pin Description Pin Description 1 Protective 10 (Reserved for 19 Secondary Ground Data Set Testing) Request to Send 2 Transmitted 11 Unassigned 20 Data Terminal Data Ready 3 Received Data 12 Sec. Rec. Line 21 Signal Quality Sig. Detector Ready 4 Request to Send 13 Sec. Clear To 22Ring Indicator Send 5 Clear to Ready 14 Secondary 23Data Signal Rate Transmit data Selector 6 Data Set ready 15 Transmission 24Transmit Signal Signal Element element Timing Testing 7 Signal Ground 16 Secondary 25 Unassigned

ii)

Double Twisted Pair In this version the master does not have to have tristate o/p the slave devices transmit over the second twisted pair ,which is intended for sending data from slave to master.The technique allows the user to implement multiple communication in system,which where originally design for one RS232.The course master software needs to be modified the master periodically sends querry packets to all slave devices.Rs485 system can also work in a point to point system.The high impedance state of the RS485 o/p driver is not used.

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2, April 2012.

C. I2C This is just two wires, called SCL and SDA. SCL is the clock line. It is used to synchronize all data transfers over the I2C bus. SDA is the data line. The SCL & SDA lines are connected to all devices on the I2C bus. There needs to be a third wire which is just the ground or 0 volts. There may also be a 5volt wire is power is being distributed to the devices. Both SCL and SDA lines are "open drain" drivers. What this means is thatthe chip can drive its output low, but it cannot drive it high. For the line to be able to go high you must provide pull-up esistors to the 5v supply. There should be a resistor from the SCL line to the 5v line and another from the SDA line to the 5v line. You only need one set of pull-up resistors for the whole I2C bus, not for each device, as illustrated below: The value of the resistors is not critical. I have seen anything from 1k8 (1800 ohms) to 47k (47000 ohms) used. 1k8, 4k7 and 10k are common values, but anything in this range should work OK. I recommend 1k8 as this gives you the best performance. If the resistors are missing, the SCL and SDA lines will always be low -nearly 0 volts - and the I2C bus will not work. Masters and Slaves The devices on the I2C bus are either masters or slaves. The master is always the device that drives the SCL clock line. The slaves are the devices that respond to the master. A slave cannot initiate a transfer over the I2C bus, only a master can do that. There can be, and usually are, multiple slaves on the I2C bus, however there is normally only one master. It is possible to have multiple masters, but it is unusual and not covered here. On your robot, the master will be your controller and the slaves will be our modules such as the SRF08 or CMPS03. Slaves will never initiate a transfer. Both master and slave can transfer data over the I2C bus, but that transfer is always controlled by the master. The I2C Physical Protocol When the master (your controller) wishes to talk to a slave (our CMPS03 for example) it begins by issuing a start sequence on the I2C bus. A start sequence is one of two special sequences defined for the I2C bus, the other being the stop sequence. The start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change while the SCL (clock line) is high. When data is being transferred, SDA must remain stable and not change whilst SCL is high. The start and stop sequences mark the beginning and end of a transaction with the slave device.

Fig.4 operation diagram of I2C Bus.

Data is transferred in sequences of 8 bits. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). The SCL line is then pulsed high, then low. Remember that the chip cannot really drive the line high, it simply "lets go" of it and the resistor actually pulls it high. For every 8 bits transferred, the device receiving the data sends back an acknowledge bit, so there are actually 9 SCL clock pulses to transfer each 8 bit byte of data. If the receiving device sends back a low ACK bit, then it has received the data and is ready to accept another byte. If it sends back a high then it is indicating it cannot accept any further data and the master should terminate the transfer by sending a stop sequence.

Fig. 5 General serial communication

Fig. 6 Data line with clock cycle of I2C Bus

The standard clock (SCL) speed for I2C up to 100KHz. Philips do define faster speeds: Fast mode, which is up to 400KHz and High Speed mode which is up to 3.4MHz. All of our modules are designed to work at up to 100 KHz. We have tested our modules up to 1MHz but this needs a small delay of a few uS between each byte transferred. In practical robots,

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2, April 2012. we have never had any need to use high SCL speeds. Keep SCL at or below 100 KHz and then forget about it.I2C Device Addressing All I2C addresses are either 7 bits or 10 bits. The use of 10 bit addresses is rare and is not covered here. All of our modules and the common chips you will use will have 7 bit addresses. This means that you can have up to 128 devices on the I2C bus, since a 7bit number can be from 0 to 127. When sending out the 7 bit address, we still always send 8 bits. The extra bit is used to inform the slave if the master is writing to it or reading from it. If the bit is zero are master is writing to the slave. If the bit is 1 the master is reading from the slave. The 7 bit address is placed in the upper 7 bits of the byte and the Read/Write (R/W) bit is in the LSB (Least Significant Bit).

System control Block

Low Speed Prescaler

SPIAENCLK

SYSCLKOUT

LSPCLK

SPISIMO

SYSR

SPISTE

SPI

r

GPI O MUX

SPICLK

Register

SPISOMI

SPIINT/R

TXIN

Fig. 7 Address line with clock cycle of I2C Bus

The placement of the 7 bit address in the upper 7 bits of the byte is a source of confusion for the newcomer. It means that to write to address 21, you must actually send out 42 which is 21 moved over by 1 bit. It is probably easier to think of the I2C bus addresses as 8 bit addresses, with even addresses as write only, and the odd addresses as the read address for the same device.

Fig. 8 Enhanced SPI Module

Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. The SPI module features include:  SPISOMI: SPI slave-output/master-input pin  SPISIMO: SPI slave-input/master-output pin  SPISTE: SPI slave transmit-enable pin  SPICLK: SPI serial-clock pin.  Two operational modes: master and slave  Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins.  Data word length: one to sixteen data bits  Four clocking schemes (controlled by clock polarity and clock phase bits) include:  Simultaneous receive and transmit operation (transmit function can be disabled in software)  Transmitter and receiver operations are accomplished through either interrupt- driven or polled algorithms.

D. SPI The serial peripheral interface (SPI) is a high- speed synchronous serial input/ output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-to-digital converters (ADCs).Multi device communications are supported by the master/slave operation of the SPI. The port supports a 16-level, receive and transmit FIFO for reducing CPU servicing overhead – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. (a) Enhanced SPI Module Overview

Table II Device information of ARM Processor

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 2, April 2012. Device

LPC2141 LPC2142 LPC2144 LPC2146 LPC2148

No. of pins

64 64 64 64 64

End point USB RAM 8 KB 16 KB 16 KB 16 KB 32KB +8KB

Onchip FLASH 32 KB 64 KB 128 KB 256 KB 512 KB

IV. CONCLUSION In this work, after successful experimentation on Different protocol working principal. Outcome of this work show that data is transmitted through RS232 & RS485 to PC, is successfully implemented on kiel platform to assert the UART signal of LPC2418 processor, so as to show the output on hyper terminal. The communication between IC’s is through I2C protocol where as communication other peripheral (ADC) is through SPI protocol.

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Krishna swami, Gupta, ”Profile guided selection of ARM AND THUMB instruction”2002.

[2]

I2C-BusSpecification’,Philips Semiconductors, January 1992.

[3]

The I2C-Bus and How to Use It’, Philips 1995.

Semiconductors, April

[4]

Embeded system design Rajkamal.

[5]

Zhang Zhijiang Zhang Yunyong , liu Yunjie,SIP protocol and application,Electronic Industry press,Beijing,2005.

[6]

Hilt V Widjaja I.Controlling overloads in network of SIP servers.Network protocol 2008.IEEE International conference on 19-22 oct 2010.

[7]

EIA standard RS-232-C: Interface between Data Terminal Equipment and Data Communication Equipment Employing Serial Binary Data Interchange. Washington: Electronic Industries Association. Engineering Dept. 1969.

[8]

Serial Peripheral Interface (SPI) SPRUEU3A–August 2008–Revised June 2009

[9]

www.ti.com Enhanced SPI Module Overview.

Jadhav S.K. MTech (Embedded & VLSI), Acropolis Institute of Techology Indore, [email protected] Mukti Avhad, MTech (Embedded & VLSI), Acropolis Institute of Techology Indore Gaikwad A.B. (M.E Communication), SSGB COE & TECH. Bhusaval. [email protected].

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