Electronics Laboratory II EECS 3440

Lab Manual

January 2002 rev. 2 editor Roger King, prof. EECS

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Foreword This lab is a continuation of the lab experience included with the course Electronics I. As such, it would be repetitious to include the sections describing the equipment, documenting procedures, or reviewing SPICE. For the same reason, a comprehensive set of data sheets is not included in this lab manual. (The PN2222A data sheet is included because of its frequent use.) It is assumed that the student has retained a copy of the lab manual from the Electronics I (EECS 3400) course. The main new topics covered by this lab are frequency response and feedback in analog electronic systems. These are fundamental for any practical electronics, and in addition, each of these has a counterpart in the digital signal processing world. An understanding of the behavior of the analog system is the best preparation for an understanding of the corresponding digital-domain behavior. As with Electronics I, this lab will also emphasize the use of SPICE along with hands-on experimentation to gain an intuitive understanding of the electronics involved. The student is encouraged in each experiment to simulate the lab using SPICE, to hand work a simplified analysis, and to compare these with the observed experimental behavior.

This lab is continually being redeveloped. Please give the instructor your feedback concerning the lab experiments and procedures so that the future manuals can be as error-free as possible.

Prof. Roger King, EECS July 1998

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Table of Contents

Experiment 1 SPICE Modeling the ‘741 Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Experiment 2 ‘741 Op-Amp Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Experiment 3 SPICE Simulation of a JFET Common-Source Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Experiment 4 JFET Common-Source Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Experiment 5 Small-Signal CC and CB Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Experiment 6 Bypass and Coupling Capacitor Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Experiment 7 BJT High-Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Experiment 8 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Experiment 9 Complementary-Symmetry Push-Pull Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Experiment 10 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Experiment 11 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Experiment 12 Wien Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Experiment 13 Analog/Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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Experiment 1 SPICE Modeling the ‘741 Op-Amp Introduction The purpose of this experiment is to gain experience with ac and transient SPICE simulation procedures, and to learn about the slew rate and bandwidth behaviors of a typical general-purpose op-amp. A simple model of the internal structure of the ‘741 op-amp will be used. Equipment Needed v PC running a current version of PSpice

v SPICE model for a ‘741 general-purpose op-amp

Procedure Use PSpice to run an analysis of the circuit of Fig. 1. A model for the ‘741 op-amp is given in Fig. 2. (The model in Fig. 2 is also available from the instructor on disk.) The actual circuit requires two 15-V power supplies for the op-amp; the model in Fig. 2 works without having to explicity show these power supplies. Most general purpose op-amps have two internal stages of gain: the first one is modeled in Fig. 2 as the voltage-controlled current source Gstage1, and the second one is modeled as the voltage-controlled voltage source Estage2. 1. Make the input source Vin a pulse voltage source (VPULSE) in series with a transient sine source (VSIN). Set the ac component of VPULSE to 1 V, and its pulse component to transition from -1 V to +1 V as a square wave with a period of 400 μs (200 μs at -1 V, and 200 μs at +1 V). Set up VSIN for an offset voltage of 0, an amplitude of 50 mV, and a frequency of 40 kHz. The input voltage to the inverting amplifier will then be a 1-V ac signal during the ac analysis (a steady-state phasor analysis), and it will be a 50-mV 40-kHz sine wave added to a 1-V 2.5-kHz square wave during the transient simulation. 2. Run an ac sweep from 0.1 Hz to 10 MHz, and a transient simulation for 500 μs.

Fig. 1 Inverting amplifier using a ‘741 op-amp. 1

SPICE Modeling the ‘741 Op-Amp 3. Use PROBE to view the results of the ac sweep. The input ac voltage Vin will have a constant magnitude of 1 V (0 dB); display the dB magnitude of the output voltage Vout. Determine the high-frequency cutoff of the inverting amplifier by finding the frequency at which the output is reduced to 3 dB less than its low-frequency value. 4. Determine why the gain of the inverting amplifier is not constant up to a very high frequency. Use PROBE to plot the gain of the op-amp itself by adding the plot DB(Vout/-Vid) to the previous plot. Note that -Vid is the input voltage to the op-amp, not the input voltage to the circuit. Print this composite plot of the inverting circuit gain together with the op-amp gain for a frequency range of 0.1 Hz to 10 MHz. 5. Use PROBE to view the results of the transient run. Plot the output voltage Vout together with -10 times the input voltage Vin. Ideally, these two traces should coincide. However, there will be some notable discrepancies. Print this composite plot. 6. The output voltage will show evidence of slew rate limiting at the times that the square wave transitions. During this time, the Vout rises or falls with a well-defined slope, and the small sinusoidal component of signal disappears. To find out why, add an additional Y-axis to the plot and add a trace of the output current leaving the first stage, I(Gstage1). The vertical scale of this new Y-axis should be -15 μA to +15 μA, and there should be evidence that the current output of stage 1 is clipping. Print this composite plot. Report There is no formal report for this lab. Simply record your findings and comments and submit them in a homework format. In the following, be careful to distinguish the op-amp by itself from the complete amplifier circuit of Fig. 1. Please answer the following questions: Vout 1. What is the voltage gain Vin (in dB) of the circuit of Fig. 1?

2. The high-frequency cutoff fH is defined as the frequency at which the gain is down to 3 dB less than its low-frequency value. What is the value of fH for this amplifier? Vout 3. What is the voltage gain of the op-amp itself Vid (in dB) at very low frequencies? Describe the variation of the op-amp gain with respect to frequency. What is the value of fH for the op-amp by itself?

4. Describe the behavior of this inverting amplifier when it is producing a 10-V square-wave output voltage, especially with regard to the regions where Vout is in transition. Why does the sine waveform disappear from the output waveform during the transition times?

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SPICE Modeling the ‘741 Op-Amp

Fig. 2 Inverting amplifier with ‘741 op-amp model.

Table 1 Device Parameters for the Inverting Amplifier SPICE Model VPULSE

VSIN

Gstage1

Estage2

D1 & D2

Input source for ac steady state + transient square wave

Input source for transient sine wave

Transconductance amplifier (VCCS) with saturation

Voltage amplifier (VCVS) with saturation

Generic diodes (use Dbreak model)

DC=0 AC=0 VOFF=0 VAMPL=50mV FREQ=40kHz

TABLE= (-75mV,-15uA) (+75mV,+15uA)

DC=0 AC=1V V1=-1V V2=+1V TD=200us TR=0 TF=0 PW=200us PER=400us

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TABLE= (-50mV,-13V) (+50mV,+13V)

Dbreak D( IS=1E-14 CJO=0.1pF RS=0.1)

SPICE Modeling the ‘741 Op-Amp

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Experiment 2 ‘741 Op-Amp Circuits Introduction The purpose of this experiment is to gain experience with the '741 op-amp in several typical applications, and to discover some of the basic limitations of all op-amps. The observed behavior of the inverting amplifier will be compared with the simulated behavior from Experiment 1. Pre-Lab It is expected that Experiment 1, "SPICE Modeling the '741 Op-Amp," has already been performed. Equipment Needed v LM741/MC741/SN741 op-amp (prefix indicates manufacturer)

v Power supplies, function generator, oscilloscope

Procedure 1. Connect the circuit of Fig. 1. Use a 100-mV peak 1-kHz sine wave input voltage to vo measure the system voltage gain Av = vi . (The expected result is -10.) To reduce the high-frequency noise on the scope channel handling the 100-mV signal, turn on its bandwidth limit, found on the channel input menu. 2. Measure the high-frequency cutoff (fH) of Fig. 1 using a 100-mV sine wave input and monitoring the output voltage. Starting at 1 kHz, increase the frequency of v i until the output v o has decreased to 70.7% of its 1-kHz value. Record this -3 dB frequency as fH . (The expected value of fH is about 90 kHz.) 3. Collect two output voltage waveforms from Fig. 1 and display them simultaneously using the memory capability of the DSO. Focus on the rising edge of the square wave response. Display and record: a) The response to a 50-mV peak 1-kHz square wave. Measure the slope of the rising edge of the response using a horizontal scale of 0.5 μs/div, and a vertical scale of 0.2 V/div. b) The response to a 500-mV peak 1-kHz square wave. Measure the slope of the rising edge of the response using a horizontal scale of 5 μs/div, and a vertical scale of 2 V/div. 4. Measure the slew rate (SR) capability of the '741 op-amp from the recorded response of (b) above. (The expected value of SR is about 0.5 V/μs.) Try increasing the amplitude 5

‘741 Op-Amp Circuits of the input square wave. Can the output voltage attain a rate-of-change any greater than your measured slew rate? 5. Connect Fig. 2. Measure the voltage gain of Fig. 2 using a low amplitude 1-kHz sine wave. (The expected result is +11.)

6. Connect Fig. 3 and display the input and output voltage waveforms together, using a 0.5-V peak 1-kHz square wave for v i . Does the output appear to satisfy the following transfer function?

vo =

−1 RiCf

¶0t vi(t) dt + vo(0)

7. Record this square wave input with its triangle wave response. Record the input/response pair for a 1-kHz sine wave. Report 1. Compare the 1-kHz voltage gains measured for Figs. 1 and 2 with those predicted by ideal op-amp equations. 2. Compare the high-frequency cutoff measured for Fig. 1 with that predicted by the SPICE simulation in Experiment 1. Use the SPICE model for the '741 op-amp to explain why the circuit gain decreases at frequencies above fH . 3. Compare the slew rate measured for Fig. 1 with that predicted by the SPICE simulation in Experiment 1. Does increasing the input voltage amplitude beyond 1 V increase the slew rate observed at the output? Why? 4. Do the integrator responses observed in steps 6 and 7 agree with the equation given for an ideal op-amp? Compare the shapes and amplitudes of the predicted and observed responses to square wave and sine wave inputs.

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‘741 Op-Amp Circuits

Fig. 1 Inverting amplifier, 8-pin dual-in-line plastic package (top view).

Fig. 2 Non-inverting amplifier.

Fig. 3 Integrator.

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‘741 Op-Amp Circuits

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Experiment 3 SPICE Simulation of a JFET Common-Source Amplifier

Introduction The purpose of this experiment is to gain practical experience with the mechanics of the SPICE simulations for bias point and ac analysis. The circuit used is a JFET common-source amplifier. Pre-Lab There is no pre-lab for this experiment. Equipment Needed v Current version of PSpice

Procedure Turn on the PC and open the current version of PSpice. Enter the circuit of Fig. 1 using the library model for the 2N5457 JFET. The signal source Vin should be an ac source, set to an amplitude of 1 V, and with its dc component set to 0 V. 1. Set up the simulation for a detailed bias point solution, a dc sweep, and an ac sweep. The bias point solution will consist of a detailed listing of the operating-point solution in the output file, along with calculated incremental model parameters for the JFET. Set the dc sweep to step the dc value of source Vin from -5 V to +5 V in 0.1-V steps. Set the ac sweep to step the frequency of the ac content of Vin from 1 Hz to 100 kHz in 101 steps

Fig. 1 JFET common-source amplifier. 9

SPICE Simulation of a JFET Common-Source Amplifier per decade. 2. After running the simulation, examine the output file to find the bias point solution. The JFET drain-source voltage (VDS) must be more than 2 V, and the drain current (ID) must be more than 0.1 mA. If the bias point does not represent a reasonable operating point for an amplifier, there is no point in proceeding further - something has gone wrong in the entry of the schematic, or the design of the circuit. Note: Later versions of SPICE allow you to enable direct display of the bias point solution on the schematic diagram. Record ID and VDS . 3. Use probe to display the dc sweep results. Plot the output voltage Vo vs. the input voltage Vin. Use the “add trace” menu to add a plot of the derivative of Vo [the syntax is “D(V(Vo))”]. Record these traces. 4. Use probe to display the ac sweep results. Plot the dB equivalent of the output voltage Vo vs. frequency. (Vin should be 0 dB at all frequencies.) Record this trace. Report No formal report is required for this experiment. Simply summarize the results you have obtained in a homework format. Briefly answer the following questions: 1. Discuss the location of the optimum Q-point for this amplifier using the plot of Vo vs. Vin obtained from the dc sweep. Use the plot of the derivative of Vo to estimate the gain at this Q-point. At what values of Vo (upper and lower) will the amplifier saturate? 2. Discuss the voltage gain of the amplifier as measured at various frequencies. Why does the voltage gain vary with frequency? 3. For what range of frequencies does the voltage gain read from the ac sweep agree with the incremental voltage gain read from the dc sweep? Why? Notes on SPICE SPICE computes the bias point analysis by setting all ac and transient components of all sources to zero, and considering only the dc components of these sources. The dc sweep is computed by stepping the dc component of the source specified in the dc sweep setup statement. During dc analyses, capacitors are open circuits; and inductors are short circuits. When SPICE does an ac sweep, it first uses the dc source values to compute the dc bias point solution. It then computes incremental models for all devices in the circuit based upon the bias point. After this, SPICE applies an ac steady-state analysis to the incremental equivalent circuit over the frequency range given in the setup. The ac amplitude of the source Vin can be set to any convenient value without causing amplifier saturation because the incremental model is always a linear model. 10

Experiment 4 JFET Common-Source Amplifier Introduction The purpose of this experiment is to investigate the performance of a JFET common-source amplifier. Equipment Needed v Normal laboratory equipment

v 2N5457 n-channel JFET

v For alternate VP and IDSS , you may substitute 2N5458/59

Pre-Lab Estimated typical values of the JFET parameters are: VP = -2.5 V and IDSS = 3 mA. Obtain a 2N5457 data sheet and find out what the allowable ranges of these parameters are. Read the text file of the 2N5457 SPICE model currently used in this department and determine what values the model assumes for these parameters. Procedure 1. Obtain the FET drain characteristics using the curve tracer. Measure the pinchoff voltage VP and the zero-bias drain current IDSS. Make sure these lie within the ranges promised on the 2N5457 data sheet. Record the measured values of these two parameters, but you do not need to record the drain characteristics. 2. Connect the circuit of Fig. 1 without C1 and measure its quiescent operating point (IDQ and VGSQ). 3. Set the function generator for a 5-kHz sine wave with zero dc offset. Increase the FG voltage level until the output voltage V o is on the verge of clipping-type distortion. Record the output waveform, showing evidence of the voltage levels at which clipping will occur. 4. Reduce the signal level to assure an undistorted output. Measure and record the voltage gain Av gain.

=

Vo Vi at 5 kHz. Place C1 into the circuit and record its effect on the voltage

5. With C1 in the circuit, measure and record the amplitude and phase of the output voltage (relative to the input voltage) at the following frequencies: 5 kHz, 500 Hz, 50 Hz.

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JFET Common-Source Amplifier Report 1. Use the measured values of VP and IDSS to predict the Q-point (IDQ and VGSQ). Compare these values with the experimentally-measured values. Compare these values with the prediction of a SPICE bias point solution using the 2N5457 model. 2. Use the measured values of VP and IDSS to estimate the transconductance (gm). Calculate the midband voltage gain (the 5-kHz gain) with and without C1, and compare with the experimentally-measured values. Also, compare the measured 5-kHz gain with the result of a SPICE ac analysis. 3. Estimate the maximum possible output voltage before the onset of severe distortion. Consider clipping due to the drain current going to zero, and distortion due to the JFET entering its ohmic region of operation. Compare these estimates with your observed data. 4. Comment on the observed frequency response data. What happens to the signal as its frequency is lowered below midband? Why? Compare these experimental results with the results of a SPICE ac frequency sweep.

Background Refer to your electronics text for background on modeling the JFET. For the purpose of this experiment, it is OK to ignore channel-length modulation in modeling the JFET. Be aware that various electronics books may present the following equations using different symbols. v

iD = IDSS 1 − VGSP and ØiD gm = ØvGS Q point = =

2IDSS −VP 2 VP

1−

2

VGS VP

IDSS $ ID

where IDSS = zero-gate-voltage drain current, and VP = pinchoff voltage. The equations above are valid only in the constant-current (saturation, or pinch-off) region.

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JFET Common-Source Amplifier

Fig. 1 JFET common-source amplifier.

Fig. 2 2N5457 case and pin-outs.

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JFET Common-Source Amplifier

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Experiment 5 Small-Signal CC and CB Amplifiers Introduction The purpose of this experiment is the measurement of the small-signal voltage gain, input resistance, and output resistance of a common-collector (emitter follower) and a common-base amplifier. These two circuits are then compared to each other. Equipment Needed v Normal laboratory equipment

v PN2222A npn transistor

Procedure Connect the circuit of Fig. 1 and measure its quiescent operating point (ICQ and VCEQ). Connect a 5-kHz sine wave signal source to the input terminals, and a 100-Ω load resistor to the output. Measure the following small-signal amplifier parameters using a signal level low enough to avoid clipping, yet high enough to be measurable. 1. Measure the voltage gain Av =

Vo Vi

.

∏

2. Measure the input resistance Ri . ∏

3. Measure the output resistance Ro . Connect the circuit of Fig. 2 and measure its quiescent operating point (ICQ and VCEQ). Connect a 5-kHz sine wave signal source to the input terminals, and a 10-kΩ load resistor to the output. Measure the same small-signal amplifier parameters as previously. Remember to keep the signal level small enough to avoid any visible distortion of the sinusoidal waveforms. 1. Measure the voltage gain Av =

Vo Vi

.

∏

2. Measure the input resistance Ri . ∏

3. Measure the output resistance Ro . Use the curve tracer to measure the incremental current gain (βac = hfe) of your transistor in the neighborhood of IC = 1 mA, VCE = 10 V.

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Small-Signal CC and CB Amplifiers

Report 1. Using reasonable approximations, predict the Q-point of Figs. 1 and 2, assuming that βdc = 150. Compare this with the experimentally measured Q-point. 2. Using the values of βac (hfe) and Q-point which were measured experimentally, predict the ∏ ∏ following: A v , Ri , Ri , R o , and Ro for Figs. 1 and 2. 3. Compare these calculated values with the experimentally-determined values. Compare the relative values of A v , Ri , and R o for Figs. 1 and 2. Based on simplified formulas, give the most important factor(s) which determine A v , Ri , and R o for Figs. 1 and 2.

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Small-Signal CC and CB Amplifiers

Fig. 1 Common-collector (emitter follower) amplifier.

Fig. 2. Common-base amplifier.

Fig. 3 PN2222A package and pin-out.

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Small-Signal CC and CB Amplifiers Appendix: The Experimental Determination of Voltage Gains and Incremental Resistances 1. Voltage gain is measured with a specified load resistor in place by monitoring Vi and V o with a two-channel scope. The smallest measurable level is used; the measurement is only valid if no appreciable distortion occurs in either Vi or V o . ∏

2. Input resistance Ri can be measured by monitoring V o while driving the amplifier from a source having a known source resistance (RS). Then, using a variable resistor in series with the source, the source resistance is increased until V o drops to one-half its previous value. We have: 3. Vo1 = Av Vs

Vo2 = Av Vs

∏

Ri

(first measurement), and

∏

Ri + Rs

(1)

∏

Ri ∏

Ri + Rs + Rpot

(second measurement)

(2)

4. Therefore: Vo1 Vo2

=

1 2

=

∏

Ri + Rs

(3)

∏

Ri + Rs + Rpot

∏

Ri = Rpot − Rs

(4) ∏

5. The input resistance Ri is calculated from the measured value of the variable resistor (R pot ) and the value of the source resistance (R s ). For the FG in the electronics lab, R s = 50 . This measurement is only valid for small (undistorted) signals. Ri is easily ∏ calculated from Ri . ∏

6. Output resistance Ro is measured by monitoring V o while driving the amplifier with a signal source having the specified source resistance R s ; V o is first measured, and then a variable resistor is paralleled with the output terminals and adjusted so that V o is one-half its previous value. The resistance of the potentiometer is then equal to the output ∏ resistance Ro . This measurement is only valid for small signals. R o is easily calculated ∏ from Ro .

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Experiment 6 Bypass and Coupling Capacitor Effects Introduction The purpose of this experiment is the measurement of the low-frequency response of an ac-coupled amplifier. Equipment Needed v Normal laboratory equipment

v PN2222A npn transistor

v Switchable 0-dB/40-dB 50-Ω attenuator

Pre-Lab Calculate the expected locations of the poles and zeros contributed by each capacitor in Fig. 1 (they each act independently). Calculate the midband gain, and sketch a Bode plot of the expected magnitude of the voltage gain from 1 Hz to 10 kHz. Procedure Gain will be measured over a wide range of values in this experiment: The amplitude of the input signal may need to be changed in order to maintain a measurable output level, but at all times keep the levels low enough to avoid appreciable distortion, yet high enough to be measurable. You will need to use a switchable 0-dB/40-dB 50-Ω attenuator at the FG output to do this. Turn on the bandwidth limiters in both channels of the scope to reduce any high-frequency noise present in low-level signals.

Fig. 1 Common-emitter amplifier with blocking and bypass capacitors. 19

Bypass and Coupling Capacitor Effects 1. Connect the circuit of Fig. 1 and measure its operating point (I C and VCE). Note that the function generator (FG) must be connected to provide a dc path for the base current. Make sure that the operating point is reasonable for operation as an amplifier. 2. Set the FG to produce a 7-mV rms 10-kHz sine wave at Vi and measure the midband gain at 10 kHz. (Expected value is about +40 dB.) Make sure that both scope channels are dc-coupled throughout this procedure. An ac-coupled scope channel is itself a high-pass filter. 3. Measure the gain magnitude (in dB) over the frequency range of 10 Hz to 10 kHz. Mark the data points on your predicted frequency response plot. If there is a deviation of more than 6 dB, you should investigate the reason for the discrepancy. Use the 2-channel scope to measure the peak-to-peak values of Vi and Vo for the purpose of measuring gain.

Details Lower the frequency by steps in a 10-4-2-1 sequence (e.g., 1 kHz - 400 Hz 200 Hz - 100 Hz), taking gain magnitude measurements at each step. You may need to increase the input signal level at lower frequencies to maintain a measurable output signal. Take data from 10 kHz down to 100 Hz. Continue going down in frequency towards 10 Hz as far as meaningful data can be obtained. Use "averaging1" (found in the scope Display menu) to reduce the amount of noise on small signals. 4. Divide the midband gain measured in part 1 by 1.414 (this is equivalent to subtracting 3 dB from its decibel value). Use the FG to experimentally measure the frequency at which the amplifier's gain is 3 dB below its midband value. This is called the "low-frequency cutoff."

Report 1. Bode plot the pre-lab calculated frequency response on 4-cycle semi-log paper. Use dB notation, and use a frequency range of 1 Hz to 10 kHz. 2. Mark the experimental data points on this graph. Do they agree well with the predicted values? 3. Identify the midband gain from the experimental data, and from the calculated response. How do they compare? 4. Identify the low-frequency cutoff (fL) from the experimental data, and from the calculated response. How do they compare? 1

"Averaging" is the process of storing repeated acquisitions of the waveform, each one based on the trigger event, and point-by-point averaging these stored waveforms to produce the display. Averaging only works if there is a stable trigger event.

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Bypass and Coupling Capacitor Effects Bode Plots The actual gain vs. frequency plot of an ac-coupled amplifier is a smooth curve. However, Bode pointed out that if semi-log paper is used, a series of straight-line asymptotic approximations to the gain curve will be close enough for many engineering purposes. The gain magnitude in dB is placed on the linear scale; the frequency is placed on the log scale. Fig. 2 below shows sample Bode plots of the contribution of the emitter bypass C1 acting alone (upper figure), and the collector blocking capacitor C2 acting alone (lower figure).

Fig. 2 Bode plot of frequency response of C1 alone (upper figure); and C2 alone (lower figure) 21

Bypass and Coupling Capacitor Effects

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Experiment 7 BJT High-Frequency Performance Introduction The purpose of this experiment is the investigation of the high-frequency performance of a BJT common-emitter amplifier. The transistor junction capacitances Cπ and Cμ will be estimated from typical data sheet information. Equipment Needed v Normal laboratory equipment

v PN2222A npn transistor

Pre-Lab Study the appendix to this lab which shows how to estimate the transistor junction capacitances on the basis of the limited information typically given on a data sheet. Procedure The circuit of Fig. 1 may not maintain a stable dc operating point; therefore, you should verify at several stages during the experiment that the operating point is still 5 mA/5 V (IC/VCE). The collector current is controlled by adjusting VBB , and the collector-emitter voltage is then set by adjusting VCC . Be sure to remove the dc voltmeter or milliameter from the circuit when making the actual gain measurements. Gain will be measured from midband (5 kHz) to beyond the high-frequency cutoff fH (1 MHz).

Fig. 1 Common-emitter amplifier. 23

BJT High-Frequency Performance

1. Connect Fig. 1 using a 1 K load resistor (RL). Set the dc operating point and remove all Vo

dc meters from the circuit. Measure the midband gain factor V i at 5 kHz using a small signal. Measure the transistor base-emitter resistance at 5 kHz by measuring the ac signal at each end of R1. 2. Take gain measurements from 5 kHz to 1 MHz. The objective is to accurately determine the high-frequency cutoff (fH). Take enough data points to be sure of the value of the midband gain, and the frequency at which the gain is reduced to 70.7% of its midband value. (Expected midband gain and hf cutoff are about -100 and 400 kHz.) 3. Change the load resistor (RL) to 560 Ω. Readjust the dc operating point to maintain 5 mA/5 V. Measure the midband gain and the high-frequency cutoff again. (The expected values are now 56% and 179% of the previous measurements, respectively.)

Report 1. Obtain a copy of the transistor data sheet for type 2N2222A or PN2222A, and put it in an appendix to your report. Use the data sheet to estimate values for C π and Cμ . 2. Calculate the midband gain and high-frequency cutoff for each of the two values of load resistance used. Compare these results with the experimental data. 3. Use SPICE to simulate the frequency response of the experimental circuit. Compare the midband gain and high-frequency cutoff predicted by SPICE with your calculated and observed data. After running your simulation successfully, open the *.OUT file and read the values for Cπ and Cμ that were produced by SPICE. Compare these with your estimated values.

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BJT High-Frequency Performance Appendix A - Estimating Cπ and Cμ From a Data Sheet The capacitance associated with a pn junction has two components: the transition capacitance, which is a nonlinear function of the junction voltage; and the diffusion capacitance, which is directly proportional to the junction forward current. In the active mode, the collector-base junction is reverse-biased, and therefore it has only transition capacitance, whose value is determined by the dc collector-base voltage. This capacitance is denoted Cbc , Cμ , Cob or "output capacitance" on most data sheets. A complete data sheet will typically contain a graph of Cμ vs. collector-base reverse voltage. An abbreviated data sheet will at least give a single value for C μ . Note that the transition capacitance increases with decreasing reverse-bias, reaching its maximum value at zero bias. In the active mode, the emitter-base capacitance is composed of both transition and diffusion components. The transition component is generally small and independent of operating point (VBE is almost constant at 0.7 V); the diffusion component is generally large and directly proportional to emitter current. The foregoing is true when the transistor is used at normal current densities: In a large transistor used at low current, C π will not be zero; it will approach a lower limit equal to its transition capacitance. The transition component of C π can be estimated from the data sheet as the zero-voltage limiting value of the reverse-biased emitter-base capacitance. The diffusion component of Cπ is directly proportional to IE , and is never directly given on the data sheet. The short-circuit unity-current-gain frequency (denoted fT and frequently called the current gain-bandwidth product, or GBW) is normally found on the data sheet. It can be shown that this is related to the junction capacitances by:

2f T =

gm C  + C

If the proposed operating point current (IE ) is within one decade of the operating point used in making the data sheet measurement, it may be assumed that fT does not change and the computation of Cπ is straightforward. If the proposed IE is small, model Cπ by the following:

C = X0 + X1 $ IE X0 is the zero-bias limiting value of the transition capacitance, and X1 is readily calculated from the given GBW data together with the operating point used to measure it. This equation is then used to estimate Cπ at the proposed operating point. As an example, capacitances are estimated from the data sheet for a National Semiconductor PN2222A. A graph labeled "Emitter Transition and Output Capacitance vs. Reverse Bias Voltages" directly states that C μ is typically 4.5 pF at VCB = 4.3 V. From the same graph, X0 = 21 pF. Under the small-signal characteristics, it is stated that fT is at least 300 MHz at IC = 20 mA. From this data, X1 = 20 pF/mA. Therefore, Cπ is expected to be 121 pF at 5 mA. 25

BJT High-Frequency Performance An alternative calculation, which simply assumes that fT is the same at 5 mA as at 20 mA, produces Cπ = 102 pF. Either is justifiable given the precision of the available data.

Appendix B - SPICE Simulation of the CE Amplifier The CE amplifier of Fig. 1 can be easily entered into SPICE and simulated using a 2N2222A transistor model. The problem that will immediately arise is that the dc operating point in the simulation will not be the same as that in the lab. The gain and bandwidth results are strongly operating-point dependent, and therefore will not match the lab results at all. The newer versions of PSpice allow the direct display of the calculated operating point on the schematic: Enable this option and verify that the correct operating point has been achieved before looking at the frequency response data in probe. With the direct display of the bias point solution, it is not difficult to iteratively adjust VBB to obtain IC = 5 mA, and then adjust VCC to obtain VCE = 5 V. This process is speeded if all other analyses except for bias point are disabled during this iterative procedure.

26

Experiment 8 Differential Amplifiers Introduction The purpose of this experiment is to investigate several key features of the balanced differential pair and the wide band (asymmetrical) differential pair. Equipment Needed v Normal laboratory equipment

v two PN2222A npn transistors

v Scope probe having known input capacitance

Pre-Lab Assuming that the transistors will have a dc current gain (β or hFE) equal to 100, predict the Q-points of Figs. 1 and 2. Estimate the differential gain (Ad) and the common-mode gain (Acm) for Fig. 1. In each case, the output is taken at Q2's collector. Procedure 1. Connect the circuit of Fig. 1 and verify that a reasonable Q-point is obtained. Remember that the amplifier is not properly biased unless a dc current path is provided from each transistor base to the ground. Substitute transistors until the collector currents of Q1 and Q2 match to within 10 μA of each other. Use the curve tracer to measure the ac current gain (βO or hfe) in the vicinity of the Q-point for each transistor. 2. Use the signal connections shown in solid lines in Fig. 1 to measure the differential-mode Vo gain ( Ad = Vs ) of the symmetric differential pair. Note that the output is taken single-endedly (from one collector only). This is a midband, small-signal measurement; use 400 Hz and a signal level low enough that there is no appreciable distortion in the output sine wave. Use an attenuator as needed to reduce the output of the function generator (FG). (The expected value is about 85.) 3. Measure the high-frequency cutoff fH of the symmetrical differential amplifier of Fig. 1. Note that the input capacitance of the scope probe 1 is a part of the high-frequency model of the circuit. (The expected value is about 27 kHz.) 4. Use the signal connections shown in broken lines in Fig. 1 to measure the common-mode Vo gain ( A cm = V cm ) of the symmetric differential pair. Use 400 Hz and a low signal level so that there is no appreciable distortion in the input or output waveforms. (The expected value is about -0.3.)

1

For the HP 10071A probe, the input capacitance is 16 pF.

27

Differential Amplifiers 5. Connect the asymmetric differential pair of Fig. 2 and verify that a reasonable Q-point is obtained. (VCB for Q2 should be between 10 and 18 V.) 6. Measure the gain ( Ad = Vs ) and the high-frequency cutoff of the asymmetric differential pair of Fig. 2. Note that the input capacitance of the scope probe is also an important part of the high-frequency model of this circuit. (The expected values are about 85 and 80 kHz, respectively.) Vo

Report 1. From the transistor data sheet, estimate the values of collector-base and emitter-base capacitance at the Q-point. Hint: at the current level used here, C π will be dominated by its transition component. 2. Calculate the theoretical values of Ad , Acm and fH for Figs. 1 and 2, and compare with the experimental results. (For Fig. 1, use Miller's Theorem and model the symmetrical differential amplifier as equivalent to a common-emitter stage.) 3. Use SPICE (with a 2N2222A model) to simulate this circuit, and compare these results with the experimental and calculated results. 4. Compare the gains and cutoff frequencies of Figs. 1 and 2. Compute a gain-bandwidth product for each.

28

Differential Amplifiers

Fig. 1 Symmetrical differential pair. The load capacitance is the scope probe capacitance.

Fig. 2 Asymmetrical differential pair. The load capacitance is the scope probe capacitance.

Fig. 3 PN2222A package and pin-out.

29

Differential Amplifiers

30

Experiment 9 Complementary-Symmetry Push-Pull Amplifier Introduction The purpose of this experiment is to observe the operation of a class-B complementary-symmetry amplifier and the use of negative feedback to improve its behavior. Equipment Needed v Normal laboratory equipment

v Complementary-symmetry output stage circuit board

v Load resistor (about 12 Ω, 5 W)

Procedure Connect the circuit of Fig. 1 using a complementary-symmetry output stage circuit board. Fig. 3 gives a top view (component side) of this circuit board to identify the correct connection points. Note that both Figs. 1 and 2 show only a simplified equivalent of the circuit board schematic: The details of the circuit board are shown in Fig. 3. In making connections, bring all ground leads separately back to the "COM" binding post on the circuit board (including the function generator and scope ground leads). This is known as a "star" grounding arrangement. 1. Use the function generator (FG) to apply a 10-V peak 100-Hz triangle wave as shown in Fig. 1. Connect the two scope channels as indicated. Display and record the input (Chan. 1) and output (Chan. 2) waveforms. Note carefully the defect in the output waveform around its zero crossings. This is known as "crossover" distortion. 2. Display and record an X-Y plot of output vs. input on the scope. (Look on the horizontal "Main/Delayed" menu.) Be sure that both channels are set for zero offset and 2 V/div before switching to the X-Y mode. This is the transfer function of the basic complementary-symmetry output stage. 3. Obtain a type '741 op-amp and connect Fig. 2, placing the op-amp on a proto-board. It is best to run separate jumper wires from each op-amp terminal to the corresponding terminals on the output stage circuit board. Make all power supply connections (+15 V, -15 V and COM) to the circuit board, not to the proto-board. Set the FG for 10 V peak at 100 Hz as before. 4. Display and record the input from the FG (Chan. 1) and the output (Chan. 2) waveforms. Note the suppression of the crossover distortion by the negative feedback. 5. Display and record an X-Y plot of output vs. input as before. Use identical vertical settings of 2 V/div and zero offset on both channels.

31

Complementary-Symmetry Push-Pull Amplifier 6. Investigate how the negative feedback functions to suppress the crossover distortion. Move the scope channel 1 to the two transistor bases (B1 and B2) on the circuit board. Switch the scope back to voltage vs. time. Display and record the input and output of the complementary-symmetry stage itself. Note the inverse crossover distortion at the input to the complementary-symmetry stage. 7. Maintain these two waveforms on the scope while increasing the FG frequency to 10 kHz. Note the decreasing ability of the feedback to cancel the crossover distortion at high frequency. Record these waveforms. Report 1. Explain the cause of the crossover distortion observed in steps 1 and 2. (Most electronics texts have a good discussion of this problem in a chapter on "power amplifiers" or "output stages.") 2. Analyze the circuit in Fig. 2 based upon the assumption of an ideal op-amp. (Assume that the voltages on pins 2 and 3 of the '741 must be exactly equal because of its infinite gain.) How does this suppress the distortion? Use the waveforms gathered in steps 4 and 5 to support your discussion. 3. Why is the distortion reduction in step 7 (at 10 kHz) not so good as it was at 100 Hz? Explain this in terms of a specific imperfection in all practical op-amps, as opposed to an ideal op-amp.

32

Complementary-Symmetry Push-Pull Amplifier

Fig. 1 Simplified diagram of the complementary-symmetry output stage.

Fig. 2 Complementary-symmetry amplifier with negative feedback.

Fig. 3 Pictorial top view and detailed schematic of the complementary-symmetry output stage. 33

Complementary-Symmetry Push-Pull Amplifier

Fig. 4 '741 pinout, top view.

34

Experiment 10 Negative Feedback Introduction The purpose of this experiment is to investigate the effects of shunt-shunt negative feedback on the gain, input resistance and output resistance of a transresistance amplifier. Equipment Needed v Normal laboratory equipment

v PN2222A npn transistor

Procedure Connect the circuit of Fig. 1. Verify that the Q-point is approximately 1 mA. All ac measurements will be at midband (5 kHz) and small signal (no appreciable distortion). 1. Measure the closed-loop voltage gain Av =

Vo Vs

. ∏

2. Measure the input resistance indicated on Fig. 1, Rif . This may be done by measuring the ac voltages VS and VSJ using the scope. Verify that these two voltages are in-phase. ∏

Compute the current in RS, and then find 60 Ω.)

Rif =

VSJ IRS . (The expected value is about ∏

3. Measure the output resistance indicated on Fig. 1, Rof . Fig. 2 shows how to do this: Remove the function generator (FG), but keep its source resistance R S in place as indicated. Connect the FG at the output terminal with a 100-K series resistor (R5). Set the FG for a 10-V peak 5-kHz sine wave output and measure voltages V1 and V2. ∏ V1 Compute the current in R5, and then find Rof = IR5 . (The expected value is about 370 Ω.) 4. Connect the circuit of Fig. 3. This is the amplifier with the feedback removed, but the loading effects of the feedback resistor Rf retained. Verify that the Q-point is the same as previously, approximately 1 mA. ∏

∏

5. Measure the voltage gain Av = Vs , input resistance Ri , and output resistance Ro using the same techniques as previously. (The expected values are -150, 3.2 KΩ and, 5 KΩ respectively.) Vo

35

Negative Feedback Report 1. Use feedback theory to calculate the gain Av = ∏

Vo Vs

∏

, input resistance Rif , and output

resistance Rof for Fig. 1. Be sure to note that the gain factor A v is not the one directly A stabilized by the feedback or given by the equation 1+A . 2. Use SPICE simulation to predict the gain and input/output resistances of Fig. 1. 3. Compare the results predicted by SPICE and by calculation to your experimental data.

Background - Measuring Input/Output Resistances in a Feedback System There are two general cautions to observe in analyzing a feedback system: The quantity which you are computing may not be the same as the one actually stabilized by the feedback; and everything (all gains and resistances) pertaining to the feedback amplifier is affected by the loop gain. The first caution applies to this lab in that the voltage gain of Fig. 1 is not directly stabilized by the feedback. Fig. 1 is a transresistance amplifier: Its current-to-voltage conversion factor is stabilized by the feedback. The best way to calculate the voltage gain of Fig. 1 is to compute the transresistance first, and then convert it into the voltage gain. The second caution affects the resistance measuring procedure used in this lab. The "ohmmeter" applied to the circuit must not alter the loop gain of the amplifier. (This caution must also be remembered in devising a SPICE-based procedure for determining the input and ∏ output resistances as well.) When measuring the input resistance Rif , the source resistance RS provides a convenient way of measuring the input current; however, changing the value of R S ∏ from that given will alter the measured value of Rif because it would alter the loop gain. The function generator (FG) is connected in series with a 1-KΩ resistor which is considered the source resistance. It is reasonably accurate to neglect the internal 50 Ω resistance of the FG.

Similarly, the measuring apparatus in Fig. 2 (the FG with R5) alters the loop gain, and ∏ thus produces an erroneous value of Rof . In this case, R5 is chosen to be much greater than the open loop value of the output resistance so that it will only change the open loop gain by a small amount and produce a reasonably accurate measurement.

36

Negative Feedback

Fig. 1 Amplifier with shunt-shunt feedback.

Fig. 2 Measuring the output resistance.

Fig. 3 Amplifier with feedback removed, but loading effects retained. 37

Negative Feedback

38

Experiment 11 Voltage Regulators Introduction The purpose of this experiment is to investigate the performance characteristics of two simple voltage regulators. Equipment Needed v Normal laboratory equipment

v MJE 371 pnp power transistor

v 1N754 6.8-V Zener diode (alternates: 1N4736 or 1N5235)

v Resistor decade box

Pre-Lab Complete the design of the Zener diode shunt regulator in Fig. 1 (determine the largest 5% standard value which can be used for R1). It must operate satisfactorily over a load current range of 0 to 10 mA using a supply voltage of 12 V. The output voltage is expected to have a nominal value of 6.8 V. Procedure The 12-V supply in the following procedure is a laboratory supply capable of 200 mA of output current. Be sure to set its current limiter for at least this amount. 1. Set up the circuit of Fig. 1 using the standard value that you calculated for R1 in the pre-lab. Use a resistor decade box as the "load resistor" RLOAD. Insert a milliammeter as shown to monitor the load current. Measure the load voltage at light-load (ILOAD = 1 mA), and at full-load (ILOAD = 10 mA). 2. Measure the output voltage/current pairs with various values of load resistance. Use output currents ranging from zero to well beyond the point where the regulator "drops out of regulation." Collect enough data to sketch a map of the regulator performance on the VLOAD vs. ILOAD plane (put VLOAD on the vertical axis, and ILOAD on the horizontal). The expected result is that the regulator will maintain the output voltage almost-constant with regard to load current up to the "dropout current:" the output voltage will then fall rapidly with further increase in load current. 3. Set up the circuit of Fig. 2 and adjust it for an output voltage of 5.0 V at no-load. Measure the output voltage and current with load resistors of 500 Ω and 50 Ω. 4. Operate the voltage regulator for several minutes with a 50-Ω load and feel Q2. (Is it getting warm?)

39

Voltage Regulators Report 1. Include and discuss your design calculations for the Zener diode voltage regulator of Fig. 1. 2. Describe the range of output current over which Fig. 1 operates satisfactorily. Why does it "drop out of regulation?" 3. Find the experimentally-measured dynamic output resistance of each regulator in the following manner:

ROUT =

VLOAD ILOAD

=

VLOAD,1 − VLOAD,2 ILOAD,1 − ILOAD,2

4. Use PSpice to estimate the output resistance of Figs. 1 and 2. Use ac simulation and measure the resistance at midband (about 1 kHz). Include a 680-Ω load resistor in Fig. 1, and a 50−Ω load resistor in Fig. 2. Model Z1 using a 1N750-series Zener diode, but edit the breakdown voltage parameter to: (BV=6.8V). Model Q2 with a transistor having its SPICE parameters set to: (IS=1E-14 BF=100 VAF=50V). Compare the SPICE results with the experimentally-measured output resistances. 5. Use PSpice to determine the range of output current over which Fig. 2 operates satisfactorily. Put a dc current source in place of the load resistor, and use a dc sweep to plot the load voltage vs. the load current. (Truncate any data beyond the point at which the load voltage is reduced to zero.) What is the maximum useful load current according to this simulation? Calculate the power dissipation in Q2, and its junction temperature for this amount of load current.

Background - Zener Shunt Regulator The Zener diode shunt regulator is treated in detail by most electronics texts. For the purposes of the pre lab design, it is sufficient to treat the diode as an ideal 6.8-V Zener. The design problem is to pick R1 such that some amount of reverse current will flow in the Zener diode under all normal load conditions. Here, worst case is at maximum load current. A calculation at maximum load current produces the maximum feasible value for R1, which then must be rounded downward to the nearest available standard value. The student version of PSpice includes a 1N750-series Zener diode model - if it is not the one you need, modify the library model to include "BV = 6.8." (This sets the reverse breakdown voltage of the diode.) Background - Series-Pass Voltage Regulator The voltage regulator in Fig. 2 is an application of series-shunt negative feedback. Resistors R5 and R4, together with Z1, form an adjustable "input voltage" to a voltage amplifier programmed for a gain of +1. The load is the external circuitry to which the voltage regulator is 40

Voltage Regulators

Fig. 1 Zener diode shunt regulator. Calculate the maximum standard value which can be used for R1.

Fig. 2 Adjustable voltage regulator.

MJE 371

Fig. 3 Transistor package outlines. 41

Voltage Regulators feeding power. (Nowadays, almost all electronic circuitry is fed from a voltage-regulated power supply.) Note that the +12-V supply is the energy source which runs the whole system; it is not usually a regulated source. One of the key specifications of a voltage regulator is its dynamic output resistance, which indicates its ability to maintain a constant output voltage even as the load current varies. This can be predicted theoretically by the same methods used to calculate the output resistance of any shunt-sensing feedback amplifier. Transistor Q2 is called a "series-pass transistor." This is because the main load current is carried by Q2; the collector-emitter voltage drop on Q2 is equal to the difference between the supply voltage (+12 V) and the load voltage. In general, Q2 dissipates a lot of heat, and thus gets hot. The junction temperature of Q2 may be estimated by using a simplified heat-flow model which makes the temperature drop between two locations directly proportional to the amount of heat flowing from one to the other. (Note the analogy to Ohm's law.) For the MJE 371, which is in a TO 225 package, mounted in free air, the "thermal resistance" between the junction and the ambient air is approximately 83 C/W. The maximum safe junction temperature for the long-term survival of this semiconductor is rated by the manufacturer at 150 C. The heat dissipated in the junction is calculated by P DISS = V CE $ I C (watts). Therefore, assuming a laboratory ambient temperature of 25 C, the junction temperature is estimated by: T J = P DISS $ (83 C/W ) + 25 C . The junction temperature of Q2 defines the maximum load current that this regulator can safely deliver.

42

Experiment 12 Wien Bridge Oscillator Introduction The Wien bridge oscillator will be used to demonstrate the effects of positive feedback, and the Barkhausen criterion for oscillation. Negative feedback is also used to stabilize the transfer characteristics of the amplifier used by this oscillator. Equipment Needed y

Normal laboratory equipment

y

PN2222A npn transistor (alternate: 2N4401)

y

PN2907A pnp transistor (alternate: 2N4403)

Pre Lab Read the appropriate section(s) of your electronics text dealing with the "Barkhausen criterion" or "quasi-linear sinusoidal" oscillators. Procedure V out

1.

Construct the amplifier of Fig. 1. Measure its voltage gain V in at 1 kHz. Verify that the amplifier is non-inverting, and that trim pot R4 adjusts its voltage gain from something less than +3 to something more than +3. Use the 100-K series resistor together with the function generator (FG) to measure the amplifier input resistance Rin . (The expected value is about 180 KΩ.)

2.

Add the frequency-selective feedback network to the amplifier as shown in Fig. 2. Use the capacitor value given for C on Fig. 2, unless otherwise instructed. Initially, wire the circuit as indicated by the "TEST" position of the switch. Set the FG for a 1 sine wave at the frequency f o = 2RC and monitor Vout and the FG signal using the two-channel scope. Monitor the phase shift. (Hint: A phase measurement is available on the DSO "Measure Time" menu.) Vary the FG frequency about f o until you find the frequency at which the phase is zero.

3.

Remove the FG, and wire Fig. 2 as indicated by the "OSCILLATE" position of the switch. Adjust trim pot R4 until the circuit breaks into oscillation. Adjust R4 to produce the minimum amplifier gain which maintains oscillation. Study the effects of a slight decrease or increase of the amplifier gain about the borderline value which just barely sustains oscillation. Measure the frequency of oscillation.

4.

Do not change the setting on R4. Remove the frequency-selective feedback network, V out and measure the amplifier gain V in as done previously in Fig. 1.

43

Wien Bridge Oscillator Report 1.

Review the Barkhausen criterion for oscillation.

2.

Derive the transfer function V i (s ) of Fig. 3, the frequency-selective feedback network. Calculate the magnitude and the phase of this function at the frequency 1 f o = 2RC .

3.

Calculate the amplifier gain required for oscillation at f o . Compare this with your laboratory observations.

4.

Run a series of several PSpice simulations of the complete oscillator circuit. Use a transient simulation, and parametrically step the total resistance RE = R3+R4 from 1.2 KΩ to 1.6 KΩ in 100-Ω steps. Set the simulation run time at 50 ms with a maximum step size of 0.1 ms. Do not omit the initial transient solution. Observe the start-up process for the oscillator, and comment on it in your report.

V o (s )

44

Wien Bridge Oscillator

Fig.1 Voltage amplifier with series-shunt feedback.

Fig. 2 Completed oscillator circuit using amplifier from above.

Fig. 3 Frequency-selective feedback network.

45

Wien Bridge Oscillator

46

Experiment 13 Analog/Digital Conversion Introduction Most digital signal processing systems are interfaced to the analog world through analog-to-digital converters (A/D) and digital-to-analog converters (D/A). The purpose of this experiment is to observe how the conversion process modifies the signal. A circuit board having separate sample-and-hold (S/H), A/D and D/A sections is provided for this experiment. It allows easy access to the signals at each stage of these conversion processes. Equipment Needed y

Digital Scope with event averaging capability

y

Function generator

y

Analog/digital conversion circuit board

Pre Lab Read the appropriate section(s) of your electronics text dealing with A/D and D/A conversion, as well as S/H circuits. Procedure

1

1.

Connect the analog/digital conversion circuit board as shown in Fig. 1. Be sure to observe correct polarity in connecting the +/- 15-V power supplies. The function generator and oscilloscope ground leads should be connected to "analog ground." The power supply common lead is connected to "digital ground." Set the FG for a dc output1 voltage of 0 V. Connect the scope channel 1 to the analog input (to the A/D converter), and channel 2 to the analog output (from the D/A converter).

2.

Vary the dc voltage at the analog input slowly from 0 V to 5 V. The eight LEDs indicate the digital value of the converted analog input voltage. The 8-bit byte should vary from 00h to FFh . Determine what happens when the analog input voltage goes below zero, or above 5 V. Using an increment of 1 mV in the analog voltage, carefully determine the voltage change (to the nearest 1 mV) required to produce a 1-bit change in the digital output. This is the "quantization step size."

3.

Use a dc voltmeter connected between "analog ground" and "VREF" to measure the internal reference voltage of the A/D and D/A converters. The result should be 5 V, plus or minus 5%. Divide VREF by (28 -1) and compare with the quantization step size measured in step 2. These two results should be equal.

To obtain dc output from the HP 33120A, press and hold the buttons for two waveforms, such as sine and triangle, simultaneously for several seconds. 47

Analog/Digital Conversion 4.

Set the FG for a 100-mVpp 50-Hz triangle wave with a 100-mV dc offset2. Connect channel 1 of the scope to show this analog input waveform, and connect channel 2 to show the output voltage of the S/H stage, labeled "S/H OUT." Trigger from channel 1. You will need to use event averaging to obtain a low-noise display at 50 mV/div. Record this display which documents the relationship between the low-frequency input signal and a sampled version of it.

5.

Keep the same setup as the previous step, except move channel 2 to the "analog output." This output shows the result of digitizing the sampled signal, and then converting it back to analog form. Record this display which documents the relationship between the low-frequency input signal and a sampled and quantized version of it. Use this display to measure the quantization step size.

6.

Measure the frequency of the sampling-and-conversion clock signal labeled "CONV. CLK." This is the sampling frequency.

7.

Set the FG for a 5-Vpp 500-Hz sine wave with a 2.5-V dc offset. View the input signal on channel 1, and the sampled signal (S/H OUT) on channel 2. Be sure to trigger the scope from channel 1. View the results both with and without event averaging (8 averages is fine). The normally-acquired waveforms should clearly show the effects of the sampling process on the signal. Record two sets off waveforms, one event-averaged and the other without event averaging.

8.

With the event averaging turned off, slowly change the frequency of the sine wave by +/- 10 Hz using 1-Hz increments. Your scope display should be showing signal components at 500 Hz, and signal components at the sampling frequency (≅ 7 kHz). These two frequencies could be commensurate (having an integer-ratio relationship), or incommensurate. As you change the signal frequency slightly, observe what happens when the two frequencies involved become commensurate. Record your written comments.

9.

Set the scope time base for 1 ms/div, and change the triggering source to channel 2 with HF reject on. Channel 2 is still connected to the analog output. Increase the frequency of the sine wave input from 0.5 kHz to 22 kHz, going in 0.1 kHz steps. Observe what happens as you pass through the frequencies fS, 2 fS, and 3 fS. Record your written comments.

1.

Discuss the meaning of "quantization step size." Give its numerical value for this A/D converter as measured in steps 2 and 3. Label your waveforms recorded in step

Report

2

Remember that the actual output voltage amplitude will not agree with the programmed value unless the output termination is set to "High Z." 48

Analog/Digital Conversion

Fig. 1 Top view of analog/digital conversion experiment circuit board. Observe polarity when connecting the +/- 15-V power supplies. 5 to show where the quantization step size can be measured from these results. 2. 3.

49

Analog/Digital Conversion

50

Data Sheets

The following data sheets are included with this lab manual: Part Number PN2222A MJE371 LM741

Brief Description (see data sheet) npn BJT: small signal, 40 V, 1 A, 625 mW, TO-92 case, complement to PN2907A pnp BJT: power, 40 V, 4 A, 4 W, TO-225AA case, complement to MJE521 Operational Amplifier: GBW=1 MHz, SR=0.5 V/μs, Voff