ELE8930 Lab 5 - Circuits with Memory

Algonquin College Of Applied Arts and Technology ELE8930 Lab 5 - Circuits with Memory Part 1: The RS Latch Objectives: To wire and observe the opera...
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Algonquin College Of Applied Arts and Technology

ELE8930 Lab 5 - Circuits with Memory Part 1: The RS Latch Objectives:

To wire and observe the operation of an RS latch.

Equipment: 7400 2-input BUBBLE-OR (NAND) gate IC and one 7404 inverter IC to drive LEDs. Procedure: 1. Use two 2-input BUBBLE-OR gates from a 7400 IC to wire the latch circuit shown on the schematic of Figure 1. Note: A BUBBLE-OR DeMorgan representation is used here (instead of a NAND) to show that the nSet and nReset inputs are active-low. 1 2

Switch 0: nSet

Switch 1: nReset

4 5

7400 3

Q

(Connect to an inverter that drives a Green LED)

Q

(Connect to an inverter that drives a Red LED)

7400 6 Figure 1

2. Connect the nSet and nReset inputs to two switches. The intent here is to show that the above circuit has memory. The latch circuit will remember which switch has been activated last. Please remember that the switches are active-low and that they are therefore active when they are closed. 3. Connect both Q outputs to 7404 inverters to drive LEDs that will allow you to easily see the state of the Q outputs. 4. Follow the procedure outlined below to prove that the circuit has memory. a) Open both switches to apply inactive logic 1’s to the nSet and nReset inputs. b) Close the Switch 0 and reopen it. The Q output is in the logic state: __________ (1 or 0) c) Close the Switch 1 and reopen it. The Q output is in the logic state: __________ (1 or 0) Although the above procedure returns both switches to their inactive position, the circuit will remember which switch was closed last. 5. What happens if both switches become active at the same time? Try it and note the state of the Q outputs. You may then return both switches to their inactive position. Describe what determines the state of the Q outputs when the switches are returned to their inactive position? ________________________________________________________________________________ ________________________________________________________________________________ ________________________________________________________________________________

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Algonquin College Of Applied Arts and Technology

6. Although you don't need to build the latch circuit schematic shown on Figure 2, analyze it and explain how its functionality differs from the circuit that you built and studied in the first 5 steps of the procedure. 1 2

Reset

Set

4 5

7402 3

Q

7402 6

Q

Figure 2

The above latch circuit is different from the previous Bubble-OR latch circuit because_____ ________________________________________________________________________________ ________________________________________________________________________________ _________________________________________________________________________ INSTRUCTORS INITIALS: ________

Part 2 - The D Flip-Flop Objectives: To wire and observe the operation of a clocked (edge-triggered) flip-flop. Equipment: 7474 flip-flop IC and one 7404 inverter IC to drive LEDs. 555 Timer circuit from Lab 1 Note: It is important to verify that the 555 Timer IC is a TLC 555 CMOS version of the timer. For this lab you must NOT use an NE555 version. Procedure: 1. Refer to the schematic shown on Figure 3 below and assemble the circuit. The resistors of your TLC 555 timer circuit should be modified to produce a timer frequency which is roughly 2 Hz. Refer to the IC diagram at right and ensure that the 7474 IC is properly powered up. Note that this edge-triggered flip-flop will record the D-input on rising edges of the clock. Switch 0 Switch 2 TLC555 Timer Circuit

1 2

Clr 5 D Q

3

Clk 6 Q Pr

7474 Switch 1

7474

(Connect to an inverter that drives a Green LED) (Connect to an inverter that drives a Red LED)

4 Figure 3

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Algonquin College Of Applied Arts and Technology

2. Note that the Clr and Pr inputs are active-low. It is important to set those two inputs inactive by ensuring that both switches 0 and 1 are open. Close switch 2 to input a logic 0 to the D input. Wait at least two seconds and then open switch 2. Did you notice what happened to the LEDs after you opened switch 2? You may want to repeat this procedure to ensure that you understand what is happening. Open switch 2 to input a logic 1 to the D input. Wait at least two seconds and then close switch 2. Did you notice what happened to the LEDs after you closed switch 2? Again you may want to repeat this procedure to ensure that you understand what is happening. Complete the following sentence:

The Q output will only reflect the state of the D input when_______________________ _____________________________________________________________ _____________________________________________________________ 3. Disconnect switch 2 and feed the D input with the Q output as shown on Figure 4 below: Switch 0

TLC555 Timer Circuit

1 2

Clr 5 D Q

3

Clk 6 Q Pr

7474 Switch 1

(Connect to an inverter that drives a Green LED) (Connect to an inverter that drives a Red LED)

4 Figure 4

Briefly explain why the LEDs are behaving this way. ________________________________________________________________________________ ________________________________________________________________________________ ________________________________________________________________________________ 4. Keep the circuit of part 3, close switch 0 and observe the result at the LEDs. Open switch 0, close switch 1 and observe the results at the LEDs. If you compare the Clk, Clr and Pr inputs how do they relate with respect to priority? ________________________________________________________________________________ ________________________________________________________________________________ _________________________________________________________________________ INSTRUCTORS INITIALS: ________

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Algonquin College Of Applied Arts and Technology

Part 3 - Counters Objectives:

To wire and observe the operation of a counter.

Equipment: 74193 counter, 7400 (NAND) and one 7404 inverter IC to drive LEDs. 555 Timer circuit from Lab 1 Note: It is important to verify that the 555 Timer IC is a TLC 555 CMOS version of the timer. For this lab you must NOT use an NE555 version. Procedure: 1. Examine the specifications of the 74193 on the next page. Install the 74193 on your protoboard and connect its power inputs to Vcc and GND. 2. Tie the “Clear” (MR) input and the “Load” ( PL )inputs inactive by connecting them to GND and Vcc respectively. 3. Connect each of the Q outputs (Q0, Q1, Q2 and Q3) to an inverter that drives a LED so that you can easily observe the state of each of the four Q outputs. 4. Tie the “Count Down” (CPD) input to Vcc to keep it inactive. Binary Sequence Hexadecimal Value Set the TLC555 time clock resistors to get Q3 Q2 Q1 Q0 0 through F approximately 1 Hz and apply this clock to the “Count Up” (CPU) input. Use the table at right to note the binary sequence at the output. 5. Disconnect the CPD from Vcc. Use the 7400 (NAND) IC and one leftover inverter to build the following selector circuit. This circuit will allow you to steer an inverted version of the TLC555 clock either to the CPU or to the CPD input of the 74193. 1 Select 3 To CPU 2

7400

TLC555 Clock

4 5 7404

6

To CPD

7400

Describe the count sequence when the select input is connected to Vcc and then to GND? ____________________________________ ____________________________________ ____________________________________ ____________________________________________________________________ ____________________________________________________________________ INSTRUCTORS INITIALS: ________

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Algonquin College Of Applied Arts and Technology 74193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The 74193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flipflops clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a LOW-to-HIGH level transition (rising edge) of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held HIGH. The counter is fully programmable which means that each output may be preset to either level by entering the desired data at the inputs while the load input is active-low. The output will change independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. An active-high clear input has been provided which forces all outputs to the low level independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, etc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up and down counting functions. The borrow output produces a pulse equal in width to the count down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists. Features - Fully independent clear input - Synchronous operation - Cascading circuitry provided internally - Individual preset each flip-flop

Note A: Clear overrides load, data, and count inputs Note B: When counting up, count-down input must be HIGH; when counting down, count-up input must be HIGH.

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