ECE 212-001 and -002 Homework Assignment #2

1) Do the actions below for each equation: a. f(a,b,c) = (a XOR b) (a XOR c') b. f(a,b,c) = (a + b) (a + c') (b + c') c. f(a,b,c) = ab'(b + c) + (a' (b' + c) + a c') b Note: XOR is the "exclusive-OR" function. A XOR B = AB' + A'B (produces 1 if either A is 1 or B is 1, but not if both are 1). • • • • • • •

Draw the logic circuit diagram that directly implements the function (i.e., OR and AND gates should match sum and product terms in the original equation). Construct the truth table. From the truth table, rewrite the equation in canonical sum-of-products (SOP) form, and then use shorthand SOP notation. From the canonical SOP, draw the circuit diagram with only NAND gates. From the truth table, rewrite the equation in canonical product-of-sums (POS) form, and then use shorthand POS notation. From the canonical POS, draw the circuit diagram with only NOR gates. Which circuit uses fewer gates: the canonical SOP circuit or canonical POS circuit? (Note: Do not include inverters in your gate count, i.e., assume both the uncomplemented and complemented versions of each input variable are already available.)

(a) f(a,b,c) = (a XOR b) (a XOR c') = (ab’ + a’b)(ac + a’c’) abc 000 001 010 011 100 101 110 111

f 0 0 1 0 0 1 0 0

a b' a' b f

a c a' c'

Canonical SOP: f = a’bc’ + ab’c Shorthand SOP: f = ∑a,b,c(2, 5)

a' b c'

NAND-gate circuit:

f a b' c

Canonical POS: f = (a + b + c)(a + b + c’)(a + b’ + c’)(a’ + b + c)(a’ + b’ + c)(a’ + b’ + c’) Shorthand POS: f = ∏a,b,c(0, 1, 3, 4, 6, 7) a b c

NOR-gate circuit:

a b c' a b' c'

f

a' b c a' b' c a' b' c'

SOP circuit has fewer gates (only 3 gates, compared to 7 for POS circuit). (b) f(a,b,c) = (a + b) (a + c') (b + c') abc 000 001 010 011 100 101 110 111

f 0 0 1 0 1 0 1 1

a b a f c' b c'

Canonical SOP: f = a’bc’ + ab’c’ + abc’ + abc Shorthand SOP: f = ∑a,b,c(2, 4, 6, 7) NAND-gate circuit:

a' b c' a b' c' f a b c' a b c

Canonical POS: f = (a + b + c)(a + b + c’)(a + b’ + c’)(a’ + b + c’) Shorthand POS: f = ∏a,b,c(0, 1, 3, 5) a b c

NOR-gate circuit:

a b c' f a b' c' a' b c'

SOP and POS circuits have the same number of gates. (c) f(a,b,c) = ab'(b + c) + (a' (b' + c) + a c') b

a b

b'

c

f

a' b'

b

c a c'

(Hint: Derive truth table faster by simplifying original expression into a sum-of-product form…f(a,b,c) = ab'(b + c) + (a' (b' + c) + a c') b = ab’b + ab’c + a’b(b’ + c) + abc’ = ab’c + a’bc + abc’ abc 000 001 010 011 100 101 110 111

f 0 0 0 1 0 1 1 0

Canonical SOP: f = a’bc + ab’c + abc’ Shorthand SOP: f = ∑a,b,c(3, 5, 6) NAND-gate circuit:

a' b c a b' c

f

a b c'

Canonical POS: f = (a + b + c)(a + b + c’)(a + b’ + c)(a’ + b + c)(a’ + b’ + c’) Shorthand POS: f = ∏a,b,c(0, 1, 2, 4, 7) NOR-gate circuit:

a b c a b c' a b' c

f

a' b c a' b' c'

SOP circuit has fewer gates (only 4 gates, compared to 6 for POS circuit).

2) Do the following for the circuit drawn below. • •

• •

Derive the Boolean equation corresponding to the circuit (do not simplify the expression -- sum/product terms should exactly match OR/AND gates in the circuit diagram). Simplify the Boolean equation using only switching algebra theorems (no Karnaugh Maps) -- SHOW ALL OF YOUR SIMPLIFICATION STEPS! Express the simplified equation in sum-of-product form. How many (1) AND gates and (2) OR gates are needed to implement your simplified expression? Derive the sum-of-product Boolean equation that produces the exact opposite (complement) of the circuit drawn below.

•

F = (X + Y + X’Z)(X + Y + XZ)(YZ’ + W)

•

Simplify: (XX + XY + XXZ + XY + YY + XYZ + XX’Z + X’YZ + X’ZXZ)(YZ’ + W) = (X + XY + XZ + Y + XYZ + X’YZ)(YZ’ + W) = (X(1 + Y + Z) + Y(1 + XZ + X’Z))(YZ’ + W) = (X(1) + Y(1))(YZ’ + W) = (X + Y)(YZ’ + W) = XYZ’ + WX + YZ’ + WY = YZ’(X + 1) + WX + WY = YZ’(1) + WX + WY = YZ’ + WX + WY

•

3 (2-input) AND gates, 1 (3-input) OR gate

•

F’ = (YZ’ + WX + WY)’ = ((YZ’) + (WX) + (WY))’ = (Y’ + Z)(W’ + X’)(W’ + Y’) = (Y’ + Z)(W’ + W’Y’ + W’X’ + X’Y’) = (Y’ + Z)(W’(1 + Y’ + X’) + X’Y’) = (Y’ + Z)(W’ + X’Y’) = W’Y’ + X’Y’ + W’Z + X’Y’Z = W’Y’ + W’Z + X’Y’(1 + Z) = W’Y’ + W’Z + X’Y’

3) A voting circuit makes a decision based on the majority of votes. The logic receives four inputs w, x, y, and z. Together, these input variables are the binary representation of the number of members who vote “yes” out of 15 total members. For example, wxyz = 1000 indicates that 8 members voted “yes”, wxyz = 0101 indicates that 5 members voted “yes”, and so on. The voting circuit outputs 1 if the majority of members vote “yes” out of 15 total members, and outputs 0 otherwise.

• • •

Express the voting logic function in a truth table. Express it in canonical SOP form. Using boolean algebra theorems, simplify the logic function so that it uses a minimum number of gates. (Hint: apply theorem 10)

Solution: Output 1 if number of “yes” votes is greater than or equal to 8 (a majority), i.e., 1000 through 1111. Truth Table: wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Canonical SOP form: f = WX’Y’Z’ + WX’Y’Z + WX’YZ’ + WX’YZ + WXY’Z’ + WXY’Z + WXYZ’ + WXYZ Simplify: f = (WX’Y’Z’ + WX’Y’Z) + (WX’YZ’ + WX’YZ) + (WXY’Z’ + WXY’Z) + (WXYZ’ + WXYZ) = WX’Y’(Z’ + Z) + WX’Y(Z’ + Z) + WXY’(Z’ + Z) + WXY(Z’ + Z) = (WX’Y’ + WX’Y) + (WXY’ + WXY) = WX’(Y’ + Y) + WX(Y’ + Y) = (WX’ + WX) = W(X’ + X) f = W 4) A parity circuit determines the parity of a 3-bit input x, y, and z. “Odd parity” means there is an odd number of 1’s in the 3-bit input (x,y,z), and “even parity” means there is an even number of 1’s in the 3-bit input (x,y,z). The parity circuit outputs 1 if the 3-bit input (x,y,z) contains an odd number of 1’s. •

Express the parity logic function in a truth table.

• •

Express it in canonical SOP form. Using boolean algebra theorems, simplify the logic function so that it uses a minimum number of gates.

Truth Table: xyz 000 001 010 011 100 101 110 111

f 0 1 1 0 1 0 0 1

Canonical SOP form: f = x’y’z + x’yz’ + xy’z’ + xyz Simplify: cannot be simplified further

5) Simplify the following expressions using only boolean algebra (show all your steps for credit). a. f(a,b,c) = (a XOR b) (a XOR c') f

= = =

(ab’ + a’b)(ac + a’c’) ab’ac + ab’a’c’ + a’bac + a’ba’c’ ab’c + a’bc’

b. f(a,b,c) = (a + b) (a + c') (b + c') f

= = = = =

(a + ac’ + ab + bc’)(b + c’) (a(1 + c’ + b) + bc’)(b + c’) (a + bc’)(b + c’) ab + ac’ + bc’ + bc’ ab + ac’ + bc’

c. f(a,b,c) = ab' (b+c) + [a' (b' + c) + ac'] b

f

= ab'b + ab'c + a'b(b'+c) + abc' = ab'c + a'bb' + a'bc + abc = ab'c + a'bc + abc'

6) Apply DeMorgan's theorem to find the inverse function f ', showing your intermediate steps. a. f(a,b,c) = (a XOR b) (a XOR c') f’ = = =

[ ((ab’) + (a’b)) ((ac) + (a’c’)) ]’ ((a’ + b)(a + b’)) + ((a’ + c’)(a + c)) (a’ + b)(a + b’) + (a’ + c’)(a + c)

(Note: May also simplify f first, then apply DeMorgan’s Theorem on simplified f.) b. f(a,b,c) = (a + b) (a + c') (b + c') f’ = = =

[ (a + b)(a + c’)(b + c’) ]’ (a’b’) + (a’c) + (b’c) a’b’ + a’c + b’c

c. f(a,b,c) = ab'(b + c) + (a' (b' + c) + a c') b f’ = = = =

[ ab’(b + c) + (a’(b’ + c) + ac’)b ]’ [ (ab’(b + c)) + (((a’(b’ + c)) + (ac’))b) ]’ (a’ + b + (b’c’)) (((a + (bc’))(a’ + c)) + b’) (a’ + b + b’c’) ((a + bc’)(a’ + c) + b’)

(Note: May also simplify f first, then apply DeMorgan’s Theorem on simplified f.)