E3 237 Integrated Circuits for Wireless Communication
Lecture 3: Advanced RF CMOS
Gaurab Banerjee Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore
[email protected]
Outline
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0.13 um RF CMOS Components
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An advanced RF-CMOS process
Resistors: Based on Diffusion
N-well resistance (about 400 Ohms/sq)
Diffusion resistance (about 10 Ohms/sq, salicided. 100-200 Ohms/sq, un-salicided) •
N-well and diffusion based resistors are characterized by large parasitics
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Salicide lowers resistance, good for MOS devices, bad for resistors
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Salicide blocking is expensive, some processes still do it for specialized poly-resistors.
Resistors: Based on poly-silicon
N+/P+ poly - sheet resistance (about 10 Ohms/sq)
Salicide-blocked poly resistance (about 200 Ohms/sq) •
Low parasitic capacitance, better than diffusion based resistors
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Some processes customize the poly sheet resistance with salicide blocking – very expensive!
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Interconnect resistance ( about 100 mOhm/square) and vias can add series resistance
Resistors: Based on MOS Device
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Device biased in triode –> bias dependent resistor –> nonlinear and PVT variation sensitive
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Large Parasitic capacitance
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Large resistance – mega-ohms in tens of square microns
Resistors: Equivalent Circuit Model
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Series inductor at high frequencies – meander to reduce impact
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Parasitic capacitance to substrate with dielectric losses
MOS Capacitor
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Offers the highest capacitance per unit area – 10 fF/ sq. micron
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Channel length adds series resistance – needs to be minimized for high Q
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Can be used as a varactor in tuning circuits -> careful, not linear!
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Requires device to be kept in strong inversion
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Often used in accumulation mode – n+ diffusion in n well, to avoid keeping the device in strong inversion. The other plate is still the gate.
Metal Capacitors
Lateral Flux Capacitor Metal-Insulator-Metal (MIM) capacitor is like this with special dielectric layer (usually on top of BEOL stack)
Stacked and Inter-digitated Metal-Oxide-Metal (MOM) capacitor is like this with whatever insulator is available in BEOL stack
Aparacio et al, “Capacity limits and Matching Properties of integrated capacitors ”, JSSC, March 2002
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MOM capacitance per unit area – 1.5-2 fF/ sq. micron
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High Q and very linear.
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Symmetric parasitic capacitance – about 10% of total capacitance
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Accuracy determined by lithography – usually better than 10%
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Use arrayed unit cells to improve matching.
Capacitors: Equivalent Circuit Model
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“Lead” inductance and resistance
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Parasitic capacitance to substrate with dielectric losses – sometimes known as “cap-to-ground” or “bottom plate capacitance”.
Integrated Spiral Inductors
1-turn with underpass
multi-turn, multi-crossover, with center-tap •
Generally uses top metal layer, with or without patterned ground shield
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Typically considered parameters (L=1-10 nH, Q = 5-10, self resonance frequency = 10-30 GHz )
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Width, length and area over substrate typically determine losses
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“Hollow” inductors typically provide better Q for same L – avoid inner turns
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Several closed form expressions exist –> Start with L = µ0 n2 r, refine with field solvers
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Usually rounded inductors are slightly more efficient –> does not make a huge difference!
Inductors: Equivalent Circuit Model
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Series resistance representing metal losses (skin effect) and eddy current losses (substrate)
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Parasitic capacitance to substrate with dielectric losses
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Turn to turn and cross-over capacitance – lowers self-resonance frequency
Bond-wire Inductors
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Generally 1nH/mm (achieves 1-5 nH)
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Not well controlled, parasitic dominated
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Q much better than integrated inductors -> around 40
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Every instantiation requires a bond-pad: difficult for “internal” inductors
Integrated Transformers
A
B
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Utilizes magnetic coupling between adjacent metal layers.
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Key Parameters : L, M=Mutual inductance.
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Typically very lossy, requires tight coupling between primary and secondary.
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Almost always requires EM field-solver.
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Studies have shown that “stacked” transformers are more efficient than “planar” transformers.
Outline
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0.13 um RF CMOS Components
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An advanced RF-CMOS process
Intel’s 32-nm CMOS for RF
C. H. Jan et al. “RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC (System-on-Chip) Applications”, Int. Electron Dev. Meeting, Dec. 2010
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Performance improvement in modern CMOS processes is not driven by geometrical scaling any more.
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Advances in materials (strained silicon, high-k gate dielectric, metal gate) are now enabling high fTs, lower noise figures and better figures of merit for RFICs.
fT Scaling Trends to 32-nm
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Steady improvement in peak fT over the last few generations -> major jump from 90 to 65-nm technology.
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Strong function of current density -> Burn more current if you need high fT.
Flicker Noise Performance
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10x reduction in flicker noise from 180 nm to 32 nm technology.
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Primarily due to increase in gate capacitance, aided by improvements in dielectric materials.
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Better growth/deposition techniques for advanced processes may have a role to play.
Minimum Noise Figure Performance
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Steady improvement in NFmin over the last three technology generations.
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Trend reversal (?) between 45-nm and 32-nm technologies?
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Generally a tradeoff between improving gm (materials) and parasitics (limitations in fabrication).
Interconnect Scaling
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Primarily driven by the performance and density requirements of digital processes.
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Generally, has a negative impact due to interconnect parasitics.
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In older processes, top metals were deliberately kept thicker for power distribution and RF inductors -> This is getting limited by interconnect scaling.
Thick Metal in Advanced Processes
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One possible solution -> Add a thick metal layer at the top.
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Similar to the “redistribution layer” offered by many foundries for RF/Analog.
Key RF Device Characteristics
Next Class: Analog/RF Layout
