E Starter Kit User s Guide

ProASIC3/E Starter Kit User’s Guide ProASIC3/E Starter Kit User’s Guide Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . ...
Author: Amanda Patrick
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ProASIC3/E Starter Kit User’s Guide

ProASIC3/E Starter Kit User’s Guide

Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Document Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Document Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1 Contents and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Starter Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ProASIC3/E Starter Kit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Detailed Board Description and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PLL Parts/Usage on ProASIC3/E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Programming the ProASIC3/E Device with FlashPro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LED Device Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Switches Device Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 FPGA – OLED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 OLED Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LVDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Setup and Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing the Starter Kit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Test File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23 23 23 23

4 Test Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Description of Test Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 LVDS Signal Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Test Procedures for Board Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Test Procedure for the A3PE-STARTER-KIT-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

A PQ208 Package Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

B Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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ProASIC3/E Starter Kit User’s Guide Top-Level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ProASIC3/E Starter Kit Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

C List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

D Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

51 51 51 51 51 52

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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Introduction Thank you for purchasing the Microsemi SoC Products Group ProASIC®3/E Starter Kit. This guide provides the information required to easily evaluate ProASIC3/E devices.

Document Contents Chapter 1 – "Contents and System Requirements" describes the contents of the ProASIC3/E Starter Kit. Chapter 2 – "Hardware Components" describes the components of the ProASIC3/E Starter Kit Board. Chapter 3 – "Setup and Self Test" describes how to set up the ProASIC3/E Starter Kit Board and how to perform a self test. Chapter 4 – "Test Design" describes the existing design on the ProASIC3/E Starter Kit Board. Chapter 5 – "LVDS Signal Evaluation" explains test setup and design, reports the measurements performed on the board, and makes recommendations to increase the LVDS signal quality in order to meet the performance criteria. Chapter 6 – "Test Procedures for Board Testing" details the test procedure to be carried out at the Microsemi SoC Products Group designated manufacturer's testing facility on the ProASIC3/E Starter Kit Board with silkscreen labeling A3PE-STARTER-KIT-2 REV A. Appendix A – "PQ208 Package Connections" provides a table listing the package connections for the A3PE1500 device. Appendix B – "Board Schematics" provides illustrations of the ProASIC3/E Starter Kit Board. Appendix C – "Product Support" describes Microsemi SoC Products Group support services.

Document Assumptions This user’s guide assumes: •

You intend to use the Microsemi SoC Products Group Libero® System-on-Chip (SoC) suite.



You have installed and are familiar with Microsemi SoC Products Group Libero SoC v10.0 or later.



You are familiar with PCs and the Windows® operating system.

Additional Information Refer to the Libero SoC Quick Start Guide to get familiar with the Microsemi SoC Products Group FPGA development flow using Libero SoC.

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1 – Contents and System Requirements This chapter details the contents of the ProASIC3/E Starter Kit and lists the power supply and software system requirements.

Starter Kit Contents The Starter Kit includes the following: •

ProsASIC3/E Starter Kit Board with an A3PE1500-PQ208



Libero IDE Gold License



FlashPro4



The ProASIC3/E Starter Kit User’s Guide



Switching brick power supply (rated from 110 V to 240 V AC) from 50 Hz to 60 Hz input, providing 9 V DC output at up to 2 A, part number DTS090220U-P5P-SZ from CUI INC

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2 – Hardware Components This chapter describes the hardware components of the ProASIC3/E Starter Kit Board.

ProASIC3/E Starter Kit Board Figure 2-1 illustrates a top-level view of the ProASIC3/E Starter Kit Board. The ProASIC3/E Starter Kit Board consists of the following: •

Wall mount power supply connector, with switch and LED indicator



Switches to select from among 1.5 V, 1.8 V, 2.5 V, and 3.3 V – I/O voltages on banks 4 and 5 (southern side)



10-pin 0.1 inch pitch programming connector compatible with Altera connections



40 MHz oscillator and two independent manual clock options for global reset and pulse



Eight LEDs (driven by outputs from the device)



Jumpers (allow disconnection of all external circuitry from the FPGA)



Two mono stable pulse generator switches ("global" and "reset")



Four switches (provide input to the device)



Two hex switches to provide four inputs each to the FPGA, and which are set to a user-switchable hexadecimal input value



OLED display to facilitate detailed message outputs from the FPGA application

For further information, refer to the following appendices: Appendix A – "I/O Naming Conventions" on page 33. Appendix B – "This appendix provides illustrations of the ProASIC3/E Starter Kit Board." on page 37.

Detailed Board Description and Usage The ProASIC3/E Starter kit board has various advanced features that are covered in later sections of this chapter. This board is socketed and is populated with A3PE1500-PQ208 silicon. Any ProASIC3 device can be used, as all devices in both the ProASIC3 and ProASIC3E families are available in the PQ208 package.

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Hardware Components A block diagram of the ProASIC3/E Starter kit board is shown in Figure 2-1 and will facilitate understanding of the more detailed schematics shown in the appendix, "Board Schematics" on page 37.

Figure 2-1 • ProASIC3/E Starter Kit Board: Top-Level View Full schematics are available for download from the Microsemi SoC Products Group website. The electronic versions of the dedicated schematics can be enlarged to a far greater degree than shown in the printed version of this manual or even in the electronic version of this manual, hence the interested reader is referred to the dedicated schematics to see the appropriate level of detail.

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PLL Parts/Usage on ProASIC3/E Instructions for PLL Activation on ProASIC3/E Starter Kit Board In order to use the PLLs on the ProASIC3/E starter kit board, power must be applied to their respective analog supply rails. For the west side PLL, known as PLF, the VCCPLF line must be connected to VCC, which is held at 1.5 V. The same is true for VCCPLC of the PLL on the east side, known as PLC. In addition, the VCOMPLF and VCOMPLC lines must be connected to ground. The jumpers JP49 and JP50 are provided on the starter kit to connect VCCPLF and VCCPLC pins to 1.5 V supply. The ground pins of the PLL supplies are connected to ground on the board. These supply voltages are not connected by default on the board for three reasons: 1. The PLC analog voltage rails are not available on ProASIC3 devices; only on ProASIC3E in the PQ208 package. Only the west side PLL, namely PLF, is available on ProASIC3 devices in PQ208. In ProASIC3 devices, the pins are used as general I/Os. The same board is used for ProASIC3E and ProASIC3 devices. 2. To demonstrate the lowest possible power consumption for the part. Perpetually powering the PLL lines would not achieve that. 3. It is easy to place a jumper on the appropriate jumper header when desired.

Power Supplies A 9 V power supply is provided with the kit (Figure 2-2). There are many power supply components in the starter kit board to illustrate the many ways that differing voltage banks may be supported with ProASIC3 and ProASIC3E technology. These voltage banks are not all required for general use of ProASIC3 silicon. They are provided purely for illustrative purposes.

+9 V DC Supply 2 A Max

2.5V Regulator

D19 Red On O

SW11

3.3V Regulator

1.8V Regulator

1.5V VPUMP Regulator OLED 3.3V supply 10 V Step-up DC/DC converter

Core FPGA Voltage

OLED10 V Supply

Figure 2-2 • Power Supply Block Diagram To use the ProASIC3/E Starter Kit board with a wall mount power supply, use the switching brick power supply that is provided with the kit. The external +9 V positive center power supply provided to the board via connector J18 goes to a voltage regulator chip U11 on the Starter Kit board. As soon as the external voltage is connected to the board,

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Hardware Components the red power applied LED (the only red LED on the board) D19 illuminates to indicate that an external supply has been connected to the board. As soon as switch SW11 is moved to the ON position (to the right, as labeled on the board “OFF/ON”), the disabling ground signal is removed from pin 7 of U11 and the regulator begins to provide power at its output. The U11 switching voltage regulator provides a dedicated 3.3 V supply at its output. The board’s 3.3 V supply is used for feeding separate regulators that deliver 1.5 V (via U15), 1.8 V (via U12) and 2.5 V (via U15). The 1.5 V is required for the core voltage of the ProASIC3/E family, and the 2.5 V is required for demonstrating LVDS extended I/O bank capability. The presence of these voltages is indicated by four green LEDs (D13, D9, D10, and D11) illuminating at the top right of the board. Each LED is labeled with the voltage it represents and its component identifier. All four voltages are selectable on the I/O banks 4 and 5 (the two southernmost banks) of a ProASIC3E device using SW9 and SW8 switches respectively. Note: Only ProASIC3E devices have 8 I/O banks. ProASIC3 devices have four I/O banks—one per side of the PQ208 package. If a ProASIC3 device is placed in the socket then both SW8 and SW9 should be set at same voltage level to power I/O bank 2. The 3.3 V supply is also used for optionally providing the VPUMP programming voltage. This VPUMP voltage may be provided to the chip during programming by applying a FlashPro4 programmer to the J1 interface and selecting VPUMP from the FlashPro v9.1 (or later) programming software. VPUMP voltage may also be provided directly to the chip from the board. Simply leave the JP48 jumper in place to apply the 3.3 V supply to the VPUMP pin (106 of the PQ208 packaged FPGA). Note that if both FlashPro4 or latest and the board are selected to provide VPUMP, then it is the connection on the board that will override, as FlashPro4 will detect that a voltage is available, issue an information message in the programming software, and then move the VPUMP output pin to a tristate value, allowing the board to provide all the power. The board must be powered-up during programming because the chip needs its core voltages to be provided and VJTAG must be detected by the FlashPro4 programmer in order for it to set its JTAG signal voltages to the right level. The OLED device requires low current 10 V supply and 3.3 V supply to operate correctly. These voltages are provided by LT1615 and LM2678S modules as shown in Figure B-5 on page 42. The external +9 V power supply is rated at 2 A maximum. On the first of the full-page dedicated schematics shown in the appendix "Board Schematics" on page 37, note that the 3.3 V supply is rated at 5 A maximum. The derived power supplies of 1.5 V, 1.8 V, and 2.5 V are rated at 2 A max each, and the OLED 10 V power supply is rated at 100 mA, as shown in Figure B-5 on page 42. Clearly, not all these derived supplies can be working at their respective maximum current outputs simultaneously. The maximum ratings are for the individual regulator ICs and cannot be numerically added together. The U11 (LM2678S-3.3) component is rated for an input voltage range of +8 V to +40 V, so a wide range of power supplies may be used with the board with no concern about over-voltage conditions occurring from inadvertent accidental usage of the wrong power supply. However, the user should take care to ensure that the voltage provided is positive at the center pin of the J18 connector and grounded on the outside. Greater heating of the regulator chips will be observed with higher voltages. It is therefore recommended that only the included power supply or an equivalent substitute be used with the Starter Kit. The included power supply has been rated for this board, including Microsemi SoC Products Group daughter cards that may be attached to the board.

Daughter Card Power Supply Connections Limited power to a daughter card may be supplied by the board. The connector for the daughter card is shown in Figure B-7 on page 44 and is the J12 header. All the FPGA voltages of 1.5 V, 1.8 V, 2.5 V, and 3.3 V are provided to the daughter card via a 12-pin 0.1 inch pitch connector. The voltages are arranged with a no-connection pin interspersing the voltage pins. This prevents accidental use of a jumper to short a supply rail to ground, which could connect differing supply rails together. The purpose is not to protect the power supply regulators, as these will go high-impedance when an over-voltage condition is detected. It is to protect the FPGA from unintentional application of a higher voltage to the 1.5 V core. Three of the twelve pins are ground pins, which will provide more than sufficient current return capability for future Microsemi SoC Products Group daughter cards that will work with this board.

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Power Supplies and Chaining Boards Together There is a special note on "VPUMP Connections When Chaining Boards Together" on page 14. Instructions are detailed here but the novice reader is advised to return to this section after reading the section on standard JTAG programming connections via FlashPro4. When joining multiple ProASIC3/E starter kit boards together via the chain programming connection, bear in mind that the J2 connector is used to connect to the J1 connector of the next board in the chain by attaching a standard 0.100-inch pitch 10-pin programming cable. The length of the cable does need to be kept as short as possible, because multiple boards connected to form a JTAG chain of ProASIC3/E devices will provide much greater noise pick-up and may degrade the TCK clock for devices remote from the FlashPro4 programmer. A rotary switch SW10 is provided on the board to set the VJTAG supply. User can select the VJTAG supply between 1.5 V, 1.8 V, 2.5 V and 3.3 V using SW10. Set VJTAG at an absolute minimum of 1.8 V to help with signal integrity when chaining boards together. Higher voltages will give better noise and impedance mismatch immunity. Disconnect the jumper at JP10 on all boards. This jumper can be used to provide VJTAG to a downstream board or to some element in the design that you wish to supply with the VJTAG voltage used by the ProASIC3/E component. The shunt that is normally in this location can be safely stored across pins 11 and 12, or 9 and 10 of the J12 daughter card power supply connector. For particularly long chains, the value of TCK used during programming should be reduced. During its development, various revisions of the ProASIC3/E Starter Kit board have been produced. This documentation contains additional text that documents some of these earlier versions, as well as the newest version of the board. The latest version of the board (A3PE-STARTER-KIT-2 REV A) is same as A3PE-PROTO-KIT except the LCD display is replaced with an OLED display and all the components are RoHS compliant. Schematics for Rev3 and Rev2 boards are the same when viewed as PDF files, but there is a short in the board layers on the Rev2 that has been corrected for Rev3. The rare Rev1 prototype boards had different schematics and are not discussed in this document.

Procedure for Starter Kit Boards To determine if the board is a Starter Kit Rev A board: A ProASIC3/E Starter Kit Rev A Board is recognized by examining the front of the board and looking for the part number just beneath the large Microsemi corporate logo on the board top silk-screen. The part number will be A3PE-STARTER-KIT-2 followed by REV A.

To chain Starter Kit Rev A boards together: All boards from the board nearest the FlashPro4 programmer should have the shunt that is placed by default on pins 3 and 4 of the J5 header moved to connect pins 1 and 2. On the board and schematic this is labeled quite clearly as CHAIN (pins 1 and 2) and LAST DEVICE (DEFAULT) (pins 3 and 4). Only the very last board in the chain should have the shunt remaining across pins 3 and 4 of the J5 connector. Note that if there is only one board in the chain then it, by definition, is the last board and should have the shunt at J5 connecting pins 3 and 4. This is why this position is labeled as the DEFAULT position for a typical customer with a single starter kit board.

Procedure for Rev3 Boards To determine if the board is a Rev3 board: A Rev3 Board is recognized by examining the front of the board and looking for the part number just beneath the large Microsemi SoC Products Group corporate logo on the board top silk-screen. The part number will be A3PE-A3P-EVAL-BRD1 followed by REV3.

To chain Rev3 boards together: Treat it as Starter Kit Rev A board in the previous section.

Procedure for Rev2 Boards, With and Without Rework To determine if the board is a Rev2 board: A Rev2 board is indicated by a red power LED in the upper right corner of the board and a part number underneath the Microsemi SoC Products Group corporate logo on the board top silk-screen. The part number will be A3PE-A3P-EVAL-BRD1. No additional text will follow the board number. If the board has been reworked to force it to become equivalent to a Rev3 board, it will contain a green wire on the top side of the board. If it does not contain green wire, it is an original Rev2.

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To chain Rev2 boards together: If reworked, treat it as Rev3 in the previous section. If not reworked, then chaining of the boards cannot be done. The shunt on J5 must be removed for any programming to take place.

Procedure for Rev1 Boards To determine if the board is a Rev1 board: A Rev1 Board is indicated by no red power LED in the upper right corner of the board. The part number on the board top silk-screen is A3PE-EVAL-BRD600. Note: Rev1 boards should not be used with this user’s guide or with design files included with this Starter Kit as the schematics are incompatible with current commercial boards.

VPUMP Connections When Chaining Boards Together When these boards are connected via a connection from J2 of one board to J1 of another board, VPUMP will be connected from one board to another. When powering on one board with a connector in place, notice that the 1.5 V, 1.8 V, 2.5 V, and 3.3 V LEDs will light on the board to which no power has been applied. The FPGA on that board, if it is programmed, will start operating. This is clearly an inappropriate situation for a large chain of boards. This is caused by having the JP48 connector for supplying VPUMP from the board connected on other boards in the chain, as VPUMP is itself connected to the 3.3 V supply output that is used to generate the other FPGA voltages on a board. To prevent VPUMP from being used as the source of a 3.3 V supply, you should remove the shunt that is in place on the JP48 connector to force JP48 to be open-circuit. To prevent loss of the shunt, it may be safely stored on the J12 header for the daughter card power supply as it is impossible to cause a short by joining any adjacent pins.

Programming the ProASIC3/E Device with FlashPro The base board used for all ProASIC3/E starter kits is the A3PE-A3P-EVAL-BRD1. The A3PE-STARTER-KIT-2 REV A and A3PE-PROTO-KIT boards are socketed and are populated with A3PE1500 silicon. Any device in the ProASIC3/E family in the PQ208 package may be placed into the socket. In a kit with a socket on the board, a reasonable number of insertions may be made if the user exercises great care in inserting components into the socket. Note that screw-down sockets are not clam shell sockets, and do have a lifetime of about 20 insertions, although far greater may be achieved with careful placement and use of a torque-limiting screwdriver. Placement of the FPGA in the socket is critical, to ensure all pins are correctly connected.

Connecting the FlashPro4 Programmer to the Board Connect the FlashPro4 programmer to your computer via the USB cable. Follow the instructions in the User’s Guide with FlashPro v9.1 (or later) software for installing the software and connecting to FlashPro4. The amber (yellow) power LED on the FlashPro4 should be illuminated at this stage. If it is not, recheck the procedure in the FlashPro User’s Guide until you obtain a steady amber (yellow) power LED illumination. Make sure the board power switch SW11 is in the OFF position and only the red board external power LED is illuminated on the board. Connect the FlashPro4 programmer to the board via the 10-pin programming cable supplied with the FlashPro4 programmer hardware. The connector to use on the board is labeled FP and is the lower J1 shrouded and keyed header. The pin 1 location on the cable indicated by the red ribbon running along the side of the cable will be on the left side as it enters into the board. After connecting the FlashPro4 programmer, select Analyze Chain from the File menu in the FlashPro software. If all is well, the appropriate device ID for the ProASIC3 or ProASIC3E part will show in the software display on the PC. If you suspect a JTAG communication issue, try changing the VJTAG voltage. For overcoming noise, higher values usually work better, but all values should work with the supplied programming cable (6 inches in length) with connection to just one board.

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Programming or Re-Programming the Example Design Download the latest version of the ProASIC3/E starter kit example design from the Microsemi website: www.microsemi.com/soc/products/hardware/devkits_boards/proasic3_starter.aspx. Using FlashPro software, program the example design on ProASIC3/E device.

Jumpers for Isolating Switches and LEDs from FPGA Many jumpers are provided on the board to allow the user to disconnect various switch combinations or LEDs from the FPGA I/O banks. All such jumpers are shown in the schematic in Figure B-1 on page 38 and are labeled on the top-layer silkscreen as JP* where * is a number. All jumpers are also labeled with the FPGA I/O pin number to which they are connected; e.g., JP48 for the 3.3 V connection of VPUMP to the FPGA is labeled with “106,” which indicates that it is connected to pin 106. Similarly, SW4 has a jumper above it called JP14, which is labeled with “64,” indicating that SW4 is connected through to pin 64 of the FPGA when this jumper is in place. Disconnecting the jumpers JP11, JP12, JP13, and JP14 causes the momentary push-button switches (SW1, SW2, SW3, and SW4) to be disconnected from the FPGA so that the I/O pins 68, 67, 66, and 64 may be used for other purposes. Disconnecting the eight jumpers, JP1 through JP8, causes the eight light emitting diodes (D1 through D8) to be disconnected from the FPGA I/O pins 63, 61, 60, 59, 58, 57, 56, and 55, respectively. The momentary push-button switches (SW5 and SW6, for applying a reset pulse and a global pulse) are connected via jumpers JP15 and JP16 to I/Os 159 and 113 respectively. Again, all labeling is clearly shown on the silk screen. The hex switches U13 and U14 each are connected to four I/Os on the FPGA. There are four separate jumpers for each of these hex switches, located on the bottom right of the board. They are labeled with Bit0, Bit1, Bit2, and Bit3 on the silk screen, as well as being labeled with the I/O pin on the FPGA to which each is connected. This allows you to individually control the desired effect of a switch and, by connecting directly to the FPGA side of a disconnected jumper, hold a particular pin at a chosen logic level while continuing to use the hex switch to affect other pins. This flexibility is useful for experimentation with designs of your own choosing and connecting other external equipment to the board for development purposes. The internal and external oscillator selection via JP24 is worth a mention. JP24 is a three-pin header onto which a normal two-hole shunt is fitted. Normally the shunt is connected across pins 3 and 2 of JP24. In this position the on-board oscillator, U1, provides the internal clock to the middle pin of the jumper which in turn is connected to pin 26 of the FPGA. By moving the shunt down to connect pins 2 and 1 of JP24, the external clock at pin 1 is connected to the FPGA instead. The external clock is connected via the SMA connector J19 at the bottom left of the board. The OLED display on the board is interfaced using the I2C protocol. The associated jumpers for the I2C interface are JP41, JP42, and JP43, located on the top left side of the board. These are connected to I/O pins 197, 198, and 194 respectively.

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Hardware Components The OLED control signals are provided from I/O pins 193, 192, and 191 via jumpers JP44, JP45, and JP46 respectively. Table 2-1 provides a summary of jumpers available on the board with their description. Table 2-1 • Summary of Jumpers Jumper

Description

JP1 to JP8

To connect LEDs (LED1 to LED8) to FPGA

JP10

VJTAG enable/disable

JP11 to JP14

To connect push-button switches (SW1, SW2, SW3 and SW4) to FPGA

JP15 and JP16

To connect momentary push-button switches SW5 and SW6 to FPGA

JP9 and JP17 to JP19

To connect hex switch (U13) to FPGA

JP20 to JP23

To connect hex switch (U14) to FPGA

JP24

On-board or external clock source selection

JP25

OLED VCC 10 V supply

JP26

OLED loopback

JP41 to JP46

To connect OLED to FPGA

JP48

VPUMP voltage

JP49

VCCPLC – Power supply to the east side PLL

JP50

VCCPLF – Power supply to the west side PLL

Test Points All test points on the board are fitted with small test loops. These test points are labeled on the silkscreen as TP1, TP2, etc. All such test points are also labeled on the silk screen with the voltage expected to be observed at that test point. Voltages will be one of 3.3 V, 2.5 V, 1.8 V, 1.5 V or GND. When measuring the voltage at a test point with a DVM (digital voltage multimeter), the ground lead should be connected to a test point labeled GND and the voltage lead should be connected to the voltage to be tested. All voltage labels on the board are relative to a 0 V ground reference or GND.

Prototyping Area The prototyping area to the right of the board has the bottom two rows of pins connected to ground, labeled as GND on the silk screen and enclosed in a box, giving 16 holes connected to 0 V. The top two rows of pins are connected to various power supply rails internally in the board. They are grouped into squares of four pins from left to right as follows: 3.3 V, 2.5 V, 1.8 V, and 1.5 V, giving four holes for each voltage level. All other holes in the prototyping area are unconnected and may be used to hold various discrete components as necessary for experimentation. Next to the prototyping area is U2, which is a space for an optional oscillator. This space may be used for fitting a second oscillator to the board, similar to the one used at U1, so as to provide two different frequency clocks to the FPGA. On the reverse side of the board, there is an area labeled U5, which is a TQ100 pattern with some surrounding pads. This area may be used to solder a TQ100 part, and then connect that part by adding discrete wires to the pads and connecting it to desired pins on the board. The main purpose of this is to allow a previously programmed TQ100 packaged device to be used to provide a more interesting system application.

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Layering on Board The complete board design and manufacturing files are available on the Microsemi website: www.microsemi.com/soc/products/hardware/devkits_boards/proasic3_starter.aspx. The board file is in Allegro format, which will allow an end user to create the appropriate Gerbers and other board views as needed. The board is fabricated with 6 layers of copper. The layers are arranged as follows from the top of the board down to the bottom: Layer 1 – Top signal layer Layer 2 – Ground Plane Layer 3 – Signal layer 3, used for LVDS receive and other signals Layer 4 – Signal layer 4, used for LVDS transmit and other signals Layer 5 – Power Plane Layer 6 – Bottom signal layer Note: Note that for signal integrity that the two LVDS layers are sandwiched between ground and power planes to isolate them as best as possible from external influences.

Clock Circuits The ProASIC3/E Starter Kit Board has two clock circuits: a 40 MHz oscillator and a manual clock.

40 MHz Oscillator The 40 MHz oscillator on the board is a 10 ppm stability crystal module which will give good LVDS performance. Should better stability be required, an external oscillator may be provided via the SMA connector. Typically a TCXO will give 1 ppm stability and an OCXO will give 0.1 ppm stability. Both the default on-board oscillator and the SMA are connected to the CLK F input of the West bank of the FPGA. Position is also provided on the board for mounting a second crystal oscillator module connected to the CLK C input of the FPGA on the East bank.

LED Device Connections Eight LEDs are connected to the device via jumpers JP1 to JP8. If the jumpers are in place, the device I/O can drive the LEDs. The LEDs change based on the following output: •

A ‘1’ on the output of the device lights the LED.



A ‘0’ on the output of the device switches off the LED.



An unprogrammed or tristated output may show a faintly lit LED.

Note: If the I/O voltage of Bank 5 (on ProASIC3, set by SW8) or Bank 2 (ProASIC3E set by SW8 and SW7 being at the same level) is not at least 2.5 V, the LEDs will not illuminate. A setting of 1.8 V on the voltage bank will cause extremely faint illumination.

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Hardware Components Table 2-2 lists the LED/device connections. To use the device I/O for other purposes, remove the jumpers. Table 2-2 • LED Device Connections LED

Device Connection

D1

U8 Pin 63

D2

U8 Pin 61

D3

U8 Pin 60

D4

U8 Pin 59

D5

U8 Pin 58

D6

U8 Pin 57

D7

U8 Pin 56

D8

U8 Pin 55

Switches Device Connections Four switches are connected to the device via jumpers JP11 to JP14. If the jumpers are in place, the device I/O can be driven by the switches listed in Table 2-3. •

Pressing a switch drives a ‘1’ into the device. The ‘1’ continues to drive while the switch is in place.



Releasing a switch drives a zero into the device.

Table 2-3 lists the switch/device connections. To use the device I/O for other purposes, remove the jumpers. Table 2-3 • Switch Device Connections Switch

Device Connections

SW1

U8 Pin 68

SW2

U8 Pin 67

SW3

U8 Pin 66

SW4

U8 Pin 64

FPGA – OLED Interface An OLED display module is provided on the ProASIC3/E Starter Kit Board for demonstrating the board’s functionality. The display used on the A3PE-STARTER-KIT-2 board is PACER 96x16 OLED module, PMO18701 using SSD0300 as driver IC. One of the functions of the ProASIC3/E is to interface to OLED and give users the ability to display data or a custom message.

Description The PACER OLED module, PMO18701 can be connected with parallel interface or serial interface using SPI or I2C protocol. In this ProASIC3/E Starter Kit Board, the above OLED module is being connected to operate with I2C protocol to minimize the number of FPGA lines committed to the interface. Three I2C interface signals and three control signals: D/C#, RES#, and CS# are required to drive the OLED module. The BANK0 I/O lines of FPGA are used for driving the OLED. Both VCCI and VMV power points of Bank0 are from a fixed 3.3 volts source, thereby enabling BANK0 to function in LVTTL mode.

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ProASIC3/E Starter Kit User’s Guide The interconnection details between the FPGA and the OLED module are listed in Table 2-4. Table 2-4 • FPGA – OLED Interconnections FPGA Pin No.

OLED Pin No.

OLED Pin Name

197

20

D0

198

21

D1

194

22

D2

193

17

D/C#

192

16

RES#

191

15

CS#

When the user of the Starter Kit Board is in need of these BANK0 I/O lines of FPGA for an application, the shorting links inserted on the 2-pin headers JP41, JP42, JP43, JP44, JP45, and JP46 are to be removed. Refer to Figure B-5 on page 42. These BANK0 I/O lines of FPGA are also available on J14D for user evaluation. Refer to Figure B-7 on page 44 for FPGA Headers interface connections. Note: Jumper JP47 is not available on the A3PE-STARTER-KIT-2 REV A board. An older version of the board comes with an LCD where jumper JP47 is required to interface it to the FPGA.

Caution Both the removal and insertion of shorting links on the JP41, JP42, JP43, JP44, JP45, and JP46 must be carried out only when the entire ProASIC3/E Starter Kit Board is in powered OFF condition.

OLED Power Supply Circuit The OLED module requires low current 10 V supply and 3.3 V supply to operate correctly. The 10 V supply is provided by a 5 V to 10 V step-up DC/DC converter (LT1615) and the 3.3 V supply is provided by a step-down voltage regulator (LM2678S) as shown in Figure B-5 on page 42. The 5 V input to the step-up DC/DC converter is provided using LM2674M-5.0 (U20) switching regulator from 9 V DC power supply. The ON/OFF control required for the U20 is controlled by SW11. Note: SW11 also controls U11 and hence all the board regulator power supplies. The presence of the 5 V power supply from U20 is indicated by the LED D17. The glowing of D17 indicates the presence of a 5 V power supply. When the user does not need the OLED at all, the shorting links on JP41, JP42, JP43, JP44, JP45, and JP46 headers are to be removed. Follow the procedure listed in the "Caution" section on page 19. Refer to Figure B-11 on page 48 and Figure B-5 on page 42 for the OLED power supply circuit details.

LVDS Channels Four LVDS channels with up to a maximum signaling rate of 350 MHz are supported on the Starter Kit Board. These LVDS signals are brought out to a pair of RJ-45 (CAT-5E) sockets (J40 and J41). Refer to the ProASIC3/E Starter Kit Board PCB layout, Figure 2-1 on page 10, for the position of these connectors. The LVDS signals are driven using 8 differential pairs (consisting of 16 I/O pins) from the west side (Bank6 and Bank7) of the FPGA device A3PE1500-PQ208. These 16 signals are terminated on the J40 and J41 connectors. The FPGA pins used for LVDS signaling are listed in Table 2-7. The LVDS signals are terminated on J40 and J41 connectors so that a standard patch cable can be used for doing loop-back testing. Refer to Figure B-11 on page 48 of the ProASIC3/E Starter Kit Board schematics for schematic representation of connector signal details.

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Hardware Components The four differential pairs (consisting of eight I/O pins) are terminated as shown in Table 2-5 using the color convention on the first RJ45 connector (referred to as “CAT 5E Primary” for the purpose of differentiation). Table 2-5 • Color Convention on CAT 5E Primary Color

Pin

Signal

White/Orange

p1

TX1+

Orange

p2

TX1–

White/Green

p3

RX1+

Blue

p4

TX2–

White/Blue

p5

TX2+

Green

p6

RX1–

White/Brown

p7

RX2+

Brown

p8

RX2–

Notes: 1. TXn+ refers to positive signal of the transmit side of balanced signal transmission. 2. TXn– refers to negative signal of the transmit side of balanced signal transmission. 3. RXn+ refers to positive signal of the receive side of balanced signal transmission. 4. RXn– refers to negative signal of the receive side of balanced signal transmission. The four differential pairs (consisting of eight I/O pins) are terminated as shown in Table 2-6 using the following color convention on the second LVDS connector (referred to as l “CAT 5E SECONDARY” for the purpose of differentiation). Table 2-6 • Color Convention on CAT 5E Secondary Color

Pin

Signal

White/Orange

p1

RX3+

Orange

p2

RX3–

White/Green

p3

TX3+

Blue

p4

RX4–

White/Blue

p5

RX4+

Green

p6

TX3–

White/Brown

p7

TX4+

Brown

p8

TX4–

Note: The colors refer to the colors that will appear on the CAT 5E cable. The pin numbers correspond to the pin numbers of an RJ-45 connector. Note that the CAT-5E PRIMARY connections are labeled for the purposes of what is regarded as standard connections for CAT-5E on Ethernettype connectors. The connections on the CAT-5E SECONDARY are reversed so as to allow a standard patch cable to check loopback on these LVDS signals.

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ProASIC3/E Starter Kit User’s Guide A 1-foot CAT5 standard patch cable supplied with the ProASIC3/E Starter Kit can be used for LVDS signals loopback. Also note that the VCCI and VMV voltages of Bank6 and Bank7 (west side) are connected to a fixed 2.5 volts, which is required in ProASIC3 (LVDS only available in A3P250 and larger) and ProASIC3E (LVDS available in all devices) for LVDS signaling. Table 2-7 • FPGA – LVDS I/O Pin Details FPGA Pin No.

FPGA I/O Pin Name1

Signal Name

CAT5E Connector Pin No.

7

GAC2/IO132PDB7V1

TX1+

CAT 5E – PRI –1

8

IO132NDB7V1

TX1–

CAT 5E – PRI –2

9

IO130PDB7V1

TX2+

CAT 5E – PRI – 5

10

IO130NDB7V1

TX2–

CAT 5E – PRI – 4

11

IO127PDB7V1

RX1+

CAT 5E – PRI –3

12

IO127NDB7V1

RX1–

CAT 5E – PRI – 6

13

IO126PDB7V0

RX2+

CAT 5E – PRI – 7

14

IO126NDB7V0

RX2–

CAT 5E – PRI – 8

30

GFA2/IO117PDB6V1

TX3+

CAT 5E – SEC –3

31

IO117NDB6V1

TX3–

CAT 5E – SEC –6

37

IO112PDB6V1

TX4+

CAT 5E – SEC – 7

38

IO112NDB6V1

TX4–

CAT 5E – SEC – 8

42

IO106PDB6VO

RX3+

CAT 5E – SEC –1

43

IO106NDB6V0

RX3–

CAT 5E – SEC – 2

44

GEC1/IO104PDB6V0

RX4+

CAT 5E – SEC – 5

45

GEC0/IO104NDB6VO

RX4–

CAT 5E – SEC – 4

Notes: 1. Pin names are valid only for the A3PE600-PQ208 part. They are not correct for use with an A3P250. 2. J40 – RJ45 connector is referred as CAT 5E PRIMARY connector. 3. J41 – RJ45 connector is referred as CAT 5E SECONDARY connector Refer to the PCB layout, Figure 2-1 on page 10, for the location of J40 and J41 connectors on the ProASIC3/E Starter Kit Board.

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3 – Setup and Self Test This chapter outlines how to set up and test the ProASIC3/E Starter Kit Board.

Software Installation The ProASIC3/E Starter Kit includes Libero SoC software. For the latest version of Libero SoC software, refer to the Microsemi SoC products group website: www.microsemi.com/soc/download/software/libero/default.aspx For Libero SoC software installation instructions, refer to the Libero SoC Quick Start Guide for Software v10.0: www.microsemi.com/soc/documents/libero_soc_qs_ug.pdf.

Hardware Installation FlashPro4 is required to use the ProASIC3/E Starter Kit. For software and hardware installation instructions, refer to the FlashPro User’s Guide at www.microsemi.com/soc/documents/flashpro_ug.pdf.

Testing the Starter Kit Board Refer to "Test Procedures for Board Testing" on page 29.

Programming the Test File To retest the Starter Kit Board at any time, use the test program to reprogram the board. Download the ProASIC3/E Starter Kit example design from the Microsemi website: www.microsemi.com/soc/products/hardware/devkits_boards/proasic3_starter.aspx Using FlashPro software, program the example design on ProASIC3/E device. This design is currently implemented for the A3PE1500 die size. For a device of a different size, it is possible to recompile the design into other device sizes. For information about retargeting the device, refer to the Designer User’s Guide at www.microsemi.com/soc/documents/designer_ug.pdf. For instructions on programming the device using FlashPro4, refer to the FlashPro User’s Guide.

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4 – Test Design Description of Test Design This description of the test design is provided with the Starter Kit. This design contains a data generator block for LEDs, PLL for clock generation, and an OLED display driver block. A block diagram of the design is shown in Figure 4-1.

OLED_driver start

SW1

sda scl resetn

40MHz

PLL CLKA

GLA

2.5 MHz

cnt[19]

pacer_rst Power_up_del OLED _init

cnt[18]

OLED _CLK

SDA SCL Pacer_rst OLED_init

Counter [19:0] cnt[1] CLK

Data_Block

Aclr Data_select

SW5 SW6

Direction sload UpDown HexA[3:0] HexB[3:0]

SW4 SW3 SW2 HexA[3:0] HexB[3:0]

DATA_LED[7:0] LED[7:0]

Figure 4-1 • Design Block Diagram The on-chip PLL takes a 40 MHz oscillator clock as reference input and generates 2.5 MHz clock for the design. The data generator (Data_Block) generates an eight-bit up-down counter and eight-bit flashing signal. The data generator output is displayed on the ProASIC3/E starter kit board LEDs. By default, an eight-bit flashing signal is displayed on the LEDs. The LEDs flashing direction can be changed by pressing SW4. You can switch between the data using the SW6 signal. The counter has synchronous load and an asynchronous clear. The counter can be loaded with the hex switches data by pressing SW3. Press and hold SW2 for down counting.

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Test Design A block diagram of the Data_Block is shown in Figure 4-2.

Aclr Data_select

Q

CLK SW6_MuxSel

mux2A[7:0] S

LED_Flashing Clock Aclr

Clock Direction

A[7:0]

Q[7:0]

Y[7:0]

DATA_LED[7:0]

B[7:0]

Direction

LED_Flashing_instanc e

DATA_MUX

count8 Clock

Data [7:0]

Updown Aclr Sload

Updown Aclr Sload

HexAB[7:0]

HexAB[7:0]

count8_instance

Figure 4-2 • Data Block Diagram When SW1 is pressed, the OLED displays "Microsemi A3PE STARTER -KIT". The OLED driver module in the design handles the data formatting and I2C communication to the OLED, including power-up initialization. The data to be displayed on the OLED is stored in a 96×16 bit array.Table 4-1 shows the functionality of different switches. Table 4-1 • Switches Action

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Results

Press SW1

To start OLED display.

Press SW2

Up-Down control for the 8-bit counter. Press and hold SW2 for down count.

Press SW3

Synchronous load for the 8-bit counter. Press SW3 for loading from the hex switches. Holding the SW3 displays the hex switches value on LEDs.

Press SW4

Direction control for LEDs flashing. While LEDs flashing is selected with SW6, SW4 can be used to change the LEDs flashing direction.

Press SW5

Asynchronous clear for the whole design.

Press SW6

Select for DATA_BLOCK. It allows switching LED output between the counter and flashing data.

Change Hex Switch setting (U13 and U14)

Changes the loaded data for the eight-bit counter.

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5 – LVDS Signal Evaluation Introduction This chapter explains the test setup and design for the LVDS signal evaluation. It reports the measurements performed on the board, and at the end, makes recommendations to increase the LVDS signal quality in order to meet the performance criteria.

Test Setup Hardware The test setup uses a ProASIC3 Development Kit containing an A3PE600-PQ208 engineering sample. LVDS loopback is closed using various lengths of CAT-5E cables (1-, 3-, and 6-foot). The measurements are taken using a 1159A-1 GHz Agilent differential probe.

Design Figure 5-1 shows the block diagram of the transmitter section of the test design programmed inside the ProASIC3 FPGA. As shown in Figure 5-1, the design contains two similar channels of data. Channel A is driven by a PLL to achieve high data rates, and Channel B uses an external clock in the event that slow data rates are needed for test or debugging purposes.

LFSR_1

DDR-REG out

clk

Qr PLL

LFSR_2

CLK_1

Dout

out

clk

LFSR_1

Channel A

Qf Clk DDR-REG

out

clk

Qr CLK_2

LFSR_2 clk

out

Dout

Channel B

Qf Clk

Figure 5-1 • TX Portion of Test Design Each channel uses an LFSR to generate a pseudo-random data stream. The data stream is entered in DDR registers to achieve higher data rates from relatively slower clocks (e.g., 300 Mbps data rate from 150 MHz clock). The output of the DDR registers is sent out using the LVDS I/O standard. The output data is looped back and received by the FPGA using LVDS receivers.

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LVDS Signal Evaluation

Measurement Results Figure 5-2 shows the LVDS signal across the 100 Ohm termination resistor at 300 Mbps. Figure 5-2 shows that the eye height across the termination is about 275 mV which is well within the LVDS specification.

Figure 5-2 • LVDS Signal across RX Termination at 300 Mbps

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6 – Test Procedures for Board Testing Overview This document defines the test procedure required to be carried out by the Microsemi SoC Products Group designated manufacturer's testing facility on the ProASIC3/E Starter Kit Board with silkscreen labeling A3PE-STARTER-KIT-2 REV A. This testing is specific to the socketed version of the board. All steps in the following enumerated test procedure should be followed in sequence for testing the board. Deviations in the sequence are explained in the text.

Equipment Required Equipment Provided by Microsemi SoC Products Group to Testing Facility Microsemi SoC Products Group will provide the following: •

This test procedure document.



FlashPro v9.1 software or latest on Microsemi website



FlashPro4 programmer and programming cable for connecting to the A3PE-STARTER-KIT-2 REV A.



Pre-programmed A3PE1500-PQ208 silicon. Ten devices will be provided for ten boards. The initial silicon will not be labeled as having been programmed. (this is just for the testing associated with the first manufacturing build.) Additional devices will be provided for testing further boards and this change will be detailed in an update to the procedure.



Power supply (+9 V, 2 A CUI) for the ProASIC3/E Starter Kit Board plus a mains cable for the power supply.

Testing Facility Equipment to be Available for Testing The manufacturer's testing facility will provide the following equipment for testing of the board: •

Digital Multimeter to measure voltages on the circuit board at the known test points.

Test Procedure for the A3PE-STARTER-KIT-2 In this section, full test procedure for the boards is outlined. This procedure applies to socketed boards. For boards fitted with directly soldered parts, the procedure is the same except for fitting of the FPGA. In such cases, adjust the procedure accordingly and ignore references to fitting parts to sockets.

Initial Power-On Procedure This part of the procedure may be carried out independently and ahead of the other parts of the test procedure. Boards passing this procedure may be transferred to a passing set of boards.

To perform the initial power-on procedure: 1. Record the time of the test and the board serial number (written by the bar code on the back of the board) into a test log. 2. Plug the +9 V power supply into the wall.

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Test Procedures for Board Testing 3. Take an A3PE-STARTER-KIT-2 that has an empty socket. Make sure the switch SW11 is in the OFF position, (the switch should be moved to the left). This corresponds with the labeling of the silkscreen on the board. 4. Connect +9 V DC output of the CUI power supply to the J18 connector on the board. You should observe the red LED at the top right of the board; LED D19 should light, indicating +9 V DC has been applied to the board. 5. Move the SW11 switch to the ON position—to the right. Observe that LEDs, D13, D9, D10, D11, and D17 light up green on the board. All LEDs are on the top edge of the board (same edge as red D19 power connector LED, which should remain lit). 6. Using a DVM, measure DC voltages using TP11 as ground: 7. TP6 and TP7 should be 3.3 V (values ±0.2 V are acceptable). Values outside this range are a failure. 8. TP15 should be 1.5 V (values ±0.1 V are acceptable). 9. TP8 should be 1.8 V (values ±0.1 V are acceptable). 10. TP10 should be 2.5 V (values ±0.2 V are acceptable). 11. TP47 should be 5.0 V (values ±0.2 V are acceptable). 12. J14C pin 106 should be 3.3 V (values ±0.2 V are acceptable). Note that jumper JP48 must be in place for this measurement, otherwise zero will be recorded. 13. That completes the initial power-on check. The board should now be switched off by moving SW11 to the OFF position (to the left).

Testing Board Functionality with A3PE1500-PQ208 Silicon To test board functionality: 1. Record the time of the test and the board serial number (written by the bar code on the back of the board) into a test log. 2. Make sure the switch SW11 is in the OFF position (i.e., to the left.) 3. Apply power to the board by attaching the +9 V DC supply to J18. Only the red LED should be illuminated. 4. Undo the four screws holding the socket of U8 in place. Remove the lid of the socket. 5. Place a pre-programmed A3PE1500-PQ208 part into the socket using the appropriate vacuum pen while observing anti-static precautions. Make sure that pin 1 of the FPGA is oriented correctly. The Microsemi SoC Products Group logo on the part should match the orientation of the Microsemi SoC Products Group logo on the board just above the A3PE-STARTER-KIT-2 part number. Take great care to make sure all pins are in correct alignment so that the FPGA is on a level plane parallel to the board. 6. Carefully replace the socket cover and screw down all four corners to appropriate tightness. It is recommended to do opposite corners first so as to lessen rotational torque on the part. 7. Supply power to on-chip PLL by connecting respective supply pin to analog supply rails. Place jumper on JP50 to power the west side PLL, known as PLF. The ground pin of the west side PLL (VCOMPLF) is already connected to ground. 8. Switch on SW11 to the ON position (slide it to the right). 9. Validate that all 5 LEDs at the top of the board including the red one turn on. D17, D11, D10, D9, D13, and D19. 10. Validate that the 8 LEDS: D8, D7, …, and D2, D1 all pulsate in either a counting pattern or a flashing towards left pattern. 11. If no LEDs are visible, stop and switch off SW11. Rotate SW8 and SW9 clockwise to the 3.3 V selection. This is best described with the thicker arrow bar pointing upward. Switch the board back on. The LEDs should be visible. If very dim, stop, switch off the board and rotate the switches one quarter turn clockwise before switching board back on. Continue if the LEDs are glowing. If unable to get a display on the LEDs, the board must be tagged as bad.

30

R e visio n 5

ProASIC3/E Starter Kit User’s Guide 12. If it is a bad board, carefully remove the A3PE1500 silicon from the socket and set it aside in an electrostatic-safe area. Using another piece of pre-programmed silicon, repeat steps 4 to 8 above. 13. If still no response, mark the board as defective and re-use the silicon for other testing. 14. If there is a good response, then place the previous silicon in a “bad” tray to prevent it from being retested. 15. Validate the change in direction of LEDs flashing by pressing SW4 on the bottom side of the board. 16. Validate that the patterns can be switched by pressing SW6 (Global pulse) on the left side of board. When the switch is pressed, the LED D15 should momentarily light. The pattern on the 8 LEDs D8 through D1 will change. 17. Press and hold SW2 to change the counting direction. Validate the change in counting pattern on LEDs. 18. Press and hold SW3 to validate the hex switches values displayed on LEDs. 19. Validate that the message MICROSEMI A3PE STARTER - KIT displayed on OLED by pressing SW1. 20. Connect a FlashPro4 programmer to a PC USB port and observe the power light illuminating. Ensure that the FlashPro 9.1 or latest version is installed on the PC being used. 21. Connect the programming cable of the FlashPro4 programmer to the J1 shrouded and keyed header labeled FP. The red line labeling pin 1 should be close to pin 1 on the header – no other orientation is possible. On the PC, run the FlashPro 9.1 or latest version and connect to the programmer. Select ProASIC3E as the device family. Once the software has shown a connection, select Analyze Chain from the File menu. If an error message of incorrect VJTAG is reported, then remove the jumper placed at J5 and place it instead at J12 across pins 11 and 12. It may safely be left there. Repeat the Analyze Chain command. If a message appears indicating that an A3PE1500 part (depending on the device fitted to the board) has been detected, then the board has passed this test. Leave the silicon in place in the socket and move to the next step. If a message of 11 or some other numeric indication appears, then record the message in a test log and fail the board. Remove the silicon from the socket and place it in the safe silicon holding area. 22. This concludes the testing of the board. Switch SW11 to the OFF position and remove the power connector from J18.

Revision 5

31

A – PQ208 Package Connections I/O Naming Conventions Due to the comprehensive and flexible nature of ProASIC3/E device user I/Os, a naming scheme is used to show the details of the I/O. The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os. I/O Nomenclature

= Gmn/IOuxwBy

Gmn is only used for I/Os that also have CCC access – i.e., global pins. G = Global m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle) n = Global input MUX and pin number of the associated Global location m, either A0, A1,A2, B0, B1, B2, C0, C1, or C2 u = I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise direction x = P (Positive) or N (Negative) for differential pairs, or S (Single-Ended) for the I/O that support single-ended and voltage-referenced I/O standards only w = D (Differential Pair) or P (Pair) or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. B = Bank y = Bank number [0.3] for ProASIC3 and [0.7] for ProASIC3E. Bank number starting at 0 from the northwest I/O bank in a clockwise direction Figure A-1 and Table A-1 are extracted from the ProASIC3E datasheet and provide package connections for the A3PE1500 device. Pinouts for other devices in the PQ208 family can be found on the Microsemi SoC Products Group website: ProASIC3 Flash Family FPGAs datasheet at www.microsemi.com/soc/documents/PA3_DS.pdf ProASIC3E Flash Family FPGAs datasheet at www.microsemi.com/soc/documents/PA3E_DS.pdf The website should always be referenced for access to the most recent datasheet.

Revision 5

33

PQ208 Package Connections

208-Pin PQFP

1

208

208-Pin PQFP

Figure A-1 • 208-Pin PQFP

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R e visio n 5

ProASIC3/E Starter Kit User’s Guide Table A-1 • Device Connections for 208-Pin PQFP 208-Pin PQFP

208-Pin PQFP

208-Pin PQFP

Pin Number

A3PE1500 Function

Pin Number

A3PE1500 Function

Pin Number

A3PE1500 Function

1

GND

36

VCC

71

VCC

2

GNDQ

37

IO184PDB6V2

72

VCCIB5

3

VMV7

38

IO184NDB6V2

73

IO145NDB5V1

4

GAB2/IO220PSB7V3

39

IO180PSB6V1

74

IO145PDB5V1

5

GAA2/IO221PDB7V3

40

VCCIB6

75

IO143NDB5V1

6

IO221NDB7V3

41

GND

76

IO143PDB5V1

7

GAC2/IO219PDB7V3

42

IO176PDB6V1

77

IO137NDB5V0

8

IO219NDB7V3

43

IO176NDB6V1

78

IO137PDB5V0

9

IO215PDB7V3

44

GEC1/IO169PDB6V0

79

IO135NDB5V0

10

IO215NDB7V3

45

GEC0/IO169NDB6V0

80

IO135PDB5V0

11

IO212PDB7V2

46

GEB1/IO168PPB6V0

81

GND

12

IO212NDB7V2

47

GEA1/IO167PPB6V0

82

IO131NDB4V2

13

IO208PDB7V2

48

GEB0/IO168NPB6V0

83

IO131PDB4V2

14

IO208NDB7V2

49

GEA0/IO167NPB6V0

84

IO129NDB4V2

15

IO204PSB7V1

50

VMV6

85

IO129PDB4V2

16

VCC

51

GNDQ

86

IO127NDB4V2

17

GND

52

GND

87

IO127PDB4V2

18

VCCIB7

53

VMV5

88

VCC

19

IO200PDB7V1

54

GNDQ

89

VCCIB4

20

IO200NDB7V1

55

IO166NDB5V3

90

IO121NDB4V1

21

IO196PSB7V0

56

GEA2/IO166PDB5V3

91

IO121PDB4V1

22

GFC1/IO192PSB7V0

57

IO165NDB5V3

92

IO119NDB4V1

23

GFB1/IO191PDB7V0

58

GEB2/IO165PDB5V3

93

IO119PDB4V1

24

GFB0/IO191NDB7V0

59

IO164NDB5V3

94

IO113NDB4V0

25

VCOMPLF

60

GEC2/IO164PDB5V3

95

GDC2/IO113PDB4V0

26

GFA0/IO190NPB6V2

61

IO163PSB5V3

96

IO112NDB4V0

27

VCCPLF

62

VCCIB5

97

GND

28

GFA1/IO190PPB6V2

63

IO161PSB5V3

98

GDB2/IO112PDB4V0

29

GND

64

IO157NDB5V2

99

GDA2/IO111PSB4V0

30

GFA2/IO189PDB6V2

65

GND

100

GNDQ

31

IO189NDB6V2

66

IO157PDB5V2

101

TCK

32

GFB2/IO188PPB6V2

67

IO153NDB5V2

102

TDI

33

GFC2/IO187PPB6V2

68

IO153PDB5V2

103

TMS

34

IO188NPB6V2

69

IO149NDB5V1

104

VMV4

35

IO187NPB6V2

70

IO149PDB5V1

105

GND

Revision 5

35

PQ208 Package Connections Table A-1 • Device Connections for 208-Pin PQFP 208-Pin PQFP

208-Pin PQFP

208-Pin PQFP

Pin Number

A3PE1500 Function

Pin Number

A3PE1500 Function

Pin Number

A3PE1500 Function

106

VPUMP

141

GND

175

IO35PDB1V0

107

GNDQ

142

VCC

176

IO35NDB1V0

108

TDO

143

IO73NDB2V2

177

IO31PDB0V3

109

TRST

144

IO73PDB2V2

178

GND

110

VJTAG

145

IO71NDB2V2

179

IO31NDB0V3

111

VMV3

146

IO71PDB2V2

180

IO29PDB0V3

112

GDA0/IO110NPB3V2

147

IO67NDB2V1

181

IO29NDB0V3

113

GDB0/IO109NPB3V2

148

IO67PDB2V1

182

IO27PDB0V3

114

GDA1/IO110PPB3V2

149

IO65NDB2V1

183

IO27NDB0V3

115

GDB1/IO109PPB3V2

150

IO65PDB2V1

184

IO23PDB0V2

116

GDC0/IO108NDB3V2

151

GBC2/IO60PSB2V0

185

IO23NDB0V2

117

GDC1/IO108PDB3V2

152

GBA2/IO58PSB2V0

186

VCCIB0

118

IO105NDB3V2

153

GBB2/IO59PSB2V0

187

VCC

119

IO105PDB3V2

154

VMV2

188

IO18PDB0V2

120

IO101NDB3V1

155

GNDQ

189

IO18NDB0V2

121

IO101PDB3V1

156

GND

190

IO15PDB0V1

122

GND

157

VMV1

191

IO15NDB0V1

123

VCCIB3

158

GNDQ

192

IO12PSB0V1

124

GCC2/IO90PSB3V0

159

GBA1/IO57PDB1V3

193

IO11PDB0V1

125

GCB2/IO89PSB3V0

160

GBA0/IO57NDB1V3

194

IO11NDB0V1

126

NC

161

GBB1/IO56PDB1V3

195

GND

127

IO88NDB3V0

162

GND

196

IO08PDB0V1

128

GCA2/IO88PDB3V0

163

GBB0/IO56NDB1V3

197

IO08NDB0V1

129

GCA1/IO87PPB3V0

164

GBC1/IO55PDB1V3

198

IO05PDB0V0

130

GND

165

GBC0/IO55NDB1V3

199

IO05NDB0V0

131

VCCPLC

166

IO51PDB1V2

200

VCCIB0

132

GCA0/IO87NPB3V0

167

IO51NDB1V2

201

GAC1/IO02PDB0V0

133

VCOMPLC

168

IO47PDB1V1

202

GAC0/IO02NDB0V0

134

GCB0/IO86NDB2V3

169

IO47NDB1V1

203

GAB1/IO01PDB0V0

135

GCB1/IO86PDB2V3

170

VCCIB1

204

GAB0/IO01NDB0V0

136

GCC1/IO85PSB2V3

171

VCC

205

GAA1/IO00PDB0V0

137

IO83NDB2V3

172

IO43PSB1V1

206

GAA0/IO00NDB0V0

138

IO83PDB2V3

173

IO41PDB1V1

207

GNDQ

139

IO81PSB2V3

174

IO41NDB1V1

208

VMV0

140

VCCIB2

36

R e visio n 5

B – Board Schematics This appendix provides illustrations of the ProASIC3/E Starter Kit Board. Note: The following figures are in low resolution. If you would like to see the figures in high resolution, refer to the ProASIC3/E Starter Kit Board Schematics, available at www.microsemi.com/soc/products/hardware/devkits_boards/proasic3_starter.aspx#docs.

Top-Level View Figure B-1 on page 38 illustrates a top-level view of the ProASIC3/E Starter Kit Board. Figure B-2 on page 39 illustrates a bottom-level view of the ProASIC3/E Starter Kit Board.

ProASIC3/E Starter Kit Board Schematics The last pages of this appendix show the following illustrations of the ProASIC3/E Starter Kit Board Schematics in order. Figure B-3 • Main 3.3 V, 2.5 V and 1.5 V Power Figure B-4 • ProASIC3 FPGA Figure B-5 • LED and OLED Module Interface Circuit Figure B-6 • PushButton and Hex Switches Figure B-7 • FPGA Headers and Expansion Bus Figure B-8 • Clocks Oscillators and Reset Figure B-9 • JTAG and JTAG DaisyChain Connector Figure B-10 • Decoupling Caps, Test Points Figure B-11 • LVDS Signal Routing Via CAT-5E Connectors

Revision 5

37

Board Schematics

Figure B-1 • Top-Level View of ProASIC3/E Starter Kit Board

38

R e visio n 5

ProASIC3/E Starter Kit User’s Guide

Figure B-2 • Bottom-Level View of ProASIC3/E Starter Kit Board

Revision 5

39

A

B

C

3.3V

3.3V

3.3V

1.8V

2.5V

RESET25N

0.22UF/25V

C55

1.5V

RESET18N

0.22UF/25V

C56

0.22UF/25V

C54

RESET15N

3 2

1

5

C7 47UF/16V

R1 4.99K

C8 47UF/16V

R8 4.99K

47UF/16V

C6

4.99K

R2

+

+

+

CONN_KLD_SMT

J18

1 2 2 3 4 5 7

2 3 4 5 7

2 3 4 5 7 NC IN3 IN4 EN SENSE

U15

+ C12 10UF/35V

NC IN3 IN4 EN SENSE

U12

U10

NC IN3 IN4 EN SENSE

1

1.5V

+ C10 10UF/35V

19 18 16 15 14 13 12 9 8 6

2 19 18 16 15 14 13 12 9 8 6

19 18 16 15 14 13 12 9 8 6 2.5V

1.8V

TPS75225_QPWP

NC7 NC6 NC5 NC4 NC3 NC2 NC1 O/P9 O/P8 RESET

TPS75218_QPWP

NC7 NC6 NC5 NC4 NC3 NC2 NC1 O/P9 O/P8 RESET

TPS75215_QPWP

NC7 NC6 NC5 NC4 NC3 NC2 NC1 O/P9 O/P8 RESET

+ C11 10UF/35V

1 @

@

4

2 @

+ C3 0.22UF/50V

2A (Max)

2A (Max)

2A (Max)

LCDON_OFF

+ C9 10UF/35V

1 2

4

U11

6

4

3

SW11 1

LM2678S-3.3

NC GND VSW

VIN FB ON/OFF CB

1

22UH

L1

R7

1.8V

D12 CMSH5-40

1

C15 0.01UF/50V

2

C16 0.01UF/50V

1.8V Pwr LED

Q1 MMBT2222

D9

R5 274

3

R6 2K

2K

2

1

R11 2K

1

R9 2K

C2 10UF/16V

2

1.5V

+ C13 100UF/10V

2

+

3.3V

C14 100UF/10V

BOARD INFORMATION PCB FAB:,REV.02

2

PCB ASSEMBLY:,REV.02

3.3V

[email protected] 5A (Max)

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

1.5V Pwr LED

Q2 MMBT2222

D13

R10 274

3.3V

1

5 1

6 3

3.3V

GPI-152-3013

5

2

4

2 7

3

1 2

9 VOLT

VIN

1 2

D

1

2

1

2

1

2

1 2 1 2 1

1 2

1 2 GND GND1 GND2 GND3 GND4 21 1 10 11 17 20 21

1 2

1 2

1 2 2 1 3 2

2 1 2 1 2 1 2

1 2

GND GND1 GND2 GND3 GND4 21 1 10 11 17 20 21 GND GND1 GND2 GND3 GND4 21 1 10 11 17 20 21

1

1 2 1 2 2 1 3

R e visio n 5 2

Figure B-3 • Main 3.3 V, 2.5 V and 1.5 V Power 2

1 2 2 D11

R3 200

2.5V

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

D10

R4 78.7

ECO#

VIN

VIN Pwr LED

D19 RED LED

R54 1K

Descripition

Revision History

1

DVP-100-000300-001 BALA

Document No:

Main 3.3V,2.5V, and 1.5V Power

DRAWN BY:

B

Size:

Title:

1 Approval

Date

Pg

2 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

2.5V Pwr LED

Microsemi

3.3V Pwr LED

1

1 2 2 1

1 2 2

40 1

5

A

B

C

D

Board Schematics

Revision 5

A

B

C

D

C86

IO53NDB3V0 GCA2/IO53PDB3V0 GCA1/IO52PPB3V0

GCC2/IO55PSB3V0 GCB2/IO54PSB3V0

TDO TRSTB VJTAG VMV3 GDA0/IO67NPB3V1 GDB0/IO66NPB3V1 GDA1/IO67PPB3V1 GDB1/IO66PPB3V1 GDC0/IO65NDB3V1 GDC1/IO65PDB3V1 IO62NDB3V1 IO62PDB3V1 IO58NDB3V0 IO58PDB3V0

VPUMP

0.01UF/16V

CLOCKF

IO122PPB7V0 IO121PSB7V0 IO122NPB7V0 GFC1/IO120PSB7V0 GFB1/IO119PDB7V0 GFB0/IO119NDB7V0

2 1 5

1.5V

2 1

VMV7 GAB2/IO133PSB7V1 GAA2/IO134PDB7V1 IO134NDB7V1 GAC2/IO132PDB7V1 IO132NDB7V1 IO130PDB7V1 IO130NDB7V1 IO127PDB7V1 IO127NDB7V1 IO126PDB7V0 IO126NDB7V0 IO124PSB7V0

5

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130

C92 0.33UF/16V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

IC149-208-161-S5_21

GND_8 VPUMP GNDQ_4 TDO TRSTB VJTAG VMV3 GDA0/IO67NPB3V1 GDB0/IO66NPB3V1 GDA1/IO67PPB3V1 GDB1/IO66PPB3V1 GDC0/IO65NDB3V1 GDC1/IO65PDB3V1 IO62NDB3V1 IO62PDB3V1 IO58NDB3V0 IO58PDB3V0 GND_9 VCCIB3 GCC2/IO55PSB3V0 GCB2/IO54PSB3V0 NC IO53NDB3V0 GCA2/IO53PDB3V0 GCA1/IO52PPB3V0 GND_10

U8E

IC149-208-161-S5_21

GND GNDQ VMV7 GAB2/IO133PSB7V1 GAA2/IO134PDB7V1 IO134NDB7V1 GAC2/IO132PDB7V1 IO132NDB7V1 IO130PDB7V1 IO130NDB7V1 IO127PDB7V1 IO127NDB7V1 IO126PDB7V0 IO126NDB7V0 IO124PSB7V0 VCC GND_1 VCCIB7 IO122PPB7V0 IO121PSB7V0 IO122NPB7V0 GFC1/IO120PSB7V0 GFB1/IO119PDB7V0 GFB0/IO119NDB7V0 VCOMPLF GFA0/IO118NPB6V1

U8A

2

JP49

IO47NDB2V1 IO47PDB2V1 IO44NDB2V1 IO44PDB2V1 IO43NDB2V0 IO43PDB2V0 IO40NDB2V0 IO40PDB2V0 GBC2/IO38PSB2V0 GBA2/IO36PSB2V0 GBB2/IO37PSB2V0 VMV2

GCB0/IO51NDB2V1 GCB1/IO51PDB2V1 GCC1/IO50PSB2V1 IO49NDB2V1 IO49PDB2V1 IO48PSB2V1

VCCPLC CLOCKC

2

IO106PDB6V0 IO106NDB6V0 GEC1/IO104PDB6V0 GEC0/IO104NDB6V0 GEB1/IO103PPB6V0 GEA1/IO102PPB6V0 GEB0/IO103NPB6V0 GEB0/IO102NPB6V0 VMV6

IO112PDB6V1 IO112NDB6V1 IO108NPSB6V0

GFA2/IO117PDB6V1 IO117NDB6V1 GFB2/IO116PPB6V1 GFC2/IO115PPB6V1 IO116NPB6V1 IO115NPB6V1

1.5V

4

4

JP50

VCCPLF GFA1/IO118PPB6V1

1.5V

1

1

1.5V

1.5V

131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

U8B

IC149-208-161-S5_21

VCCPLC GCA0/IO52NPB3V0 VCOMPLC GCB0/IO51NDB2V1 GCB1/IO51PDB2V1 GCC1/IO50PSB2V1 IO49NDB2V1 IO49PDB2V1 IO48PSB2V1 VCCIB2 GND_11 VCC_4 IO47NDB2V1 IO47PDB2V1 IO44NDB2V1 IO44PDB2V1 IO43NDB2V0 IO43PDB2V0 IO40NDB2V0 IO40PDB2V0 GBC2/IO38PSB2V0 GBA2/IO36PSB2V0 GBB2/IO37PSB2V0 VMV2 GNDQ_5 GND_12

U8F

IC149-208-161-S5_21

VCCPLF GFA1/IO118PPB6V1 GND_2 GFA2/IO117PDB6V1 IO117NDB6V1 GFB2/IO116PPB6V1 GFC2/IO115PPB6V1 IO116NPB6V1 IO115NPB6V1 VCC_1 IO112PDB6V1 IO112NDB6V1 IO108PSB6V0 VCCIB6 GND_3 IO106PDB6V0 IO106NDB6V0 GEC1/IO104PDB6V0 GEC0/IO104NDB6V0 GEB1/IO103PPB6V0 GEA1/IO102PPB6V0 GEB0/IO103NPB6V0 GEA0/IO102NPB6V0 VMV6 GNDQ_1 GND_4

3

IO18PPB0V2 IO19NPB0V2 IO18NPB0V2 IO17PPB0V2

IO23PPB1V0 IO22PSB1V0 IO23NPB1V0 IO21PDB1V0 IO21NDB1V0 IO19PPB0V2

GBB0/IO34NDB1V1 GBC1/IO33PDB1V1 GBC0/IO33NDB1V1 IO31PDB1V1 IO31NDB1V1 IO27PDB1V0 IO27NDB1V0

GBA1/IO35PDB1V1 GBA0/IO35NDB1V1 GBB1/IO34PDB1V1

VMV1

IO85NPB5V0 IO84NPB5V0 IO85PPB5V0 IO84PPB5V0 IO83NPB5V0 IO82NPB5V0

IO94PDB5V1 IO92NDB5V1 IO92PDB5V1 IO88NDB5V0 IO88PDB5V0

IO96PSB5V2 IO94NDB5V1

IO101NDB5V2 GEA2/IO101PDB5V2 IO100PDB5V2 GEB2/IO100PDB5V2 IO99NDB5V2 GEC2/IO99PDB5V2 IO98PSB5V2

VMV5

3

1.5V

1.5V

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

U8C

VMV0

GAC1/IO02PDB0V0 GAC0/IO02NDB0V0 GAB1/IO01PDB0V0 GAB0/IO01NDB0V0 GAA1/IO00PDB0V0 GAA0/IO00NDB0V0

IO07PDB0V1 IO07NDB0V1 IO05PDB0V0 IO05NDB0V0

IO13NDB0V2 IO11PSB0V1 IO09PDB0V1 IO09NDB0V1

IO15PDB0V2 IO15NDB0V2

IO16PPB0V2 IO17NPB0V2 IO16NPB0V2

TCK TDI TMS VMV4

GDA2/IO68PDB4V0 GDB2/IO69PSB4V0

IO76NDB4V1 IO76PDB4V1 IO72NDB4V0 IO72PDB4V0 IO70NDB4V0 GDC2/IO70PDB4V0 IO68NDB4V0

IO80NDB4V1 IO80PDB4V1 IO79NPB4V1 IO78NPB4V1 IO79PPB4V1 IO78PPB4V1

IO83PPB5V0 IO82PPB5V0

1.5V

1.5V

PCB FAB:,REV.02

BOARD INFORMATION

2

PCB ASSEMBLY:,REV.02

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

IC149-208-161-S5_21

VMV1 GNDQ_6 GBA1/IO35PDB1V1 GBA0/IO35NDB1V1 GBB1/IO34PDB1V1 GND_13 GBB0/IO34NDB1V1 GBC1/IO33PDB1V1 GBC0/IO33NDB1V1 IO31PDB1V1 IO31NDB1V1 IO27PDB1V0 IO27NDB1V0 VCCIB1 VCC_5 IO23PPB1V0 IO22PSB1V0 IO23NPB1V0 IO21PDB1V0 IO21NDB1V0 IO19PPB0V2 GND_14 IO18PPB0V2 IO19NPB0V2 IO18NPB0V2 IO17PPB0V2

U8G

IC149-208-161-S5_21

VMV5 GNDQ_2 IO101NDB5V2 GEA2/IO101PDB5V2 IO100PDB5V2 GEB2/IO100PDB5V2 IO99NDB5V2 GEC2/IO99PDB5V2 IO98PSB5V2 VCCIB5 IO96PSB5V2 IO94NDB5V1 GND_5 IO94PDB5V1 IO92NDB5V1 IO92PDB5V1 IO88NDB5V0 IO88PDB5V0 VCC_2 VCCIB5 IO85NPB5V0 IO84NPB5V0 IO85PPB5V0 IO84PPB5V0 IO83NPB5V0 IO82NPB5V0

2

U8D

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

DRAWN BY:

B

Size:

Title:

1

DVP-100-000300-001 BALA

Document No:

ProASIC3 FPGA

Pg

3 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

IC149-208-161-S5_21

IO16PPB0V2 IO17NPB0V2 IO16NPB0V2 VCCIB0 VCC_6 IO15PDB0V2 IO15NDB0V2 IO13PDB0V2 IO13NDB0V2 IO11PSB0V1 IO09PDB0V1 IO09NDB0V1 GND_15 IO07PDB0V1 IO07NDB0V1 IO05PDB0V0 IO05NDB0V0 VCCIB0 GAC1/IO02PDB0V0 GAC0/IO02NDB0V0 GAB1/IO01PDB0V0 GAB0/IO01NDB0V0 GAA1/IO00PDB0V0 GAA0/IO00NDB0V0 GNDQ_7 VMV0

U8H

IC149-208-161-S5_21

IO83PPB5V0 IO82PPB5V0 GND_6 IO80NDB4V1 IO80PDB4V1 IO79NPB4V1 IO78NPB4V1 IO79PPB4V1 IO78PPB4V1 VCC_3 VCCIB4 IO76NDB4V1 IO76PDB4V1 IO72NDB4V0 IO72PDB4V0 IO70NDB4V0 GDC2/IO70PDB4V0 IO68NDB4V0 GND_7 GDA2/IO68PDB4V0 GDB2/IO69PSB4V0 GNDQ_3 TCK TDI TMS VMV4

Microsemi

183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

1

A

B

C

D

ProASIC3/E Starter Kit User’s Guide

Figure B-4 • ProASIC3 FPGA

41

A

B

C

D

1

D7

C157

0.1uF 16V

3.3V

D8

1

D5

DS1818

GND

VCC

U28

D6

1 R15 274

RST

D4

1

R16 274

1

5

1

5V

C156 +

0

1

1

1

1

1

1

1

1

JP8

JP7

JP6

JP5

JP4

JP3

JP2

JP1

2

2

2

2

2

2

2

2

IO101NDB5V2 (U8 PIN 55)

GEA2/IO101PDB5V2 (U8 PIN 56)

IO100PDB5V2 (U8 PIN 57)

GEB2/IO100PDB5V2 (U8 PIN 58)

IO99NDB5V2 (U8 PIN 59)

GEC2/IO99PDB5V2 (U8 PIN 60)

IO98PSB5V2 (U8 PIN 61)

IO13NDB0V2 (U8 PIN 191)

4.7uF 25V

C159 +

DNP

C160 +

SHDN_LT1615

4 SHDN

U29

10uH

4

LT1615

L6

FB

3

MBR0530

D16

140K,1%

R143

1M,1%

R142

JP25

10uF 16V

C155 +

4.7 pF 50V

C158

2

Mfr P/N :LQH32CN100K53L Mfr P/N :MBR0530T1G Mfr: Murata Mfr: ON Semiconductor

1

1

C1

2

3

1000pF 1000V

2

2

2

(U8 PIN 193) IO09PDB0V1

(U8 PIN 192) IO11PSB0V1

2

(U8 PIN 194) IO09NDB0V1

2

2

10V

3

IO05PDB0V0

(U8 PIN 198)

(U8 PIN 197) IO07NDB0V1

IO96PSB5V2 (U8 PIN 63)

4

5V TO 10V @ 100mA OLED

D1

R19 274

10uF 16V

D2

R18 274

GRM32DR71C106KA01L

R141

D3

R17 274

Mfr P/N :DS1818R-10+T&R Mfr: Dallas

3

2

1

R14 274

1 2

1

2

1

2

2

1

2

2

1

2

2 1 2

2 1 2

2 1 2

2 1 2

1 2

R13 274

5 VIN

1

1

1

1

1

1

1K

1K 2M

R148

OLED_BS1

R146 R147

10K

R144

3.3V

C93

28

17 16 15

12

7 6 5 4 3

IREF

D/C# RES# CS#

BS1

TEST1 TEST2 TEST3 TEST4 TEST5

LED1

1uF

3.3V

10V

PCB FAB:,REV.02

BOARD INFORMATION

2

PCB ASSEMBLY:,REV.02

C95 +

RD#

WR#

BS2

D0 D1 D2 D3 D4 D5 D6 D7

0.01uF

C94

10K

R55

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

OLED_SCL OLED_SDA_IN OLED_SDA_OUT

10K

R40

JP26

BALA

Document No:

1

DVP-100-000300-001

Pg

4 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

10K

R56

3.3V

1

2

LED & LCD Module Interface Circuit

DRAWN BY:

B

Size:

Title:

Microsemi

10K

R145

OLED_BS2

Mfr P/N :PMO13701 Mfr: PACER

PMO13701

29

19

18

13

20 21 22 23 24 25 26 27

TANT

4.7uF 25V

VCOMH

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

LED MODULE INTERFACE CIRCUIT

JP46

JP45

JP44

JP43

JP42

JP41

2

11 VDD VSS 2

R12 274

2

1

R e visio n 5 SW

Figure B-5 • LED and OLED Module Interface Circuit GND

30 VCC NC1 NC2 NC3 NC4 NC5 NC6 1 8 9 10 14 31

42 1

5

A

B

C

D

Board Schematics

A

B

C

D

F0

5 4 3 12

1 2 4 8

B C C DE

5

Hex Switch 8 76

C

B C D EF

A9

U13

0

5 4 3 12

Hex Switch 8 76

1 2 4 8

A9

16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8

U14

RN5 560

4

4

VMV5

1

1

1

1

1

1

1

1

JP23

JP22

JP21

JP20

JP19

JP18

JP17

JP9

2

2

2

2

2

2

2

2

3

IO82NPB5V0 (U8 PIN 78)

IO83NPB5V0 (U8 PIN 77)

IO84PPB5V0 (U8 PIN 76)

IO85PPB5V0 (U8 PIN 75)

IO84NPB5V0 (U8 PIN 74)

IO85NPB5V0 (U8 PIN 73)

IO88PDB5V0 (U8 PIN 70)

IO88NDB5V0 (U8 PIN 69)

VMV5

3

1

1

1

1

332

R24

332

R26

332

R22

332

R21

2

2

2

2

SW4

3 4

SW3

4

3

SW2

4

3

SW1

4

3

C19 0.01UF/50V

C20 0.01UF/50V

C18 0.01UF/50V

C17 0.01UF/50V

2

R25 1K

R27 1K

R23 1K

R20 1K

1

1

1

1

JP11

JP12

JP13

JP14

2

2

2

2

PCB FAB:,REV.02

BOARD INFORMATION

2

PCB ASSEMBLY:,REV.02

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

TL1105SP_F100Q

2

1

TL1105SP_F100Q

2

1

TL1105SP_F100Q

2

1

TL1105SP_F100Q

2

1

1 2 1 2 1 2 1 2

1 2 1 2 1 2 1

Revision 5

2

5

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

DRAWN BY:

B

Size:

Title:

Microsemi

BALA

Document No:

1

DVP-100-000300-001

PushButton & HEX Switches

Pg

5 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

IO92PDB5V1 (U8 PIN 68)

IO92NDB5V1 (U8 PIN 67)

IO94PDB5V1 (U8 PIN 66)

IO94NDB5V1 (U8 PIN 64)

1

A

B

C

D

ProASIC3/E Starter Kit User’s Guide

Figure B-6 • Push-Button and Hex Switches

43

A

B

C

2.5V 1.5V

5

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155

106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156

J12

2 4 6 8 10 12

HEADER 2X52

105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155

J14C

HEADER 2X52

HEADER 2X6

1 3 5 7 9 11

J14A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

Power Connector for Daughter Board

IO47NDB2V1 IO44NDB2V1 IO43NDB2V0 IO40NDB2V0 GBC2/IO38PSB2V0 GBB2/IO37PSB2V0

GCB1/IO51PDB2V1 IO49NDB2V1 IO48PSB2V1

GCB2/IO54PSB3V0 IO53NDB3V0 GCA1/IO52PPB3V0

TRSTB VMV3 GDB0/IO66NPB3V1 GDB1/IO66PPB3V1 GDC1/IO65PDB3V1 IO62PDB3V1 IO58PDB3V0

IO106NDB6V0 GEC0/IO104NDB6V0 GEA1/IO102PPB6V0 GEB0/IO102NPB6V0

T3GFC2/IO115PPB6V1 IO115NPB6V1 T4+ IO108NPSB6V0

IO122PPB7V0 IO122NPB7V0 GFB1/IO119PDB7V0

VMV7 GAA2/IO134PDB7V1 T1+ T2+ IO127PDB7V1 IO126PDB7V0 IO124PSB7V0

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

1.8V

106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

3.3V

1.5V

1.5V

3.3V

3.3V

2

4

VMV1

VMV0

IO47PDB2V1 IO44PDB2V1 IO43PDB2V0 IO40PDB2V0 GBA2/IO36PSB2V0 VMV2

CLOCKC GCB0/IO51NDB2V1 GCC1/IO50PSB2V1 IO49PDB2V1

GCA2/IO53PDB3V0

GCC2/IO55PSB3V0

VPUMP TDO VJTAG GDA0/IO67NPB3V1 GDA1/IO67PPB3V1 GDC0/IO65NDB3V1 IO62NDB3V1 IO58NDB3V0

1

JP48

IO106PDB6V0 GEC1/IO104PDB6V0 GEB1/IO103PPB6V0 GEB0/IO103NPB6V0 VMV6

T4-

IO121PSB7V0 GFC1/IO120PSB7V0 GFB0/IO119NDB7V0 CLOCKF GFA1/IO118PPB6V1 T3+ GFB2/IO116PPB6V1 IO116NPB6V1

GAB2/IO133PSB7V1 IO134NDB7V1 T1T2IO127NDB7V1 IO126NDB7V0

4

3.3V

VMV3

VMV2

IO07NDB0V1 IO05NDB0V0 GAC1/IO02PDB0V0 GAB1/IO01PDB0V0 GAA1/IO00PDB0V0

IO15NDB0V2 IO13NDB0V2 IO09PDB0V1

IO22PSB1V0 IO21PDB1V0 IO19PPB0V2 IO18PPB0V2 IO18NPB0V2 IO16PPB0V2 IO16NPB0V2

VMV1 GBA1/IO35PDB1V1 GBB1/IO34PDB1V1 GBB0/IO34NDB1V1 GBC0/IO33NDB1V1 IO31NDB1V1 IO27NDB1V0

3.3V

3.3V

GDB2/IO69PSB4V0 TCK TMS

IO76PDB4V1 IO72PDB4V0 GDC2/IO70PDB4V0

IO80PDB4V1 IO78NPB4V1 IO78PPB4V1

IO85NPB5V0 IO85PPB5V0 IO83NPB5V0 IO83PPB5V0

IO92NDB5V1 IO88NDB5V0

VMV5 IO101NDB5V2 IO100PDB5V2 IO99NDB5V2 IO98PSB5V2 IO96PSB5V2

2.5V

2.5V

1.5V

1.5V

3

VMV7

VMV6

3

53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103

54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104

157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207

158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208

158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208

54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104

HEADER 2X52

157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207

J14D

HEADER 2X52

53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103

J14B

1.5V VMV5

PCB FAB:,REV.02 2

BOARD INFORMATION

1

GEC0/IO104NDB6V0

4

C1

1

4

C1

GEC1/IO104PDB6V0

IO106NDB6V0

IO106PDB6V0

IO126NDB7V0

R50 100 / 1%

R49 100 / 1%

R52 100 / 1%

R51 100 / 1%

3

C2

2

SW9

3

C2

2

2.5V

1.8V

2.5V

1.8V

1

PCB ASSEMBLY:,REV.02 Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

DRAWN BY:

B

Size:

Title:

Microsemi

RX4- (U8 PIN 45)

RX4+ (U8 PIN 44)

RX3- (U8 PIN 43)

RX3+ (U8 PIN 42)

RX2- (U8 PIN 14)

RX2+ (U8 PIN 13)

RX1- (U8 PIN 12)

RX1+ (U8 PIN 11)

1

DVP-100-000300-001 BALA

Document No:

Rev

6 of 11

A Pg

FPGA Headers & Expansion Bus

A3PE STARTER KIT BOARD REV.A

3) ALL RXn+ AND RXn- (n=0,1,2,3,4)TRACE PAIRS TO BE 100 OHM IMPEDANCE CONTORLLED

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

GAC0/IO02NDB0V0 GAB0/IO01NDB0V0 GAA0/IO00NDB0V0 VMV0

IO11PSB0V1 IO09NDB0V1 IO07PDB0V1 IO05PDB0V0

IO15PDB0V2

IO19NPB0V2 IO17PPB0V2 IO17NPB0V2

IO23PPB1V0 IO23NPB1V0 IO21NDB1V0

GBC1/IO33PDB1V1 IO31PDB1V1 IO27PDB1V0

IO126PDB7V0

IO127NDB7V1

IO127PDB7V1

3.3V

1.5V

3.3V

1.5V

SW8

NOTE:- 1) PLACE RESISTORS R49,50,51,52 CLOSE TO A3P PART(U8)(PAGE 3) IN LAYOUT 2) ALL RXn+ AND RXn- (n=0,1,2,3,4) TRACE PAIRS SHOULD BE MAINTAINED EQUIDISTANT FROM THE FPGA TO THE TERMINATING RESISTORS.

VMV4

GBA0/IO35NDB1V1

TDI VMV4

IO76NDB4V1 IO72NDB4V0 IO70NDB4V0 IO68NDB4V0 GDA2/IO68PDB4V0

IO84NPB5V0 IO84PPB5V0 IO82NPB5V0 IO82PPB5V0 IO80NDB4V1 IO79NPB4V1 IO79PPB4V1

IO94NDB5V1 IO94PDB5V1 IO92PDB5V1 IO88PDB5V0

GEA2/IO101PDB5V2 GEB2/IO100PDB5V2 GEC2/IO99PDB5V2

2

1 2 1 2 1

R e visio n 5

2

44 1

Figure B-7 • FPGA Headers and Expansion Bus 2

D

5

A

B

C

D

Board Schematics

A

B

C

D

Q4 MMBT2222

1

D15

R42 150

3.3V

1

D14

R33 150

3.3V

Q3 MMBT2222

J19

2

3

5

R44 2K

1

R31 2K

1

in Layout

2K

R47

2K

R30

2

2

close to J19

142-0701-201

1

1 2

4

Place R53

1 2 2 1 3 2 1 2 2 1 3 2

C74 1UF/25V

3.3V

R43 221K

3.3V

R32 221K

C21 1UF/25V

R53 49.9

1 2

1 EN

U1

OUT

1 2 3 4 5 6 7 8 SN74LV123ADR

16 15 14 13 12 11 10 9

1K_NL

R29

1A VCC 1B 1REXT 1CLR 1CEXT 1Q 1Q 2Q 2Q 2CEXT 2CLR 2REXT 2B GND 2A

U9

3

1K_NL

R28

3.3V

R57

3.3V

1

39

18.2k

R36

1 2 3 4 5 6 7 8

U16

SN74LV123ADR

1A VCC 1B 1REXT 1CLR 1CEXT 1Q 1Q 2Q 2Q 2CEXT 2CLR 2REXT 2B GND 2A

16 15 14 13 12 11 10 9

3.3V

4

One shot pulse generator for RESET

3.3V

1 18.2k

R48

One shot pulse generator for global

3.3V

Main Oscillator

40MHZ-OSCILLATOR

C4 0.1UF/50V

10K

R149

4

Externial Clock input via SMA

4 VCC GND 2

1 2 1 2

5 1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2

R45 2k

2

R34 2k

2

3

1

1 2 1 2

2

2

2

C73 0.001UF/50V

1UF/25V

1

C75

C22 0.001UF/50V

1UF/25V

1

C23

JP24

3

3

2

2

3 4

4

2

TL1105SP_F100Q

3

SW6

1

1

JP16

TL1105SP_F100Q

2

SW5

1 GBA1/IO35PDB1V1 (U8

R46 332

3.3V

2

C5

0.1UF/50V

10K

R150

1 EN

U2

PCB FAB:,REV.02

2

PCB ASSEMBLY:,REV.02

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

BOARD INFORMATION

OUT

3

1K_NL

R38

R58

1K_NL

R37

3.3V

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

DRAWN BY:

B

Size:

Title:

Microsemi

Optional Oscillator

40MHZ-OSCILLATOR-NL

PIN 113)

PIN 159)

GDB0/IO66NPB3V1 (U8

R35 332

3.3V

(U8 PIN 26)

1

JP15

CLOCKF

1 2 1

Revision 5 2

1 2

4 VCC GND 2

1

2

1

2

5

CLOCKC (U8

PIN 132)

BALA

Document No:

1

DVP-100-000300-001

Clocks Oscillators & Reset

Pg

7 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

39

1

A

B

C

D

ProASIC3/E Starter Kit User’s Guide

Figure B-8 • Clocks Oscillators and Reset

45

Figure B-9 • JTAG and JTAG Daisy Chain Connector

R e visio n 5

A

B

C

5

6

5

TP19 TP20 TP29 TP30 T POINT A T POINT A T POINT A T POINT A

TDI

C2 3

C1 4

J5

2.5V

2 4

2.5V

1.8V

HEADER 2X2

1 3

VJTAG Voltage Selection

2

SW10

TRSTB

TMS

VPUMP

1

TP32 T POINT A 3.3V

3.3V

1.5V

74LVC125APWR

TP21 TP22 TP31 T POINT A T POINT A T POINT A

TDO

U3B

CHAIN

1.5V

1.8V

2

J1

2 4 6 8 10 VJTAG TRSTB

1 2 4

TP34 TP33 TP13 TP14 T POINT A T POINT A T POINT A T POINT A

TP36 TP35 TP17 TP18 T POINT A T POINT A T POINT A T POINT A

SHROUDED OR KEYED HEADER

HEADER 2X5

1 3 5 7 9

FROM FlashPro3 GND OR PREVIOUS BOARD TCK TDO TMS VPUMP TDI

74LVC125APWR

--x--x-- LAST DEVICE (DEFAULT)

-------

J5 JUMPER SETTING

TCK

3

U3A

1

9

R39 274

U3C

3.3V

TCK TDO TMS VPUMP TDI

J2

2 4 6 VJTAG 8 TRSTN 10

HEADER 2X5

1 3 5 7 9

TO NEXT BOARD GND

11 74LVC125APWR

U3D

2 JP10

2

VJTAG

3

PCB FAB:,REV.02

BOARD INFORMATION

2

PCB ASSEMBLY:,REV.02

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

1

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

A3PE STARTER KIT BOARD REV.A

1

DVP-100-000300-001 BALA

Document No:

Pg

8 of 11

A

Rev

JTAG & JTAG DaisyChain Connector

DRAWN BY:

B

Size:

Title:

Microsemi

TP37 TP38 TP45 TP46 TP43 TP44 T POINT A T POINT A T POINT A T POINT A T POINT A T POINT A

Enable/Disable VJTAGdownstream Default Disabled

TP23 TP24 TP25 TP26 TP27 TP28 TP39 TP40 TP41 TP42 T POINT A T POINT A T POINT A T POINT A T POINT A T POINT A T POINT A T POINT A T POINT AT POINT A

12

SHROUDED OR KEYED HEADER

74LVC125APWR

8

U3E

74LVC125APWR

3

14 7

3.3V

10

D

4

4

13

46 1

5

A

B

C

D

Board Schematics

A

B

VMV5

1.8V

1.5V

5

C38 0.01UF/50V

C85 0.01UF/50V

C33 0.01UF/50V

C37 0.01UF/50V

C84 0.01UF/50V

C32 0.01UF/50V

1 C36 0.01UF/50V

VCCPLC

C83 0.01UF/50V

C31 0.01UF/50V

C40 0.01UF/50V

1

C81 0.01UF/50V

C29 0.01UF/50V

C49 0.01UF/50V

2.5V

C97 0.1UF/50V

4

1 VCCPLF

C79 0.01UF/50V

C27 0.01UF/50V

C42 0.01UF/50V

C47 0.01UF/50V

C98 10UF/16V

C80 0.01UF/50V

C28 0.01UF/50V

LAYOUT NOTE: PLACE THESE CAPACITORS NEAR DUT PIN U8.131

C96 0.01UF/50V

1 C43 0.01UF/50V

C48 0.01UF/50V

DE-CAPS FOR VCCPLC

C82 0.01UF/50V

C30 0.01UF/50V

C39 0.01UF/50V

C50 0.01UF/50V

C77 0.01UF/50V

C25 0.01UF/50V

C35 0.01UF/50V

C45 0.01UF/50V

C100 0.1UF/50V

3

TP7

TP9

C101 10UF/16V

C76 0.01UF/50V

TP16 TP15

C24 0.01UF/50V

TP8

C34 0.01UF/50V

TP10 TP5

C44 0.01UF/50V

LAYOUT NOTE: PLACE THESE CAPACITORS NEAR DUT PIN U8.27

C99 0.01UF/50V

DE-CAPS FOR VCCPLF

C78 0.01UF/50V

C26 0.01UF/50V

C41 0.01UF/50V

C46 0.01UF/50V

TP6

1 C72 10UF/16V

C70 10UF/16V

C66 10UF/16V

C62 10UF/16V

C57 10UF/16V

2

C69 10UF/16V

C65 10UF/16V

C61 10UF/16V

C58 10UF/16V

C68 10UF/16V

C64 10UF/16V

C60 10UF/16V

C59 10UF/16V

PCB FAB:,REV.02 2

BOARD INFORMATION PCB ASSEMBLY:,REV.02

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

C71 10UF/16V

C67 10UF/16V

C63 10UF/16V

2

3

1 2

1

2

1 2 1 2

1

2

1

2

C

1 2

1 2

1 2

2 1 2

VMV4

1 2

1 2

1 2

2 1 2 1 2

1 2 1 2 1 2

C51 0.01UF/50V

1 2

C52 0.01UF/50V

1 2

1 2

1 2 1 2 1 2

C53 0.01UF/50V

1 2

1 2

2 1 2 1 2

1 2

2 1 2 1 2

D

1 2

1 2

4

1 2

1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2

3.3V

1

2

1 2

1 2 1 2 1 2

1 2 1 2 1 2

1 2 1 2 1 2

1 2 1 2 1

Revision 5

2

5

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

DRAWN BY:

B

Size:

Title:

Microsemi

TP2

TP1

1

DVP-100-000300-001 BALA

Document No:

Pg

9 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

TP3

Decoupling Caps, Test Points

TP12 TP11 TP4

1

A

B

C

D

ProASIC3/E Starter Kit User’s Guide

Figure B-10 • Decoupling Caps, Test Points

47

A

B

C

D17

R41 475

TP47 5V

C90 0.01UF/16V

2

5

1

D18 CMSH5-40

LCD POWER SUPPLY CIRCUIT

C91 100UF/10V

100uH

L2

C89 0.01UF/50V

[email protected] 500mA (Max)

1 2 1 1

D

2

1

R e visio n 5 2

Figure B-11 • LVDS Signal Routing Via CAT-5E Connectors 2

48 1

4

3

2

U20

GND

VIN

VSW

LM2674M-5.0

FB ON/OFF

NC2

NC1

CB

8 7

5

6

4

4

1 2

5

IO112NDB6V1

C87 100UF/25V

Impedence Control on the TX+ , TX-

(U8 PIN 10) IO130NDB7V1

(U8 PIN 9) IO130PDB7V1

(U8 PIN 8) IO132NDB7V1

(U8 PIN 7) GAC2/IO132PDB7V1

LCDON_OFF

C88 0.22UF/50V

VIN

(U8 PIN 38)

(U8 PIN 37) IO112PDB6V1

(U8 PIN 31) IO117NDB6V1

(U8 PIN 30)GFA2/IO117PDB6V1

TX3+

Traces

TX2-

TX2+

TX1-

TX1+

TX4-

TX4+

TX3-

3

3

(U8 (U8 (U8 (U8

(U8 (U8 (U8 (U8

PIN PIN PIN PIN

PIN PIN PIN PIN

9 10 11 12 13 14 15 16

9 10 11 12 13 14 15 16

PIN PIN PIN PIN

42) 43) 44) 45)

PCB FAB:,REV.02

BOARD INFORMATION PCB ASSEMBLY:,REV.02 2

RX3+ RX3RX4+ RX4-

(U8 PIN 11) RX1+ (U8 PIN 12) RX1(U8 PIN 13) RX2+ (U8 PIN 14) RX2-

(U8 (U8 (U8 (U8

SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

T1+ T1T2+ T2-

8 7 6 5 4 3 2 1 U4

7) 8) 9) 10)

8 7 6 5 4 3 2 1

T3+ T3T4+ T4-

CAT16-LV4F12

30) 31) 37) 38)

2

Date:

04/27/11

Assembly

Doc Ctrl:

Engr:

Eng Mgr:

Approvals:

DRAWN BY:

B

Size:

Title:

Microsemi

J41

GND GND1

TX3+ TX3TX4+ TX4RX3+ RX3RX4+ RX4-

J40

GND GND1

TX1+ TX1TX2+ TX2RX1+ RX1RX2+ RX2-

1

DVP-100-000300-001 BALA

Document No:

Pg10 of 11

A

Rev

A3PE STARTER KIT BOARD REV.A

CAT5E-RJ45 PRIMARY

9 10

1 2 5 4 3 6 7 8

LVDS SIGNAL ROUTING VIA CAT-5E CONNECTORS

T1+ T1T2+ T2-

9 10

3 6 7 8 1 2 5 4

CAT5E-RJ45 SECONDARY

T3+ T3T4+ T4-

1

A

B

C

D

Board Schematics

C – List of Changes List of Changes The following table lists critical changes that were made in each revision of the chapter. Date October 2012

Changes

Page

The part number for the ProASIC3/E Starter Kit was changed from A3PE-STARTER-KIT to A3PE-STARTER-KIT-2 (SAR 42164).

Multi

In the "FPGA – OLED Interface" section, PMO13701 was corrected to PMO18701 (SAR 42164).

18

February 2012 Libero IDE software has been updated to Libero SoC throughout the document (SAR 36951).

Multi

October 2011

Multi

The silicon for this kit has been updated, so the document has been updated accordingly (SAR 27883).

Note: *The part number is located on the last page of the document. The digits following the slash indicate the month and year of publication.

Revision 5

49

D – Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services.

Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world, 650.318.8044

Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues, and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions.

Technical Support Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the website.

Website You can browse a variety of technical and non-technical information on the SoC home page, at www.microsemi.com/soc.

Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website.

Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is [email protected]

Revision 5

51

Product Support

My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases.

Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email ([email protected]) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx.

ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.

52

R e visio n 5

Index A

T

Assumptions 5

tech support

B

ITAR 52 My Cases 52 outside the U.S. 52 technical support 51

board 9

test file

C

programming 23

clock circuits 17 40MHz oscillator 17

contacting Microsemi SoC Products Group customer service 51 email 51 web-based technical support 51 customer service 51

W web-based technical support 51

D Document Assumptions 5

H hardware components 9 hardware installation 23

L LED device connections 17

M Microsemi SoC Products Group email 51 web-based technical support 51 website 51

P product support customer service 51 email 51 My Cases 52 outside the U.S. 52 technical support 51 website 51

S software installation 23 starter kit contents 7

Starter Kit Board 9 switches device connections 18

Revision 5

53

Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996

© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 50200048-5/10.12