Driving a BLDC Motor Using the HT45FM03B – C Language

Driving a BLDC Motor Using the HT45FM03B – C Language

D/N：AN0230E

Introduction Brushless DC motors, which are controlled using electric commutation and PWM modulation, have the advantages of greater motor life by overcoming the problems associated with DC motor mechanical commutation. Applications in recent years have seen their widespread use in home appliances, electric bikes, digital machine tools and robotics to name but a few. The HT45FM03B is a RISC architecture microcontroller device specifically aimed at brushless DC motor control applications. The device includes a complementary PWM controller that has functions such as internal comparator, operational amplifier, multi-channel AD converter, multi-channel external interrupts and a dead time function. The following content uses the HT45FM03B as the core of a brushless DC motor control system to describe the relevant component functions in brushless control motor such as speed setting, commutating principles, PWM modulation, motor over-current protection and motor quick brake methods.

Basic Features The HT45FM03B is situated at the core of the brushless DC motor control system with a host of fully integrated features such as:

 Operating voltage: fSYS = 4MHz at 2.2V~5.5V fSYS = 8MHz at 2.7V~5.5V fSYS = 12MHz at 3.3V~5.5V fSYS = 20MHz at 4.5V~5.5V

 26 bidirectional I/O lines  External interrupt inputs shared with 4 I/O lines  8-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler  16-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler  4096x15 Flash Program Memory  Flash Type MCU  192x8 Data Memory RAM  Integrated crystal, internal RC and external RC oscillators  Fully integrated RC oscillator with three fixed frequencies: 12MHz, 16MHz and 20MHz

1

Driving a BLDC Motor Using the HT45FM03B – C Language  Watchdog timer function  PFD for audio frequency generation  HALT and wake-up functions to reduce power consumption  Up to 0.2　s instruction cycle with 20MHz system frequency at VDD=5V  8-level subroutine nesting  8-channel 12-bit resolution A/D converter  3 pairs of 10-bit PWM complementary outputs shared with six I/O lines and with 3 PWM duty control registers

 Bit manipulation instructions  Table read instructions  63 powerful instructions  All instructions in one or two machine cycles  Low voltage reset function  Low voltage protect function  Single Operational Amplifier  One comparator with interrupt function  28-pin SOP package P B 5 /A N 5 /[IN T 0 B ] 1

2 8

P B 6 /A N 6 /[IN T 0 C ]

P B 4 /A N 4 /[IN T 0 A ] 2

2 7

P B 7 /A N 7 /T M R 0 /T M R 1 P A 4 /IN T 0 A

P A 3 /C O U T 3

2 6

P A 2 /C V IN N 4

2 5

P A 5 /IN T 0 B

P A 1 /C V IN P 5

2 4

P A 6 /IN T 0 C

P A 0 /O P V IN P 6

2 3

P A 7 /IN T 1

P B 3 /A N 3 /O P V IN N 7

2 2

P D 3 /O S C 2

P B 2 /A N 2 /O P O U T 8

2 1

P D 2 /O S C 1

P B 1 /A N 1 9

2 0

V D D /A V D D

P B 0 /A N 0

1 0

1 9

P D 1 /R E S

V S S /A V S S

1 1

1 8

P D 0 /P F D

P C 0 /P W M 0 H

1 2

1 7

P C 5 /P W M 2 L

P C 1 /P W M 0 L

1 3

1 6

P C 4 /P W M 2 H

P C 2 /P W M 1 H

1 4

1 5

P C 3 /P W M 1 L

H T 4 5 F M 0 3 B 2 8 S O P -A

Figure 1 This application will introduce the relevant components in the HT45FM03B for operation in a brushless DC motor control system as well as the relevant control principles.

BLDC Motor Introduction Brushless DC (BLDC) motors use semiconductor components to implement electrical commutation, namely replacing the traditional contact type commutator and electric brushes with electric switching components. Brushless DC motors are composed of a permanent magnent rotor, a multipole stator and positional sensors etc. all of which combine to provide many advantages such as high reliability, elimination of commutating sparking, and low mechanical noise.

2

Driving a BLDC Motor Using the HT45FM03B – C Language

BLDC Motor ADC Applications Speed Setting The speed setting method will transmit an analog voltage via the AD port to the MCU as shown in figure 2. VR is used to change the speed setting voltage value. R9 and C15 form a low pass filter circuit. DC5V HT45FM03B

R8 1k VR 50k

R9 1k

AN0 10 PB0/AN0 C15 104

Figure 2 Brief Introduction of AD The registers related to the AD conversion in the HT45FM03B are ADRL, ADRH, ADCR, ACSR. The following content shows the relevant register setting methods before an A/D conversion.

 ADCR  Select a pin by setting the PCR0~PCR2 bits 3~5 of the ADCR register.  Select a corresponding A/D channel by setting the ACS0~ACS2 bits 0~2 of the ADCR register.  Set bit 7 (START bit) in the ADCR register from low to high and then low again (0→1→0), to initiate an AD conversion.  Check if bit 6 (EOCB bit) in the ADCR register is “0” to determine if an A/D conversion process is completed after it is initiated.  ACSR The AD clock source is determined by the ADCS0~ADCS3 bits 0~4 of the ACSR register.  ADRH, ADRL These are the locations where the AD conversion results are stored. The highest 8-bits are stored in ADRH and low 4-bits in ADRL. The above is only an introduction to the A/D in the HT45FM03B. For more details refer to the datasheet and the AD application notes on Holtek’s official website.

BLDC Motor Hall Sensors Hall Sensor Detect Circuit in the HT45FM03B As shown in figure 3, the three Hall Sensor lines are connected to the INT0A~INT0C pins of external interrupt 0 in the HT45FM03B. Pins INT0A~INT0C are shared with PA4, PA5, and PA6. As long as a falling edge signal occurs from any interrupt pin, INT0A, INT0B and INT0C, an external interrupt 0 will be generated. The Hall Sensor status in the external interrupt 0 service program is thus used to execute mechanical commutation.

3

Driving a BLDC Motor Using the HT45FM03B – C Language Presently each brushless DC motor is installed using three Hall Sensors. For the HT45FM03B, there are eight input status levels, namely: 001, 010, 011, 100, 101, 110, 111 and 000, taking a 120 degree phase motor for example, among which 111 and 000 are not in use, and which will be regarded as phaseless motor when being detected. The function of the Hall Sensors lies in executing not only the motor commutation but also for positional and speed feedback. The advantage of using Hall Sensors for speed control feedback lower costs though the positioning accuracy may be lower. In the figure 3, R1, R2, R3 are pull-high resistors, R4, R5, R6 are the current limiting resistors, C7, C8, C9 are the bypass capacitors, and D1, D2, D3 are used as isolating diodes to prevent motor noise from coupling into the HT45FM03B. DC5V

R1 51k

R2 51k

SA SB SC

M

R3 51k R4 3k R5 3k R6 3k C7 104

C8 104

Phase A

D1

1N4148

Phase B

D2

1N4148

Phase C

D3

1N4148

C9 104

Figure 3 Motor Commutation Principles Brushless DC motor drivers are based on the Hall Sensor status to control the six MOSFETs that commutate the motor for motor rotation. Figure 4 illustrates these principles using six MOSFET to drive a motor. DC36V

Q1

Q3

M

Q5 A B C

Q2

Q4

Q6

Figure 4 For brushless DC motors, there are 60 and 120 degree phases while for each motor the corresponding status of the Hall Sensor and MOSFET is as follows:

4

Driving a BLDC Motor Using the HT45FM03B – C Language 60 degree brushless motor commutation truth table: Hall Sensor (SA : SB : SC) 000 001 011 111 110 100

MOSFET Tube Status Q1, Q4 on Q5, Q4 on Q5, Q2 on Q3, Q2 on Q3, Q6 on Q1, Q6 on

120 degree brushless motor commutation truth table: Hall Sensor (SA : SB : SC)

MOSFET Tube Status

101

Q1, Q4 on

001

Q5, Q4 on

011

Q5, Q2 on

010

Q3, Q2 on

110

Q3, Q6 on

100

Q1, Q6 on

Quick Motor Brake Principle The motor brake plays an important role in the positioning system. Many disadvantages exist in traditional mechanical brakes, such as increasing positioning errors with worn-down brakes. E-ABS electrical braking (electromagnetic control braking) overcomes all the problems of mechanical braking. The method of using E-ABS electric braking is as follows;

 At least two phases may simultaneously open the three upper arms or lower arms using the HT45FM03B to make the three motor phases a short circuit. Meanwhile the stator coil inside the motor will form a closed circuit, when the stator starting turning, the magenetic flux lines will be cut and thus generate the turning of the magnetic reluctance stator.

 The present brushless motor control method uses three-phase six statuses. The eight statuses (for 120 degree motors) of the three Hall Sensors are: 001, 010, 011, 100, 101, 110, 111 and 000, among which 000 and 111 are phaseless statuses. The other six statuses respectively correspond to six positions of the motor when the phaseless statuses are excluded. When the motor is driven according to the Hall Sensor order of 001→010→011→100→101→110, the motor will rotate in a forward direction. When the motor is driven in an opposite way according to the Hall Sensors, the motor will rotate in a backward direction so as to generate a braking effect with its reversing power.

5

Driving a BLDC Motor Using the HT45FM03B – C Language

BLDC Motor PWM Function HT45FM03B PWM Feature Description The HT45FM03B provides three pairs of complementary PWM outputs shared with the PC0~PC5 pins. Each PWM is named PWM0H~PWM2H whose complementary ports are named PWM0L~PWM2L. Using complementary PWM outputs increases the motor operating efficiency. A dead time function is included in the complementary PWM output in the HT45FM03B to avoid both high and low drive MOSFETS being simultaneously on, The HT45FM03B also provides an interrupt service routine entry for the PWM to generate an interrupt with the rising edge of every duty cycle. The HT45FM03B provides four PWM operation modes, 10-bit mode, (9+1)-bit mode, (8+2)-bit mode and (7+3)-bit mode, for different PWM outputs under different frequencies.

Function Setting  PWM Clock Setting The PWM clock is determined using bits 5 ~ 7 (PWMPS0~PWMPS2) of the PWMC1 register. The relation of the PWM clock fPWM and the system clock fSYS is shown in the table. PWMPS2 : PWMPS1 : PWMPS0 000 001 010 011 100 101 110 111

PWM Clock fPWM = fSYS fPWM = fSYS/2 fPWM = fSYS/3 fPWM = fSYS/4 fPWM = fSYS/5 fPWM = fSYS/6 fPWM = fSYS/7 fPWM = fSYS/8

 PWM Operating Mode Options











There are four PWM operating modes, 10-bit mode, (9+1)-bit mode, (8+2)-bit mode, (7+3)-bit mode, for different PWM outputs under different frequencies. The four modes can be chosen from the Configuration Options. Master Control for the PWM Outputs (PWMCTRL) Bit 6 (PWMCTRL) in the PWMC0 acts as the master control bit for the PWM outputs. When this bit is 1, the PWM outputs will be active and when the bit is 0, the PWM outputs will be placed into their inactive state. PWM Output Selection Method (PWMCM) The bit 2 (PWMCM) in the PWMC2 selects which method is used for the PWM outputs. When this bit is 1, the PWM outputs are controlled by the PCPWMC register and when the bit is 0, the PWM outputs will be controlled both by the PC6 and PC7 pins of I/O. PWM Output Enable Control (PWMEN) Bit 0 (PWMEN) in the PWMC0 register is the enable bit for the PWMxH output. When this bit is 1, the PWMxH output will be enabled or be disabled when the bit is 0. PWM Complementary Output Enable Control (PWMCEN) Bit 1 (PWMCEN) in PWMC0 is the enable bit for the PWMxL output. When this bit is 1, the PWMxL output will be enabled or disabled when the bit is 0. PWM Output Option Control Setting PCPWMC is the PWM output option control register. The output control options are shown in figure 5: 6

Driving a BLDC Motor Using the HT45FM03B – C Language b 7 P W M B U F

P C 5 M O D

P C 4 M O D

P C 3 M O D

P C 2 M O D

P C 1 M O D

b 0 P C 0 M O D

P C P W M C R e g is te r P C 0 o u tp u t m o d e 1 : P W M m o d e 0 : I/O m o d e P C 1 o u tp u t m o d e 1 : P W M m o d e 0 : I/O m o d e P C 2 o u tp u t m o d e 1 : P W M m o d e 0 : I/O m o d e P C 3 o u tp u t m o d e 1 : P W M m o d e 0 : I/O m o d e P C 4 o u tp u t m o d e 1 : P W M m o d e 0 : I/O m o d e P C 5 o u tp u t m o d e 1 : P W M m o d e 0 : I/O m o d e P W M 1 : P W P W p re 0 : P W P W a fte

b u ffe r e n a M b u ffe r e M w a v e fo s e n t P W M M b u ffe r d M w a v e fo r p re s e n t

b le /d is a n a b le d rm n o t u e n d s is a b le d rm u p d a P W M s u

b le p d a te d u n til te d im m e d ia te ly b c y c le

N o t im p le m e n te d , r e a d a s " 0 "

Figure 5 PCPWMC Register

 PWM Data Output Control Setting PCPWMD is the PWM data output control register, operating as shown in figure 6. b 7 P W M 2 L D

P W M 2 H D

P W M 1 L D

P W M 1 H D

P W M 0 L D

b 0 P W M 0 H D

P C P W M D

R e g is te r

P W M 0 H o n /o ff c o n tro l 1 : P W M s ig n a l 0 : in a c tiv e le v e l P W M 0 L o n /o ff c o n tro l 1 : P W M s ig n a l 0 : in a c tiv e le v e l P W M 1 H o n /o ff c o n tro l 1 : P W M s ig n a l 0 : in a c tiv e le v e l P W M 1 L o n /o ff c o n tro l 1 : P W M s ig n a l 0 : in a c tiv e le v e l P W M 2 H o n /o ff c o n tro l 1 : P W M s ig n a l 0 : in a c tiv e le v e l P W M 2 L o n /o ff c o n tro l 1 : P W M s ig n a l 0 : in a c tiv e le v e l N o t im p le m e n te d , r e a d a s " 0 "

Figure 6 PCPWMD Register

7

Driving a BLDC Motor Using the HT45FM03B – C Language  PWM Stop Output Setting The PWM stop output is controlled by bit 2 ~ bit 4 (PWMSP0~PWMSP2) in the PWMC1 register. The control methods are as follows: PWMSP2 : PWMSP1 : PWMSP0

PWM Stop Output Method

000

By software

001

By COUT / PA3 falling edge

010

By INT1 interrupt

011

By COUT / PA3 falling edge or INT interrupt When a COUT / PA3 falling edge occurs, the PWMxH and

100

PWMxL outputs are invalid. When a COUT / PA3 rising edge occurs, the PWMxH and PWMxL outputs are active. When a COUT / PA3 falling edge occurs, the PWMxH output

101

is invalid. When a COUT / PA3 rising edge occurs, the PWMxH output is active.

110 111

When a COUT / PA3 falling edge occurs, the PWMxH output is invalid. When a COUT / PA3 falling edge occurs, the PWMxH and PWMxL outputs are invalid.

Dead Time Setting  PWM Dead Time Output Enable Control (DTEN) Bit 2 (DTEN) in the PWMC0 is the enable bit to determine whether the dead time function is to be added to the PWN complementary output. When this bit is 1, the dead time function will be included in the PWM complementary output. When this bit is “0”, the dead time is disabled.

 Dead Time Clock Option The Dead Time Clock is determined using bit 6 ~ bit 7 (DTPS0~DTPS1) in the MISC register selecting the value for fD. The relation of the Dead Time clock and the system frequency is shown in the table: DTPS1 : DTPS0 00 01 10 11

Dead Time Clock fD = fSYS fD = fSYS/2 fD = fSYS/4 fD = fSYS/8

8

Driving a BLDC Motor Using the HT45FM03B – C Language  Dead Time Option The Dead Time length option is selected using bits 3 ~ bit 5 (PWMDT0~PWMDT2) in the PWMC0 register. The related values are shown in the table: PWMDT2 : PWMDT1 : PWMDT0 000 001 010 011 100 101 110 111

Dead Time Length 1/ fD 2/ fD 3/ fD 4/ fD 5/ fD 6/ fD 7/ fD 8/ fD

 Complementary PWM output Dead Time function The reason for using a dead time function in the PWM outputs in the HT45FM03B is to avoid the drivers of the same set of PWMs (PWMxH and PWMxL) from being on simultaneously due to the operating speed of the driver during output generation. For example: if the output waveform of PWMxH and PWMxL without dead time is as figure 7.

Figure 7 The problem in figure 7 is that the PWMxH bit chages to Active at T1 while the PWMxL bit changes to Inactive. At this time, should the driver be quickly turned on yet slowly turned off, the condition where both drivers, PWMxH and PWMxL are simulteneously active, may occur. The output waveform for PWMxH and PWMxL with dead time is shown in figure 8.

Figure 8

9

Driving a BLDC Motor Using the HT45FM03B – C Language For the PWMxH and PWMxL outputs with dead time as shown in figure 8, the PWMxL bit changes to Inactive at T1 while the PWMxH changes to Active at T2 so that the condition whereby the same set of drivers are simultaneously activated due to slow turning off speeds can be avoided. Some dead time options in the HT45FM03B should be noted:  The Dead Time length should not be too short otherwise the same driver pair may still be simultaneously activated.  The Dead Time length should not be too long to ensure good efficiency. A proper dead time length should be selected according to the speed of the selected driver.

PWMxH and PWMxL Output Logic Options There are two selection bits in the PWM configuration options for the PWM output logic, the PWMLEV and PWMCLEV bits. The PWMLEV bit is used to select the PWM0H~PWM2H bits that determine the logic connection of each PWM output modulation duty cycle. If the PWMLEV bit is selected as Active High, the values in the PWMnH/PWMnL registers will decide the high level output width of the PWM modulation duty cycle. If the PWMLEV bit is set as Active Low, then the values in the PWMnH/PWMnL registers will determine the low level output length of the PWM modulation duty cycle. For example: When the PWM operates in the (9+1) bits mode with fPWM = 8MHz, if the PWMLEV bit is selected as Active High and PWMH/PWML=0014H, the PWM waveform will be: PWM Cycle: 128us

1.25us

64us

64us

PWM Modulation Cycle : 64us

Figure 9 If the PWMLEV bit is selected as Active Low and PWMH/PWML=0014H, the PWM output waveform will be: PWM Cycle: 128us

1.25us

64us

64us

PWM Modulation Cycle : 64us

Figure 10

10

Driving a BLDC Motor Using the HT45FM03B – C Language PWM Data Output The data bit assignment in the PWM modulation data register, PWMnH and PWMnL, is shown in table 11: Register PWMnH PWMnL

Bit 7 D9 --

Bit 6 D8 --

Bit 5 D7 --

Bit 4 D6 --

Bit 3 D5 --

Bit 2 D4 --

Bit 1 D3 D1

Bit 0 D2 D0

Figure 11 The value in the PWM data register decides the duty ratio of the high/low level in one PWM modulation duty cycle.

PWM Control In the PWM configuration options, the PWM on/off control can be setup using the PC0~PC5 bits. When the PC0~PC5 bits are 1, the PWM output will be enabled, or else disabled when the values are 0. For example: When PC0 = 1, the PWM0H output will be on; when PC0 = 0, the PWM0H output will be off.

PWM Interrupt Control The PWM will generate an interrupt during every modulation duty cycle. The four PWM operating modes in the HT45FM03B are 10 bits mode, (9+1) bits mode, (8+2) bits mode and (7+3) bits mode. No matter what mode the PWM output is in, the PWM interrupt interval is fixed with the time of the PWM modulation duty cycle. To understand the length of an PWM interrupt interval is very important when writing the PWM interrupt service program. The following example describes the way to calculate the PWM interrupt interval. Example: When the HT45FM03B PWM is in the (9+1) bits mode, the PWM interval calculation method is: T=512/fPWM T means the length of an interrupt interval. fPWM is the PWM clock frequency from the system frequency fSYS divided by the value of bit 5 ~ bit 7 (PWMPS0~PWMPS2) in the PWMC1 register. If fSYS=8MHz and bits 5 ~ bit 7 in the PWMC1 register is 001, fPWM=fSYS/2=8MHz/2=4MHz and T=512/fPWM=512/4MHz =128　s In this condition, the PWM will generate an interrupt every 128　s.

11

Driving a BLDC Motor Using the HT45FM03B – C Language

PWM MOSFET Driving Principles There are many methods to modulate the speed of a motor using MOSFETs driven by the PWM, for example, using the IR2103 or the HT45B0C driver modules. For a better understanding about these driving principles, a drive circuit composed of transistors is provided as shown in figure 12. DC36V DC15V

D4

C18 104

1N4148

C19

R34 2k

Q8 5551

DC5V R32 1k

DC15V

COIL

R36

Q10

R35 510

R37 1k

Q28 75N75F

1k

5401

Q12 5401 Q11 5551

DC5V PWMxL

Q24 75N75F

Q9 5401

47uF/63V

PWMxH

1N4148

1k

5401

R31 510

D5

R33

Q7

R38 2k

Figure 12 In the figure 12, COIL is a motor winding and the MOSFET driver is divided into an upper arm drive circuit and a lower arm circuit. The reason why the upper arm drive circuit is much complicated in relation to the lower arm circuit is that when the upper and lower arms are conducting, the DC 36V voltage will effective be connected to the coil, therefore D4 and D5 are added to the upper arm as isolating diodes, and C19 to maintain the capacitance. Two functions are implemented within the driver circuit:

 Level shifting of the electrical switches on the upper and lower arms. On the upper arm, the electric switches is composed of R31, Q7, Q8 and R32 while the lower arm is composed of R35, Q10, Q11 and R37.

 The driver circuit should include a discharge circuit for cases where the PWM quickly turns on and off. In such cases the MOSFET may not turn off completely due to the stray capacitance on the MOSFET gates. The discharge circuit in the upper arm is composed of Q9 and R34 while the lower arm is composed of Q12 and R38.

12

Driving a BLDC Motor Using the HT45FM03B – C Language Successive Approximation PWM Modulation Algorithm There are many methods to control motor speeds using PWM techniques, such as PI modulation and so on. Here a successive approximation method is provided as follows.

 Step 1: Read the speed data and set the AD value from which the corresponding PWM output value can be checked using a table read function. The PWM output value corresponds successively with speed.

 Step 2: In the PWM interrupt service routine, compare the current PWM output value with the selected PWM value during every interval. If the current PWM output value is smaller than the selected PWM value, increase the PWM output value, or reduce it if the output value is larger than the selected value till the two value are equal to each other. In this way, any speed changes will be implemented smoothly. In short, the AD value decides the required value of speed. To achieve the required speed, it is not simply a matter of transmitting the corresponding PWM value immediately but rather to successively increase or decrease the PWM value in the PWM interrupt service routine until the final speed is reached.

Operational Amplifier and Comparator Application in the BLDC Motors HT45FM03B Comparator Features The HT45FM03B provides a comparator whose I/O pins are pin-shared respectively with PA1, PA2, and PA3 as shown in figure 13: P A 1 /C V IN P P A 2 /C V IN N P A 3 /C O U T

C M P O P

S 1 S 2

D e -b o u n c e C ir c u it

S 3

C o m p a ra to r In te rru p t

C O F 0 ~ C O F 4 C M P E N

Figure 13 Comparator Related Register Setting

 CP Enable Control Bit 3 (CMPEN) in the MISC is the comparator enable bit. When this bit is 0, the comparator is disabled. When this bit is 1, the comparator is enabled.  CP Output Selection Control Bit 5 (COUTEN) in the MISC register is the comparator output selection bit. When this bit is 0, pin PA3/COUT is used as a normal I/O. When this bit is 1, PA3/COUT is used as a comparator output.  CP Delay Enable Bit 7 (CHYSON) in the CMPC register is the comparator delay enable bit. When this bit is 0, the delay function will be disabled or else enabled when this bit is 1.  Comparator Offset Voltage Calibration Mode Selection Bit 6 (COFM) in the CMPC register is the comparator offset voltage calibration mode selection control bit. When this bit is 0, it is used as a normal comparator mode; when this bit is 1, it is used as the offset voltage calibration Mode.

13

Driving a BLDC Motor Using the HT45FM03B – C Language  Comparator Offset Voltage Calibration Input Selection Bit 5 (CRS) in the CPMC register is the comparator offset voltage calibration input selection control bit. When this bit is 0, choose CVINN as the reference voltage input or choose CVINP as the reference voltage input when this bit is 1.  Comparator Offset Voltage Adjustment Control Bit 0~bit 4 (COF0~COF4) in the CMPC register are the comparator offset voltage adjust control bits.  Comparator Interrupt Delay Time Setting The comparator interrupt delay time is decided by bits 0~ 3 (CMPDB0~CMPDB3) in the DBTC register with the corresponding reference delay time shown in the table. CMPDB3：CMPDB2：CMPDB1：CMPDB0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001~1111

Delay Time 0 4/fSYS 8/fSYS 16/fSYS 32/fSYS 64/fSYS 128/fSYS 256/fSYS 512/fSYS 1024/fSYS

Comparator Offset Voltage Calibration Steps

 Step 1: Set COFM to 1 to select the offset voltage calibration mode – here S3 is closed.  Step 2: Set CRS to 0 or 1 to select whether CVINN or CVINP is the reference voltage.  Step 3: Adjust COF0~COF4 until the COUT output voltage status changes and record the values of COF0~COF4.

 Step4: Set COFM to 0 to select the normal comparator mode. The above is only a brief introduction to the HT45FM03B comparator. For detailed information, refer to the datasheet and other comparator related application notes on Holtek’s official website.

HT45FM03B Operational Amplifier Features The HT45FM03B provides one operational amplifier of which the OPVINP, OPVINN, and OPOUT are pin-shared with PA0, PB3 and PB2. The related setting is as follows.

 OPA Enable Control Bit 7 (OPAEN) in the OPAC register is the operational amplifier enable control bit. When this bit is 0, the OPA is disabled. When this bit is 1, the OPA is enabled.

 OPA Offeset Voltage Calibration Mode Selection Bit 5 (AOFM) in the OPAC register is the OPA offset voltage calibration mode select bit. This bit is 0, it is used as a normal OPA mode. When this bit is 1, it is used as the offset voltage calibration mode.

 OPA Offset Voltage Calibration Input Selection Bit 4 (ARS) in the OPAC register is the offet voltage calibration input select bit. When this bit is 0, OPVINN is chosen as the reference voltage input. When this bit is 1, OPVINP is chosen as the voltage input.

14

Driving a BLDC Motor Using the HT45FM03B – C Language  OPA Offset Voltage Calibration Control Bits 0~3 (AOF0~AOF4) in the OPAC register is the OPA offset voltage calibration control bit.

BLDC Motor OPA and Comparator Application The HT45FM03B includes an internal comparator and an operational amplifier. The main purpose of these functions is for overcurrent protection for the motor. The comparator can offer a protection mechanism for instantaneous overcurrent and the operational amplifier can be used to monitor the operational current of the motor. The sampling current value can be acquired from the Constantant copper resistor as shown in figure 14. HT45FM03B DC5V R27 5k CPP DC36V

R28 1k5

DC5V CPP

Q1

Q3

M

Q5

OPOUT R29

A B C

Q2

Q4

R30 39k CPN

CP INTERRUPT CPN

1k C17 104

Q6 R24

Current

OPP

OPP OPOUT

1k R23 1R

AN2

OPN

16 104

R25 10k R26 2k

Figure 14 R23 in Figure 14 is a Constantant resistor whose value corresponds to the motor power consumption. Using the internal OPA in the HT45FM03B to amplify current, R24 and C16 will form a filter circuit that is connected to the OPA and uses R25 as the feedback resistor. In the HT45FM03B, the OPA output, being connected to the AD converter, allows the motor operational condition to be monitored through monitoring the current. The other current filter circuit formed by R29 and C17 is connected to inverting terminal of the internal comparator in the HT45FM03B. R27 and R28, are used to setup a reference value for the current. In the HT45FM03B, the comparator output is connected to the interrupt system. When the current value is larger then the reference value, the comparator output will switch quickly and generate an interrupt.

15

Driving a BLDC Motor Using the HT45FM03B – C Language

Application Circuit

R9 1k

DC36V

DC5V R8 1k VR 50k

DC5V

DC36V R10 36R/2W C2 104

C10 104

10k

R13 51

Phase B

R14 51

DC15V C4 104

3

IC2 7805 1 C3 100uF/25V

HT45FM03B

2 51

R16

Q6

Q5

XT1 4MHz

C5 47uF/25V

C12 104

C17 104

R30 39k CPN

DC5V

PWM2L PWM2H PWM1L

DC5V RES

SA SB SC

C6 104 GND

DC5V

28 27 26 25 24 23 22 21 20 19 18 17 16 15

R29 1k

R22 100k

60NF60

R21 100k

60NF60

Current

Phase C

51

R15

PB6/AN6/[INT0C] PB7/AN7/TMR0/TMR1 PA4/INT0A PA5/INT0B PA6/INT0C PA7/INT1 PD3/OSC2 PD2/OSC1 VDD/AVDD PD1/RES PD0/PFD PC5/PWM2L PC4/PWM2H PC3/PWM1L

R28 1k5

C11 104 CB

CT

R27 5k CPP

DC5V

Q4

Q3

DC36V

R20 100k

60NF60

R19 100k

60NF60

R26 2k

OPN

PB5/AN5/[INT0B] PB4/AN4/[INT0A] PA3/COUT PA2/CVINN PA1/CVINP PA0/OPVINP PB3/AN3/OPVINN PB2/AN2/OPOUT PB1/AN1 PB0/AN0 VSS/AVSS PC0/PWM0H PC1/PWM0L PC2/PWM1H

IC3

3

IC1 7815 1

BB

BT

OPOUT R25

1 2 3 4 CPN 5 CPP 6 OPP OPN 7 OPOUT 8 9 10 11 12 13 14

Q2

Q1

AN0 GND PWM0H PWM0L PWM1H

C1 1000uF/50V

AN0 C15 104

OPP

C16 104

60NF60

R17 100k

60NF60

R7 100k RES

1k

R24

C13 104

R23 1R

R11 51

Phase A

R12 51 R18 100k

DC15V

D4

C18 104

D6

PWM0H

DC15V C20 104

D8

PWM1H

DC15V C22 104

PWM2H

1N4148

C19 47uF/63V

R32 1k 1N4148

C21 47uF/63V

R40 1k 1N4148

C23 47uF/63V

R48 1k

DC5V

DC5V

DC5V

R31 510

R39 510

R47 510

Q7 5401

Q8 5551

Q13 5401

Q14 5551

Q19 5401

Q20 5551

R34 2k

R42 2k

R50 2k

R33 1k

R41 1k

R49 1k

D5

D7

D9

SA SB SC

1N4148

AT

BT

Phase A

Q9 5401

1N4148

Q15 5401

Phase B

CT

R2 51k

DC5V

Phase C

Q21 5401

1N4148

R1 51k

PWM0L

PWM1L

PWM2L

R3 51k R4 3k R5 3k R6 3k

DC5V

DC15V

R37 1k

DC5V

DC15V

R45 1k

C8 104

DC5V

DC15V

R53 1k

C7 104

R35 510

R43 510

Q10

5401

Q11 5551

Q16

5401

Q17 5551

Q22

5401

R38 2k

R46 2k

D2

D1

1N4148

1N4148

1N4148

R51 510

Phase A

D3

R54 2k

Phase B

Q23 5551

Phase C C9 104

R36

1k

R44

1k

R52

1k

M

AB

Q12 5401

BB

Q18 5401

CB

Q24 5401

16

C14 104

Current

AT

AB

Current

Figure 15

2

Driving a BLDC Motor Using the HT45FM03B – C Language

Software Flowchart Main Flowchart

Figure 16

17

Driving a BLDC Motor Using the HT45FM03B – C Language PWM Interrupt Subroutine

Figure 17

Hall Sensor Interrupt

Figure 18

18

Driving a BLDC Motor Using the HT45FM03B – C Language CP Interrupt

Figure 19

Description This example uses the HT45FM03B to generate the PWM signals for controlling a brushless DC motor through the PC0~PC5 outputs. The brushless DC motor in this example uses 120 degree phase. The main program will start by determining whether the WDT has overflowed or whether it is a power-on reset. If it is a power-on reset then clear the specific function registers. The program follows up with an initialization to the I/O, CP, OP, PWM and Interrupts and then acquires the current state of the Hall Sensors to control the PWM. Finally the program will activate an AN0 conversion and modulate the motor speed according to the converted voltage value from AN0. If an overcurrent is detected, the PWM output will be disabled. In the PWM interrupt service program, compare the current PWM output value with the PWM set value. If the current PWM value is smaller than its sett value, increase the PWM output value, otherwise decrease the value until the output value is equal to the set value. In this way, the speed will then smoothy increase or decrease. Read the Hall Sensor state from the Hall Sensor interrupt service program and enable the corresponding PWM output according to the current state. In the comparator interrupt service program, the only way to prevent an overcurrent situation is to disable the PWM output.

Conclusion The application content has described the functional components within the HT45FM03B as applied to a brushless DC motor with reference circuits and software programs. Users may adapt the required control circuitry and programs according to their actual requirements.

19