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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Features

NAND Flash Memory MLC FNNL41A

Features

Figure 1: 48-Pin TSOP Type 1

• Organization – Page size: x8: 2,112 bytes (2,048 + 64 bytes) Block size: 128 pages (256K + 8K bytes) – Device size: 8Gb: 4,096 blocks • READ performance – Random READ: 50µs – Sequential READ: 25ns • WRITE performance – PROGRAM PAGE: 650µs (TYP) – BLOCK ERASE: 2ms (TYP) • Endurance: 5,000 PROGRAM/ERASE cycles (with ECC and invalid block mapping) • Industry-standard basic NAND Flash command set • Operation status byte provides a software method of detecting: – PROGRAM/ERASE/READ operation completion – PROGRAM/ERASE pass/fail condition – Write-protect status • Ready/busy# (R/B#) signal provides a hardware method of detecting PROGRAM, READ, or ERASE cycle completion • WP# signal: Entire device hardware write protect • Staggered power-up sequence: Issue RESET (FFh) command

Options • Density:1 – 8Gb (single-die stack) – 16Gb (dual-die stack) – 32Gb (quad-die stack) • Device width: – x8 • Configuration: # of die # of CE# 1 1 2 2 4 4

# of R/B# 1 2 4

I/O Common Common Common

• VCC: 2.7–3.6V • First-generation die • Package:

– 48-pin TSOP type I OCPL2 (lead-free plating) • Operating temperature: Commercial (0°C to 70°C) Notes:1. For part numbering and markings, see Figure 2 on page 2. 2. OCPL = off-center parting line.

Source: 09005aef82b4174b/PDF: 09005aef82af83db SpecTek_8gb_nand_l41a_mlc__1.fm - Rev. A 4/07 EN

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SpecTek reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by SpecTek without notice. Products are only warranted by SpecTek to meet SpecTek production data sheet specifications.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Part Numbering Information

Part Numbering Information SpecTek® NAND Flash devices are available in several different configurations and densities (see Figure 2).

Figure 2: Part Number Chart FN N

L41A

4G

K

3 W G - xx

SpecTek Memory

Grade

FN, FT, FB = SpecTek

(see Table 1 below)

Product Marking

Package Functionality G = 1 Die CE1 Functional Only 1 = 2 Die CE1 Functional Only 2 = 2 Die CE1 and CE2 Functional 3 = 2 Die CE2 Functional Only 4 = 4 Die CE1 and CE2 Functional 5 = 4 Die CE1 Functional Only 6 = 4 Die CE2 Functional Only

N = SpecTek M, T = Blocked Mark

Product Family and Generation L41A = NAND 8 Gig MLC 1st-Generation Die

Functional Density

Package Type

Single die = 8.0Gb, 7.8Gb,

W = 48-lead TSOP Type 1 (CPL) PB-Free

7.5Gb, 6.0Gb, and 4.0Gb

P = 48-lead TSOP Type 1 (OCPL) PB-Free

Dual-die stack = 16.0Gb, 15.8Gb, 14.0Gb, 12.0Gb,

Voltage

and 8.0Gb

3 = 3.3V

Quad-die stack = 32.0Gb, 31.8Gb, 30.0Gb, 24.0Gb,

Configuration

and 16.0Gb

K = x8

Table 1:

Flash Product Type Definitions

Product Type

Name

Description

-AT

One-Time Programmable

-AA

No READ ID feature

Device may be programmed multiple times. The programming method must follow some strict guidelines. Download those guidelines at: www.spectek.com/pdfs/SP_TN-00-01.pdf The products meet the full datasheet specifications except for the READ ID (90h). The values needed by this command should be forced upon the part number of the device.

Valid Part Number Combinations After building the part number from the part numbering chart, verify that the part number is valid by contacting SpecTek Sales at: 208-363-5716, or one of the distributors listed at: www.spectek.com/menus/distributors.aspx.

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SpecTek reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Table of Contents

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 RANDOM DATA READ 05h-E0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 TSOP Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

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SpecTek reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory List of Figures

List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40:

48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Assignment (Top View) 48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Array Organization for FNNL41AxxKxxG, FNNL41AxxKxx2, and FNNL41AxxKxx3 . . . . . . . . . .11 Array Organization for FNNL41AxxKxx4, FNNL41AxxKxx5, and FNNL41AxxKxx6 . . . . . . . . . .12 READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AC Waveforms During Power Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 READ Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 PROGRAM Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PROGRAM PAGE Operation with RANDOM DATA INPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 48-Pin TSOP Type 1 (Package Code W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 48-Pin TSOP Type 1 OCPL (Package Code P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Source: 09005aef82b4174b/PDF: 09005aef82af83db SpecTek_8gb_nand_L41A_r1LOF.fm - Rev. A 4/07 EN

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SpecTek reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved.

Advance ®

8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory List of Tables

List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20:

Flash Product Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Signal/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Operational Example (8Gb x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Array Addressing: FNNL41AxxKxxG, FNNL41AxxKxx2, and FNNL41AxxKxx3 . . . . . . . . . . . . . .11 Array Addressing: FNNL41AxxKxx4, FNNL41AxxKxx5, and FNNL41AxxKxx6. . . . . . . . . . . . . . .12 Max Number of Blocks Available. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Device DC and Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 AC Characteristics – Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 AC Characteristics – Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory General Description

General Description NAND Flash technology provides a cost-effective solution for applications requiring high-density, solid-state storage. FNNL41AxxxxWG is a 4,096 block MLC NAND Flash memory device. FNNL41AxxxxW2 is a two-die stack that operates as a single 8,192 block device. FNNL41AxxxxW4/5/6 are four-die stacked devices that operate as two independent 8,192 block devices providing a total storage capacity of 16,384 blocks in a single, space-saving package. SpecTek NAND Flash devices include standard NAND Flash features as well as new features designed to enhance system-level performance. These NAND Flash devices utilize multi-level cell (MLC) technology. Each memory cell stores 2 bits of information. SpecTek NAND Flash devices use a highly multiplexed 8-bit bus (I/O[7:0]) to transfer data, addresses, and instructions. The five command signals (CLE, ALE, CE#, RE#, WE#) implement the NAND Flash command bus interface protocol. Two additional signals control hardware write protection (WP#) and monitor device status (R/B#). This hardware interface creates a low-pin-count device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities without board redesign. Each FNNL41A device contains 4,096 blocks. Each block is subdivided into 128 programmable pages. Each page consists of 2,112 bytes (x8). The pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device. The 64-byte area is typically used for error management functions. The contents of each 2,112-byte page can be programmed in tPROG (TYP), and an entire 264K-byte/132K-word block can be erased in tBERS (TYP). On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. PROGRAM/ ERASE endurance is specified at 5,000 cycles when appropriate error correction code (ECC) and error management are used.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory General Description

Figure 3: NAND Flash Functional Block Diagram VCC

I/O [7:0] I/O Control

VSS

Address Register Status Register

Command Register

CE#

Column Decode

ALE WE#

Row Decode

CLE Control Logic

RE# WP#

Data Register

R/B#

Figure 4: Pin Assignment (Top View) 48-Pin TSOP Type 1 x8 NC NC NC NC NC R/B2# R/B# RE# CE# CE2# NC VCC VSS NC NC CLE ALE WE# WP# DNU DNU DNU NC NC

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x8 1● 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

7

DNU NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC DNU VCC VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC DNU DNU

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Table 2:

8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory General Description

Signal/Pin Descriptions

Symbol

Type

Function

ALE

Input

CE#, CE2#

Input

CLE

Input

RE#

Input

WE#

Input

WP#

Input

I/O[7:0] FNNL41AxxK

I/O

R/B#, R/B2#

Output

VCC VSS NC

Supply Supply –

DNU

–

Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register on the rising edge of WE#. When address information is not being loaded, ALE should be driven LOW. Chip enable: Gates transfers between the host system and the NAND Flash device. After the device starts a PROGRAM or ERASE operation, CE# can be de-asserted. For the W2 and P2 packages, CE# controls the first 4,096 blocks of memory; CE2# controls the second 4,096 blocks of memory. For the W4 and P4 packages, CE# controls the first 8,192 blocks of memory; CE2# controls the second 8,192 blocks. See “Bus Operation” on page 13 for additional operational details. For packages types WG, PG, W1, P1, W5, and P5, only CE# is valid. For packages types W3, P3, W6, and P6, only CE2# is valid. Command latch enable: When CLE is HIGH, information is transferred from I/O[7:0] to the on-chip command register on the rising edge of WE#. When command information is not being loaded, CLE should be driven LOW. Read enable: RE# is used to gate transfers from the NAND Flash device to the host system. Write enable: WE# is used to gate transfers from the host system to the NAND Flash device. Write protect: WP# protects against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when the WP# is LOW. Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs. Ready/busy: An open-drain, active-LOW output that uses an external pull-up resistor. R/B# is used to indicate when the chip is processing a PROGRAM or ERASE operation. R/B# is also used during READ operations to indicate when data is being transferred from the array into the serial data register. When these operations have completed, R/B# returns to the High-Z state. In the W2 and P2 packages, R/B# is for the 4,096 blocks of memory enabled by CE#; R/B2# is for the 4,096 blocks of memory enabled by CE2#. In the W4 and P4 packages, R/B# is for the 8,192 blocks of memory enabled by CE#; R/B2# is for the 8,192 blocks of memory enabled by CE2#. For packages types WG, PG, W1, P1, W5, and P5, only R/B# is valid. For packages types W3, P3, W6, and P6, only R/B2# is valid. VCC: The VCC pin is the power supply pin. VSS: The VSS pin is the ground connection. No connect: NC pins are not internally connected. These pins can be driven or left unconnected. Do not use: These pins must be left disconnected.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Architecture

Architecture These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins. This provides a memory device with a low pin count. The internal memory array is accessed on a page basis. For reads, a page of data is copied from the memory array into the data register. After being copied to the data register, data is output sequentially, byte by byte. The memory array is programmed on a page basis. After the starting address is loaded into the internal address register, data is sequentially written to the internal data register up to the end of a page. After all of the page data has been loaded into the data register, array programming is started.

Addressing NAND Flash devices do not contain dedicated address pins. Addresses are loaded using a 5-cycle sequence, as shown in Figure 6 on page 11. Table 4 on page 11 presents address functions internal to the device. See Figure 5 on page 10 for additional memory mapping and addressing details.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Addressing

Figure 5: Memory Map x8 Blocks 8Gb: BA[18:7]

0

1

2

• • • • • • • • • • • • 4,095

Pages PA[6:0]

0

1

2

• • •

Bytes CA[11:0]

0

1

2

• • • • • • • • • • • • • • • • • • •

127

2,047

•••

2,111

Spare area

Table 3: Blocks 0 0 0 ... 4,095 4,095

Operational Example (8Gb x8) Page

Min Address in Page

Max Address in Page

Out-of-Bounds Addresses in Page

0 1 2 ... 126 127

0x00000000 0x00010000 0x00020000 ... 0x7FFFE0000 0x7FFFF0000

0x0000083F 0x0001083F 0x0002083F ... 0x7FFFE083F 0x7FFFF083F

0x00000840–0x00000FFF 0x00010840–0x00010FFF 0x00020840–0x00020FFF ... 0x7FFFE0840–0x7FFFE0FFF 0x7FFFF0840–0x7FFFF0FFF

Notes: 1. As shown in Table 4 on page 11, the high nibble of ADDRESS cycle 2 has no assigned address bits; however, these 4 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they have no address bits assigned to them. 2. Block address concatenated with page address = row address.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Addressing

Figure 6: Array Organization for FNNL41AxxKxxG, FNNL41AxxKxx2, and FNNL41AxxKxx3 2,112 bytes I/O 7 Data Register

2,048

Notes: 1. 2. 3.

I/O 0

128 pages = 1 block (128K + 4K) bytes

1 Block

4,096 blocks per device

Table 4:

64

1 page

= (2K + 64 bytes)

1 block

= (2K + 64) bytes x 128 pages = (256K + 8K) bytes

1 device

= (2K + 64) bytes x 128 pages x 4,096 blocks = 8,448 Mb

For FNNL41Axxxxx1, the 4,096 block array organization shown applies to only chip enable 1 (CE#). For FNNL41Axxxxx2, the 4,096 block array organization shown applies to each chip enable (CE# and CE2#). For FNNL41Axxxxx3, the 4,096 block array organization shown applies to only chip enable 2 (CE2#).

Array Addressing: FNNL41AxxKxxG, FNNL41AxxKxx2, and FNNL41AxxKxx3

Cycle

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

First Second Third Fourth Fifth

CA7 LOW BA73 BA15 LOW

CA6 LOW PA6 BA14 LOW

CA5 LOW PA5 BA13 LOW

CA4 LOW PA4 BA12 LOW

CA3 CA11 PA3 BA11 LOW

CA2 CA10 PA2 BA10 BA18

CA1 CA9 PA1 BA9 BA17

CA0 CA8 PA0 BA8 BA16

Notes: 1. 2. 3.

Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. If CA11 is “1,” then CA[10:6] must be “0.” This keeps a MAX limit of 2,112 bytes addressed per page. Plane select bit.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Addressing

Figure 7: Array Organization for FNNL41AxxKxx4, FNNL41AxxKxx5, and FNNL41AxxKxx6 Die 0

Die 1

2,112 bytes

2,112 bytes I/O 7

2,048

Data Register

2,048

64

I/O 0

64

1 page = (2K + 64 bytes)

1 block

8,192 blocks per die

1 block

1 block = (2K + 64) bytes x 128 pages = (256K + 1 8K) bytes 1 block block 1 die

= 4,224Mb x 4,096 blocks = 8,448Mb

1 device

= 8,448Mb x 2 die = 16,896Mb

Notes: 1. Die 0: BA19 = 0 2. Die 1: BA19 = 1 3. For the 16,384 block, the 8,192 block array organization shown applies to each chip enable (CE# and CE2#)

Table 5:

.

Array Addressing: FNNL41AxxKxx4, FNNL41AxxKxx5, and FNNL41AxxKxx6

Cycle

O/I7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

First Second Third Fourth Fifth

CA7 LOW BA7 BA15 LOW

CA6 LOW PA6 BA14 LOW

CA5 LOW PA5 BA13 LOW

CA4 LOW PA4 BA12 LOW

CA3 CA11 PA3 BA11 BA193

CA2 CA10 PA2 BA10 BA18

CA1 CA9 PA1 BA9 BA17

CA0 CA8 PA0 BA8 BA16

Notes: 1. CAx = column address; PAx = page address; BAx = block address. 2. If CA11= “1,” thenCA[10:6] must be “0.” This keeps a MAZX limit of 2,112 bytes addressed per page. 3. Die address boundary: “0” = 0–8Gb, “1” = 8Gb–16Gb.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Bus Operation

Bus Operation The bus on the FNNL41A devices is multiplexed. Data I/O, addresses, and commands all share the same pins. Addresses and commands are always supplied on I/O[7:0]. The command sequence normally consists of a COMMAND LATCH cycle, an ADDRESS LATCH cycle, and a DATA cycle—either READ or WRITE.

Control Signals CE#, WE#, RE#, CLE, ALE, and WP# control Flash device READ and WRITE operations. On the FNNL41Axxxxx1, CE# controls a 4,096 block array, CE2# is not applicable. On the FNNL41Axxxxx2, CE# and CE2# each control independent 4,096 block arrays. On the FNNL41Axxxxx3, CE2# controls a 4,096 block array, CE# is not guaranteed. On the FNNL41Axxxxx4, CE# and CE2# each control independent 8,192 block arrays. On the FNNL41Axxxxx5, CE# controls a 8,192 block array, CE2# is not guaranteed. On the FNNL41Axxxxx6, CE2# controls a 8,192 block array, CE# is not guaranteed. CE2# functions the same as CE# for its own array; all operations described for CE# also apply to CE2#. CE# is used to enable a device. When CE# is LOW and the device is not in the busy state, the Flash memory will accept command, data, and address information. When the device is not performing an operation, CE# is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption. See Figure 13 on page 38 and Figure 16 on page 39 for examples of CE# “Don’t Care” operations. The CE# “Don’t Care” operation allows the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus. One device can be programmed while another is being read. A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring.

Table 6:

Max Number of Blocks Available Part Number

CE#

FNNL41AxxxxG FNNL41Axxxx1 FNNL41Axxxx2 FNNL41Axxxx3 FNNL41Axxxx4 FNNL41Axxxx5 FNNL41Axxxx6

4,096 max 4,096 max 4,096 max not guaranteed 8,192 max 8,192 max not guaranteed

CE2# not applicable not guaranteed 4,096 max 4,096 max 8,192 max not guaranteed 8,192 max

Commands Commands are written to the command register on the rising edge of WE# when: • CE# and ALE are LOW, and • CLE is HIGH, and • the device is not busy.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Bus Operation

As exceptions, the device accepts the READ STATUS and RESET commands when busy. Commands are transferred to the command register on the rising edge of WE# (see Figure 7 on page 35). Commands are input on I/O[7:0] only.

Address Input Addresses are written to the address register on the rising edge of WE# when: • CE# and CLE are LOW, and • ALE is HIGH. Addresses are input on I/O[7:0] only. Bits not part of the address space must be LOW. The number of ADDRESS cycles required for each command varies. Refer to the command descriptions to determine addressing requirements. See Table 8 on page 18.

Data Input Data is written to the data register on the rising edge of WE# when: • CE#, CLE, and ALE are LOW, and • the device is not busy. Data is input on I/O[7:0]. See Figure 9 on page 36 for additional data input details.

READs After a READ command is issued, data is transferred from the memory array to the data register from the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after the transfer is complete. When data is available in the data register, it is clocked out of the device by RE# going LOW. See Figure 12 on page 37 for detailed timing information. The READ STATUS (70h) command or the R/B# signal can be used to determine when the device is ready.

Ready/Busy# The R/B# output provides a hardware method of indicating the completion of PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for proper operation. The signal is typically HIGH, and it transitions to LOW after the appropriate command is written to the device. The signal’s open-drain driver enables multiple R/B# outputs to be OR-tied. The READ STATUS command can be used in place of R/B#. Typically, R/B# would be connected to an interrupt pin on the system controller (see Figure 8 on page 15). On the FNNL41Axxxxx1, FNNL41Axxxxx2, and FNNL41Axxxxx3, R/B# provides a status indication for the 4,096 block section enabled by CE#, and R/B2# does the same for the 4,096 block section enabled by CE2#. R/B and R/B2# can be tied together, or they can be used separately to provide independent indications for each 4,096 block section. On the FNNL41Axxxxx4, FNNL41Axxxxx5, and FNNL41Axxxxx6, R/B# provides a status indication for the 8,192 block section enabled by CE#, and R/B2# does the same for the 8,192 block section enabled by CE2#. R/B and R/B2# can be tied together, or they can be used separately to provide independent indications for each 8,192 block section The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The actual value used for Rp depends on system timing requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10- to 90-percent points on the R/B# waveform, rise time is approximately two time constants (TC).

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Bus Operation

TC = R × C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.

The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# signal and the total load capacitance. Figure 9 on page 16 and Figure 10 on page 16 depict approximate Rp values for a circuit load of 100pF. The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCC. 3.2V V CC ( MAX ) – V OL ( MAX ) Rp = --------------------------------------------------------------- = -------------------------8mA + Σ IL I OL + Σ IL Where Σ IL is the sum of the input currents of all devices tied to the R/B# pin.

Figure 8: READY/BUSY# Open Drain

Rp VCC

R/B# Open drain output

IOL

GND Device

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Figure 9:

tFall

8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Bus Operation

and tRise 3.50 3.00 2.50 V

tFall tRise

2.00 1.50 1.00 0.50 0.00 -1

0

2

4

0

2

4

TC

6 Vcc 3.3

and tRise are calculated at 10 percent–90 percent points. is dependent on external capacitance and resistive loading and output transistor impedance. 3. tRise is primarily dependent on external pull-up resistor and external capacitive loading. 4. tFall ≈ 10ns at 3.3V. 5. See TC values in Figure 11 on page 16 for approximate Rp value and TC.

Notes: 1. 2.

tFall

tRise

Figure 10: IOL vs. Rp 3.50mA 3.00mA 2.50mA 2.00mA 1.50mA 1.00mA 0.50mA 0.00mA 0

2,000

4,000

6,000

8,000

10,000

12,000

Rp IOL at 3.60V (MAX)

Note:

To calculate Rp value, see page 15.

Figure 11: TC vs. Rp 1.20µs 1.00µs T

800ns 600ns 400ns 200ns 0ns 0

2kΩ

4kΩ

6kΩ Rp

8kΩ

10kΩ

12kΩ

IOL at 3.60V (MAX) RC = TC C = 100pF

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Table 7:

8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Bus Operation

Mode Selection RE#

WP#1

L

H

X

H

L

H

X

H

L

L

H

H

L

H

L

H

H

L

L

L

H

H

Data input

L

L

L

H

X

Sequential read and data output

X X X X X

X X X X X

X X X X H

X X X X X

CLE

ALE

CE#

H

L

L

WE#

H X X X X

X H H L 0V/VCC

Mode Read mode

Command input Address input

Write mode

Command input Address input

During read (busy) During program (busy) During erase (busy) Write protect Standby

Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby. 2. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

Command Definitions Table 8:

Command Set Command Number of Data Cycles Command Valid Cycle 1 Address Cycles Required1 Cycle 2 During Busy

Operation PAGE READ READ for INTERNAL DATA MOVE RANDOM DATA READ READ ID READ STATUS PROGRAM PAGE RANDOM DATA INPUT BLOCK ERASE RESET

00h 00h 05h 90h 70h 80h 85h 60h FFh

5 5 2 1 – 5 2 3 –

No No No No No Yes Yes No No

30h 35h E0h – – 10h – D0h –

No No No No Yes No No No Yes

Notes 2 3

4

Notes: 1. Indicates required DATA cycles between COMMAND cycle 1 and COMMAND cycle 2. 2. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and PROGRAM for INTERNAL DATA MOVE. 3. RANDOM DATA READ command is limited to use within a single page. 4. RANDOM DATA INPUT command is limited to use within a single page.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

READ Operations PAGE READ 00h-30h To enter READ mode while the device is in operation, write the 00h command to the command register, then write 5 ADDRESS cycles, and conclude with the 30h command. To determine the progress of the data transfer from the Flash array to the data register (tR), monitor the R/B# signal, or, alternatively, issue a READ STATUS command. If the READ STATUS command is used to monitor the data transfer, the user must reissue the READ (00h) command to receive data output from the data register. After the READ command has been reissued, pulsing the RE# line will result in outputting data, starting from the initial column address. A serial page read sequence outputs a complete page of data. After 30h is written, the page data is transferred to the data register, and R/B# goes LOW during the transfer. When the transfer to the data register is complete, R/B# returns HIGH. At this point, data can be read from the device. Starting from the initial column address and going to the end of the page, read the data by repeatedly pulsing RE# at the maximum tRC rate (see Figure 12).

Figure 12: PAGE READ Operation CLE

CE#

WE#

ALE tR R/B#

RE#

I/Ox

00h

30h

Address (5 cycles)

Data output (Serial access)

Don‘t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

RANDOM DATA READ 05h-E0h The RANDOM DATA READ command enables the user to specify a new column address so the data at single or multiple addresses can be read. The random read mode is enabled after a normal PAGE READ (00h-30h sequence). Random data can be output after the initial page read by writing an 05h-E0h command sequence along with the new column address (2 cycles). The RANDOM DATA READ command can be issued without limit within the page. Only data on the current page can be read. Pulsing RE# outputs data sequentially (see Figure 13).

Figure 13: RANDOM DATA READ Operation tR R/B#

RE#

I/Ox

00h

Address (5 cycles)

30h

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Data output

20

05h

Address (2 cycles)

E0h

Data output

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

READ ID 90h The READ ID command is used to read the 5 bytes of identifier codes programmed into the devices. The READ ID command reads a 5-byte table that includes manufacturer’s ID, device configuration, and part-specific information. See Table 9 on page 22, which shows complete listings of all configuration details. Writing 90h to the command register puts the device into the read ID mode. The command register stays in this mode until another valid command is issued (see Figure 14).

Figure 14: READ ID Operation CLE

CE#

WE# tAR ALE

RE# tWHR I/Ox

90h

00h

tREA Byte 1

Byte 0

Byte 2

Byte 3

Byte 4

Address, 1 cycle

Note:

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See Table 9 on page 22 for byte definitions.

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Table 9:

8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

Device ID and Configuration Codes Options

Byte 0 Byte 1 FNNL41AxxK3xG FNNL41AxxL3xG FNNL41AxxK3x1 FNNL41AxxK3x2 FNNL41AxxK3x3 FNNL41AxxL3x1 FNNL41AxxL3x2 FNNL41AxxL3x3 FNNL41AxxK3x4 FNNL41AxxK3x5 FNNL41AxxK3x6 FNNL41AxxL3x4 FNNL41AxxL3x5 FNNL41AxxL3x6 Byte 2 Number of die per CE Cell type Reserved Interleaved operations between multiple die Cache programming Byte value

Byte 3 Page size Spare area size (bytes) Block size (w/o spare) Organization Serial access (MIN) Byte value

Manufacturer ID SpecTek Device ID 4,096 block x8 3.3v 4,096 block x16 3.3v 4,096 block x8 3.3v 8,192 block x8 3.3v 4,096 block x8 3.3v 4,096 block x16 3.3v 8,192 block x16 3.3v 4,096 block x16 3.3v 8,192 block x8 3.3v 16,384 block x8 3.3v 8,192 block x8 3.3v 8,192 block x16 3.3v 16,384 block x16 3.3v 8,192 block x16 3.3v

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

0

0

1

0

1

1

0

0

2Ch

1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 1 1 1 0 0 0 1 1 1 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1

1 1 1 1 1 1 1 1 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1

D3h C3h D3h D3h D3h C3h C3h C3h D5h D5h D5h C5h C5h C5h

0 0

0 1

00b 01b 00b 01b 0b 1b

1 2 MLC 1 Not supported Supported Not supported FNNL41AxxK3xG FNNL41AxxK3x1 FNNL41AxxK3x2 FNNL41AxxK3x3 FNNL41AxxK3x4 FNNL41AxxK3x5 FNNL41AxxK3x6

0

1

0

1

0 1 1 1 1

0 0

0 0

1 1

0 0

1 1

0 0

0 0

1b 94h 94h

1

1

0

1

0

1

0

1

D5h

0

1

1

01b 1b

1 1

10b 0b 0xxx0b 1xxx0b A5h 65h

2KB 64B 256KB x8 50ns/30ns 25ns FNNL41AxxK3xx FNNL41AxxL3xx

Byte 4 Reserved Planes per CE#

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Value1 Notes

I/O7

1

0

0 0 1 1 0

0 1

1 1

2

0 0

0 0 0 0

0

22

1

0 0

1 1

0

0

2 2 2 2 2 2

00b 01b

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Table 9:

8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

Device ID and Configuration Codes (Continued) Options

Plane size Reserved Byte value

I/O7

I/O5

I/O4

1

1

0

0 0 0

1 1

1 1

0 0

0 0

1 1

0 0

0 0

110b 0b 64h 64h

0

1

1

0

1

0

0

0

68h

4Gb FNNL41AxxK3xG FNNL41AxxK3x1 FNNL41AxxK3x2 FNNL41AxxK3x3 FNNL41AxxK3x4 FNNL41AxxK3x5 FNNL41AxxK3x6

I/O3

I/O2

I/O1

I/O0

Value1 Notes

I/O6

2

Notes: 1. b = binary; h = hex. 2. The FNNL41AxxK3x1, FNNL41AxxK3x2, and FNNL41AxxK3x3 device ID codes reflect the configuration of each 8Gb section.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

READ STATUS 70h These NAND Flash devices have an 8-bit status register that the software can read during device operation. Table 10 on page 24 describes the status register. After a READ STATUS (70h) command, all READ cycles are from the status register until a new command is given. Changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to start a new READ cycle to see these changes. In devices that have more than one die sharing a common CE# connection, the READ STATUS (70h) command reports the status of the die that was last addressed. While monitoring the read status to determine when the transfer from the Flash array to the data register (tR) is complete, the user must reissue the READ (00h) command to make the change from STATUS to DATA. After the READ command has been reissued, pulsing the RE# line will result in outputting data, starting from the initial column address.

Table 10: Status Register Bit Definition SR Bit

Program Page

Page Read

Block Erase

0

Pass/fail

–

Pass/fail

1 2 3 4 5

X – – – Ready/busy

– – – – Ready/busy

– – – – Ready/busy

6

Ready/busy

Ready/busy

Ready/busy

7

Write protect

Write protect

Write protect

Note:

Definition 0 = Successful PROGRAM/ERASE 1 = Error in PROGRAM/ERASE X = Don’t care 0 0 0 0 = Busy 1 = Ready 0 = Busy 1 = Ready 0 = Protected 1 = Not protected

Status register bit 0 reports a “1” if a TWO-PLANE PROGRAM operation fails on one or both planes. Status register bit 1 reports a “1” if a TWO-PLANE PROGRAM PAGE CACHE MODE operation fails on one or both planes. Use TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) to determine the plane on which the operation failed.

Figure 15: Status Register Operation CE# tCLR CLE WE# tREA RE# I/Ox

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70h

Status output

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

PROGRAM Operations PROGRAM PAGE 80h-10h SpecTek NAND Flash devices are inherently page-programmed devices. Within a block, the pages must be programmed consecutively from the least significant page address to the most significant page address. Random page address programming is prohibited. These MLC NAND Flash devices do not support partial-page programming operations— a page can only be programmed one time before requiring an ERASE operation. If a RESET (FFh) command is issued during a PROGRAM PAGE operation while R/B# is LOW, the data in the shared memory cells being programmed will become invalid. Interrupting a programming operation on one page will corrupt the data in another page within the block being programmed. SERIAL DATA INPUT 80h PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command into the command register, followed by 5 ADDRESS cycles, then the data. Serial data is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h) command is written after the data input is complete. The control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects “1s” that are not successfully written to “0s.” R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS (70h) and the RESET (FFh) commands are the only commands valid during the programming operation. Bit 5 of the status register will reflect the state of R/B#. When the device reaches ready, read bit 0 of the status register to determine if the programming operation passed or failed (see Figure 16). The command register stays in read status register mode until another valid command is written to it. RANDOM DATA INPUT 85h After the initial data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuance of the PAGE WRITE (10h) command. See Figure 17 for the proper command sequence.

Figure 16: PROGRAM and READ STATUS Operation tPROG R/B# I/Ox

80h Address (5 cycles)

DIN

70h

10h

Status I/O 0 = 0 PROGRAM successful I/O 0 = 1 PROGRAM error

Figure 17: RANDOM DATA INPUT tPROG R/B# I/Ox

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80h

Address (5 cycles)

DIN

85h

25

Address (2 cycles)

DIN

10h

70h

Status

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Command Definitions

BLOCK ERASE Operation BLOCK ERASE 60h-D0h Erasing occurs at the block level. The FNNL41AxxxxxG, FNNL41Axxxxx2, and FNNL41Axxxxx4 devices have 4,096, 8,192, and 16,384 blocks, respectively. These blocks are organized into 128 pages per block, 2,112 bytes per page (2,048 + 64 bytes) for x8 devices. For x8 devices, each block is 264K bytes (256K + 8K bytes). The BLOCK ERASE command operates on one block at a time (see Figure 18). Three cycles of addresses [PA0–BA18] are required for single-die and dual-die devices, and 3 cycles of addresses [PA0–BA19] are required for quad-die devices. Although [PA0– PA6] are loaded, they are a “Don’t Care” and are ignored for BLOCK ERASE operations, since these bits normally specify the page address within a block. See Figure 5 on page 10 for addressing details. The actual command sequence is a two-step process. The ERASE SETUP (60h) command is first written to the command register. Then 3 cycles of addresses are written to the device. Next, the ERASE CONFIRM (D0h) command is written to the command register. At the rising edge of WE#, R/B# goes LOW and the control logic automatically controls the timing and erase-verify operations. R/B# stays LOW for the entire tBERS erase time. The READ STATUS (70h) command can be used to check the status of the error. When bit 6 = 1, the ERASE operation is complete. Bit 0 indicates a pass/fail condition where 0 = pass (see Figure 18, and Table 10 on page 24).

Figure 18: BLOCK ERASE Operation CLE

CE#

WE#

ALE tBERS R/B#

RE#

I/Ox

60h

Address input (3 cycles)

D0h

70h

Status I/O 0 = 0 ERASE successful I/O 0 = 1 ERASE error Don‘t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory

RESET Operation RESET FFh The RESET command is used to put the memory device into a known condition and to abort a command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data register and cache register contents are marked invalid. If a RESET command is issued during any type of programming operation while R/B# is LOW, the data in the shared memory cells being programmed will become invalid. Interrupting any programming operation on one page will corrupt the data in another page within the block being programmed. The status register contains the value E0h when WP# is HIGH; otherwise, it is written with a 60h value. R/B# goes low for tRST after the RESET command is written to the command register (see Figure 19 and Table 11). The RESET command must be issued to all CE#s after a power-on. The device will be busy for a maximum of 1ms.

Figure 19: RESET Operation CLE

CE#

tWB WE#

tRST R/B#

FFh

I/Ox

RESET command

Table 11: Status Register Contents After RESET Operation Condition

Status

WP# HIGH WP# LOW

Ready Ready and write protected

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Hex

1 0

1 1

1 1

0 0

0 0

0 0

0 0

0 0

E0h 60h

27

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory

WRITE PROTECT Operation It is possible to enable and disable PROGRAM and ERASE commands using WP#. Figures 20 through 23 illustrate the setup time (tWW) required from WP# toggling until a PROGRAM or ERASE command is latched into the command register. After command cycle 1 is latched, WP# must not be toggled until the command is complete and the device is ready (status register bit 5 is “1”).

Figure 20: ERASE Enable WE# tWW I/Ox

60h

D0h

WP# R/B#

Figure 21: ERASE Disable WE# tWW I/Ox

60h

D0h

WP# R/B#

Figure 22: PROGRAM Enable WE# tWW I/Ox

80h

10h or 15h

WP# R/B#

Figure 23: PROGRAM Disable WE# tWW I/Ox

80h

10h or 15h

WP# R/B#

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Error Management

Error Management SpecTek NAND Flash devices are specified to have a minimum of 3,936 valid blocks (NVB) out of every 4,096 total available blocks for every 8Gb. This means the devices may have blocks that are invalid when they are shipped. An invalid block is one that contains one or more bad bits. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, replacement, and error correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the Flash device. Before NAND Flash devices are shipped from SpecTek, they are erased. The factory identifies invalid blocks before shipping by programming data other than FFh (x8) into the first spare location (column address 2,048) of the first page (page 0) or the second page (page 1) of each bad block. System software should check the first spare address on the first 2 pages of each block prior to performing any erase or programming operations on the Flash device. A bad block table can then be created, allowing system software to map around these areas. Factory testing is performed under worst-case conditions. Because blocks marked “bad” may be marginal, it may not be possible to recover these bad block markings if the block is erased. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the Flash device, certain precautions must be taken: • Always check status after a PROGRAM or ERASE operation. • Under typical use conditions, utilize a minimum of 4-bit ECC per 528 bytes of data. • Use a bad-block replacement algorithm.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Electrical Characteristics

Electrical Characteristics Table 12: Absolute Maximum Ratings by Device Voltage on any pin relative to VSS. Parameter/Condition Voltage input VCC supply voltage Storage temperature Short circuit output current, I/Os

Symbol

Min

Max

Unit

VIN VCC TSTG

–0.6 –0.6 –65 –

+4.6 +4.6 +150 5

V V °C mA

FNNL41Axxx3 FNNL41Axxx3

Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 13: Recommended Operating Conditions Parameter/Condition Operating temperature VCC supply voltage Ground supply voltage

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Commercial FNNL41Axxx3

30

Symbol

Min

Typ

Max

Unit

TA VCC VSS

0 2.7 0

– 3.3 0

+70 3.6 0

°C V V

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Electrical Characteristics

VCC Power Cycling SpecTek NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. (The WP# signal permits additional hardware protection during power transitions.) When VCC reaches 2.3V for a 3V device, a minimum of 100µs should be allowed for the Flash device to initialize before any commands are executed (see Figure 24 for the states of signals during VCC power cycling). The RESET command must be issued to all CE#s after the NAND Flash device is powered on. Each CE# will be busy for a maximum of 1ms after a RESET command is issued.

Figure 24: AC Waveforms During Power Transitions 3V device: ≈ 2.3V

3V device: ≈ 2.3V

VCC

CLE tCS

CE#

WP#

LOCK1

WE#

100µs (MIN)

ALE

RE#

FFh

I/Ox

1ms (MAX) R/B#

Don’t Care

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Undefined

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Electrical Characteristics

Table 14: Device DC and Operating Characteristics Parameter

Conditions

Sequential read current Program current Erase current Standby current (TTL) Standby current (CMOS) Input leakage current Output leakage current Input high voltage Input low voltage (all inputs) Output high voltage Output low voltage Output low current (R/B#)

t

Symbol

Min

Max

Unit

ICC1

–

40

mA

ICC2 ICC3 ISB1 ISB2 ILI ILO VIH

– – – – – – 0.8 x VCC

40 40 1 350 ±10 ±10 VCC + 0.3

mA mA mA µA µA µA V

VIL VOH VOL IOL (R/B#)

–0.3 2.4 – 8

0.2 x VCC – 0.4 –

V V V mA

t

RC = RC (MIN); CE# = VIL; IOUT = 0mA – – CE# = VIH; WP# = 0V/VCC CE# = VCC - 0.2V; WP# = 0V/VCC VIN = 0V to VCC VOUT = 0V to VCC I/O [7:0], I/O [15:0], CE#, CLE, ALE, WE#, RE#, R/B#, WP# – IOH = –400µA IOL = 2.1mA VOL = 0.4V

Table 15: Valid Blocks Parameter Valid block number

Symbol

Part Number

Min

Max

Unit

Notes

NVB

FxxL41A 8G FxxL41A 78 FxxL41A 75 FxxL41A 6G FxxL41A 4G FxxL41A HG FxxL41A F8 FxxL41A EG FxxL41A CG FxxL41A 8G FxxL41A 32 FxxL41A 31 FxxL41A 30 FxxL41A 24 FxxL41A HG

3,936 3,836 3,690 2,952 1,968 7,872 7,772 6,888 5,904 3,936 15,744 15,644 14,760 11,808 7,872

4,096 4,096 4,096 4,096 4,096 8,192 8,192 8,192 8,192 8,192 16,384 16,384 16,384 16,384 16,384

blocks

1, 2, 3

Notes: 1. Invalid blocks are blocks that contain more bad bits than can be corrected by required ECC. See “Error Management” on page 29 for device ECC requirements. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from factory. 3. Each CE# has a maximum of 320 invalid blocks.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Electrical Characteristics

Table 16: Capacitance Description

Symbol

Part Number

Max

Unit

Notes

CIN

FxxL41AxxxxxG FxxL41Axxxxx2 FxxL41Axxxxx4 FxxL41AxxxxxG FxxL41Axxxxx2 FxxL41Axxxxx4

10 20 40 10 20 40

pF

1, 2

pF

1, 2

Input capacitance

Input/output capacitance (I/O)

COUT

Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: Tc = 25°C; f = 1 MHz; VIN = 0V.

Table 17: Test Conditions Parameter Input pulse levels FxxL41Axxx3 Input rise and fall times Input and output timing levels Output load FxxL41Axxx3 (VCC = 3.3V ± 10%) FxxL41Axxx3 (VCC = 3.3V ± 10%)

Value

Notes

0.0V to 3.3V 5ns VCC/2 1 TTL GATE and CL = 50pF 1 TTL GATE and CL = 100pF

1 1

Notes: 1. Verified in device characterization; not 100 percent tested.

Source: 09005aef82b4174b/PDF: 09005aef82af83db SpecTek_8gb_nand_l41a_mlc__4.fm - Rev. A 4/07 EN

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Electrical Characteristics

Table 18: AC Characteristics – Command, Data, and Address Input Parameter

Symbol

ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# setup time

t

ADL ALH t ALS tCH t CLH tCLS t CS t DH tDS tWC tWH tWP tWW t

Min

Max

Unit

Notes

70 5 10 5 5 10 15 5 10 25 10 15 30

– – – – – – – – – – – – –

ns ns ns ns ns ns ns ns ns ns ns ns ns

1

Notes: 1. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input.

Table 19: AC Characteristics – Normal Operation Parameter

Symbol

Min

Max

Unit

ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Output High-Z to RE# LOW Data transfer from Flash array to data register READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH to RE# LOW

tAR

10 – – 10 15 0 – 25 – 10 15 100 – 5 12 20 – – 60

– 25 30 – – – 50 – 15 – – – 100 – – – 5/10/500 100 –

ns ns ns ns ns ns µs ns ns ns ns ns ns ns ns ns µs ns ns

tCEA tCHZ tCLR tCOH tIR tR tRC tREA t

REH

tRHOH tRHW tRHZ tRLOH tRP t

RR

tRST tWB tWHR

Notes

1

1

2 2, 3

Notes: 1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. 2. The first time the RESET (FFh) command is issued while the device is idle, the device goes busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5µs. 3. Do not issue a new command during tWB, even if R/B# is ready.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Electrical Characteristics

Table 20: PROGRAM/ERASE Characteristics Parameter Description

Typ

Max

Unit

Notes

NOP BERS t PROG

– 2 650

1 10 2,200

cycles ms µs

1

t

Number of partial page programs BLOCK ERASE operation time PROGRAM PAGE operation time Notes: 1. One total to the same page.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Timing Diagrams Figure 25: COMMAND LATCH Cycle CLE tCLS tCS

tCLH tCH

CE# tWP WE# tALS

tALH

ALE tDS I/Ox

tDH

COMMAND

Don‘t Care

Figure 26: ADDRESS LATCH Cycle CLE

CE#

tCLS tCS tWC tWP

tWH

WE# tALS tALH ALE tDS tDH I/Ox

Col add 1

Col add 2

Row add 1

Row add 2 Don‘t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Figure 27: INPUT DATA LATCH Cycle CLE tCLH

CE# tALS

tCH

ALE tWC tWP

tWP

tWP

WE# tWH tDS tDH

tDS tDH

DIN 0

I/Ox

DIN 1

tDS tDH

DIN Final1 Don’t Care

Notes: 1. DIN Final = 2,111 (x8) or 1,055 (x16).

Figure 28: SERIAL ACCESS Cycle After READ tCEA CE# tREA

tREA tRP

tCHZ

tREA

tREH

tCOH

RE# tRHZ

tRHZ tRHOH

DOUT

I/Ox tRR

DOUT

DOUT

tRC

R/B# Don’t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Figure 29: READ STATUS Cycle tCLR CLE tCLS tCLH

tCS CE# tCH

tWP WE#

tCHZ

tCEA tWHR

tCOH

tRP

RE#

tRHZ tRHOH tDS tDH

tIR

tREA Status output

70h

I/Ox

Don’t Care

Figure 30: PAGE READ Operation CLE tCLR CE# tWC WE# tWB tAR ALE tR

tRC

tRHZ

RE# tRR I/Ox

00h

Col add 1

Col add 2

Row add 1

Row add 2

Row add 3

tRP DOUT N

30h

DOUT N+1

DOUT M

Busy R/B# Don‘t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Figure 31: READ Operation with CE# “Don’t Care” CLE CE# RE# ALE tR R/B#

WE# I/Ox

00h

Address (5 cycles)

30h

Data output tCEA

CE# tREA

tCHZ tCOH

RE#

Don’t Care

Out

I/Ox

Figure 32: RANDOM DATA READ Operation CLE tCLR CE#

WE# tWB

tWHR

tAR

ALE tR

tRC

tREA

RE# tRR I/Ox

00h

Col add 1

Col add 2

Row add 1

Row add 2

Row add 3

DOUT N

30h

Column address N

DOUT N+1

05h

Col add 1

Col add 2

E0h

DOUT M

DOUT M+1

Column address M Busy

R/B# Don’t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Figure 33: READ ID Operation CLE

CE#

WE# tAR ALE

RE# tWHR 90h

I/Ox

tREA

00h

Byte 1

Byte 0

Byte 2

Byte 3

Byte 4

Address, 1 cycle

Note:

See Table 6 on page 21 for actual values.

Figure 34: PROGRAM Operation with CE# “Don’t Care” CLE

CE#

WE#

ALE

I/Ox

80h

Address (5 cycles)

Data

input

tCS

Data

input

10h

tCH

CE# tWP WE#

Source: 09005aef82b4174b/PDF: 09005aef82af83db SpecTek_8gb_nand_l41a_mlc__4.fm - Rev. A 4/07 EN

Don‘t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Figure 35: PROGRAM PAGE Operation CLE

CE# tWC

tADL

WE# tWB

tPROG

ALE

RE#

I/Ox

80h

Col add 1

Col add 2

Row add 1

Row add 2

Row add 3

DIN N

SERIAL DATA INPUT command

DIN M

10h

70h

1 up to m Byte PROGRAM serial input command

Status

READ STATUS command

R/B# x8 device: m = 2,112 bytes Don‘t Care

Figure 36: PROGRAM PAGE Operation with RANDOM DATA INPUT CLE

CE# tWC

tADL

tADL

WE# tWB tPROG ALE

RE# I/Ox

80h

Col Col Row Row Row add 1 add 2 add 1 add 2 add 3

SERIAL DATA INPUT command

DIN N

DIN N+1

Serial input

85h

Col Col add 1 add 2

RANDOM DATA Column address INPUT command

DIN N

DIN N+1 Serial input

10h PROGRAM command

Status

70h READ STATUS command

R/B# Don‘t Care

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Timing Diagrams

Figure 37: BLOCK ERASE Operation CLE

CE# tWC WE# tWB

tWHR

ALE

RE# tBERS I/Ox

60h

Row add 1

Row add 2

Row add 3

Row address

Status

D0h

70h

ERASE command

READ STATUS command Busy

R/B#

I/O0 = 0, Pass I/O0 = 1, Fail

AUTO BLOCK ERASE SETUP command

Don’t Care

Figure 38: RESET Operation CLE

CE#

tWB WE#

tRST R/B#

I/Ox

FFh RESET command

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory TSOP Package Information

TSOP Package Information Figure 39: 48-Pin TSOP Type 1 (Package Code W) 20.00 ±0.25 18.40 ±0.08 48

0.25 for reference only 0.50 TYP for reference only

1

Mold compound: Epoxy novolac Plated lead finish: 100% Sn Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side.

12.00 ±0.08

0.27 MAX 0.17 MIN

24

25

0.25 0.10 0.15

+0.03 -0.02

Gage plane

See detail A 1.20 MAX

0.10

+0.10 -0.05 0.50 ±0.1 0.80

Detail A

Note:

Source: 09005aef82b4174b/PDF: 09005aef82af83db SpecTek_8gb_nand_l41a_mlc__4.fm - Rev. A 4/07 EN

All dimensions are in millimeters.

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory TSOP Package Information

Figure 40: 48-Pin TSOP Type 1 OCPL (Package Code P) 0.25 for reference only 0.50 for reference only

20.00 ±0.25 18.40 ±0.08 48 1

Mold compound: Epoxy novolac Plated lead finish: 100% Sn Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side.

12.00 ±0.08

0.27 MAX 0.17 MIN

24

25

0.10 0.15

+0.03 -0.02

See detail A

0.25

1.20 MAX

Gage plane 0.10

+0.10 -0.05 0.50 ±0.1 0.80

Detail A

Note:

All dimensions are in millimeters.

®

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8Gb, 16Gb, and 32Gb: x8/x16 NAND Flash Memory Revision History

Revision History Rev A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 03/07 • Initial Release.

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