Multi-Cycle CPU Organization

Multi-Cycle CPU Organization Datapath and Control © Mark Redekopp, All rights reserved Single-Cycle CPU Datapath 0 1 A + B [31:26] Control MemR...
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Multi-Cycle CPU Organization Datapath and Control

© Mark Redekopp, All rights reserved

Single-Cycle CPU Datapath 0 1

A

+ B [31:26]

Control

MemRead & MemWrite ALUOp[1:0] MemtoReg RegDst ALUSrc

5 [20:16]

5

PC

0 1

5

I-Cache [15:0]

RegDst 16

Read Reg. 1 # Read Reg. 2 # Write Reg. # Write Data

MemRead Read data 1

0 Zero

Read data 2

0

Res.

Read Data

Register File Sign Extend

Addr.

1

32 INST[5:0]

ALUOp[1:0] © Mark Redekopp, All rights reserved

Branch

ALU

[15:11]

Instruc.

PCSrc

RegWrite [25:21]

Addr.

Sh. Left 2

+

4

Write Data

ALUSrc

D-Cache ALU control

MemWrite

1

MemtoReg

Multicycle CPU Implementation • Single cycle CPU sets the clock period according to the longest instruction execution time • Rather than making every instruction “pay” the worst case time, why not make each instruction “pay” just for what it uses – Example: Pay Parking • Parking meters: Cost proportional to time spent • Flat fee parking lot: One price no matter the time

• Multicycle CPU implementation breaks instructions into smaller, shorter sub-operations – Clock period according to the longest sub-operation

• Instructions like ADD or Jump with few sub-operations will take fewer cycles while more involved instructions like LW will take more cycles

© Mark Redekopp, All rights reserved

Single vs. Multi-Cycle CPU • Single Cycle CPU design makes all instructions wait for the full clock cycle and the cycle time is based on the SLOWEST instruction • Multi-cycle CPU will break datapath into sub-operations with the cycle time set by the longest sub-operation. Now instructions only take the number of clock cycles they need to perform their sub-ops. add Decode / Reg. Fetch

Instruc. Fetch

ALU

lw

Memory Access

Write Result

time

CPI=1

time © Mark Redekopp, All rights reserved

lw

Memory Access

REG.

ALU

REG.

Decode / Reg. Fetch

REG.

Instruc. Fetch

REG.

Single-Cycle

Write Result

CPI=n

Multi-cycle

Single-/Multi-Cycle Comparison CLK R-Type

BEQ SW LW

CLK Fetch / Reg. Read / ALU Op / Reg. Write Fetch / Reg. Read / Update PC Fetch / Reg. Read / Calc. Addr / Mem Write.

Wasted

Wasted

Wasted

Fetch / Reg. Read / Calc. Addr. / Mem Read / Reg. Write

In single-cycle implementations, the clock cycle time must be set for the longest instruction. Thus, shorter instructions waste time if they require a shorter delay.

© Mark Redekopp, All rights reserved

R-Type

Fetch

Reg. Read

ALU Op

Reg. Write

Next Instruc.

BEQ

Fetch

Reg. Read

Update PC

SW

Fetch

Reg. Read

Calc. Addr.

Mem Write

Next Instruc.

LW

Fetch

Reg. Read

Calc. Addr.

Mem Read

Reg. Write

Next Instruc.

In multi-cycle CPU, each instruction is broken into separate short (and hopefully timebalanced) sub-operations. Each instruction takes only the clock cycles needed, allowing shorter instructions to finish earlier and have the next instruction start.

Sharing Resources in Single-Cycle • Single-cycle CPU required multiple: – Adders/ALU – Memories (instruc. & data)

[31:26] [25:21]

5 [20:16]

PC

0 1

Addr.

[15:11]

Dout. Din. Mem. Addr.

Mem. Write Data

© Mark Redekopp, All rights reserved

5

0

1

5

Shared Mem.

RegDst [15:0]

because all operations occurred during a single clock cycle which limited our control of the flow of data signals

Control

16

Read Reg. 1 # Read Reg. 2 # Write Reg. # Write Data

Read data 1 Read data 2

Register File Sign Extend

Sharing Resources in Multicycle CPU • Any resource needed in different clock cycles (time steps) can be shared/re-used – 1 ALU and 2 adders in single-cycle CPU can be replaced by just the one ALU (& some muxes) – Separate instruction and data memories can be replaced with a single memory

© Mark Redekopp, All rights reserved

Temporary Registers • Another implication of a multi-cycle implementation is that data may be produced in one cycle (step) but consumed in a later cycle • This may necessitate saving/storing that value in a temporary register – If the producer can keep producing across multiple cycles (i.e. is not needed for another subsequent operation) then we can do without the temporary register – If the producer is needed for another operation in a subsequent cycle, then we must save the value it produced in a temporary register

© Mark Redekopp, All rights reserved

Temporary Registers • If the producer can keep producing across multiple cycles (i.e. is not needed for another subsequent operation) then we can do without the temporary register • If the producer is needed for another operation in a subsequent cycle, then we must save the value it produced in a temporary register

CLK Producer (ALU)

Branch Target Branch Target

Consumer (PC)

Temporary Register not Necessary CLK Producer (ALU) Temp Reg. Consumer (PC)

Branch Target

Next Value

Branch Target Branch Target

Temp Register Necessary © Mark Redekopp, All rights reserved

Instruction Register [31:26]

Control

• Do we need a register to store instruction

[25:21]

5 [20:16]

– In single-cycle CPU: NO Addr.

0

Read Reg. 2 # Write Reg. #

1

5

I-Cache RegDst

– In multi-cycle CPU: YES

Write Data

Read data 2

Register File

16

Sign Extend

Addr. Read Data

Write Data

Memory

Multicycle CPU Datapath

Instruction Reg.

0 1

Data read/write address from ALU

© Mark Redekopp, All rights reserved

Read data 1

Single-Cycle CPU Datapath PC

• Single memory may need to be used to read or write data after reading instruction. We must buffer / save the instruction somewhere (i.e. IR)

[15:11]

Instruc.

[15:0]

PC

• Separate instruction memory + stable PC value during entire cycle = Stable instruction value for entire execution of instruction

5

Read Reg. 1 #

• Do temporary registers need a write enable (i.e. do we need IRwrite signal? • Unless it is acceptable for the register to be written on every clock cycle, then we do need a write enable – Based on our design, we only write the IR after the cycle we read the instruction and not on other cycles…thus we need an IRwrite © Mark Redekopp, All rights reserved

IRWrite

More on Temporary Registers

D

Q

CLK

Instruc. Reg.

Multi-Cycle CPU Datapath 0

PC

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[25:21]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

Res.

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Zero

0

Register File Sign Extend

30

ALU

Read Data

26

Reg Write

IRWrite

MemWrite

MemRead

PCWrite

PC[31:28]

ALU control

Target Reg.

1

Sh. Left 2

32

2

Multi-Cycle CPU Datapath PCSource TargetWrite

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[25:21]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

Write Reg. # Write Data

MemtoReg

0

0 Read data 1

Read data 2

1

16

4

Res.

1 2

Register File

3 ALUSelB

Sign Extend

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Zero

0

1 [15:0]

30

ALU

Read Data

RegDst

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

ALUSelA

PC

PCWrite

0

ALU control

Target Reg.

1

Sh. Left 2

32

2

Single vs. Multi-Cycle CPU Single-Cycle CPU

Multi-Cycle CPU

Single LONG clock

Several SHORT clocks

No sharing of resources

Sharing resources possible

ALU & 2 separate adders

Single ALU does all three jobs

Separate instruction & data memory

Single unified memory

No need for any temp. register

Need for temp. registers like IR

PCWrite Unneeded

PCWrite Needed

Control unit not an FSM

Control Unit is an FSM

© Mark Redekopp, All rights reserved

Instruction Fetch + PC Increment PCSource TargetWrite

0

0 1

Addr.

Write Data

Memory

Instruc[31:26] Instruc[25:0]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

ALUSelA

[25:21]

Reg Write

RegDst]

26

1

Write Reg. # Write Data

MemtoReg

0

Read data 2

1

16

4

Res.

1 2 3 ALUSelB

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

1

Sh. Left 2

32

Zero

0

Register File Sign Extend

Target Reg.

0 Read data 1

1 [15:0]

30

ALU

Read Data

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

Instruc.

PC

PCWrite

New PC (PC + 4)

ALU control

New PC (PC + 4)

2

R-Type Execution PCSource TargetWrite

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[25:21]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

Write Reg. # Write Data

MemtoReg

0

Read data 2

1 Op. A Op. B

16

4

Res.

1 2 3 ALUSelB

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

1

Sh. Left 2

32

Zero

0

Register File Sign Extend

Target Reg.

0 Read data 1

1 [15:0]

30

ALU

Read Data

RegDst]

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

ALUSelA

PC

PCWrite

0

ALU control

Result

2

LW Execution PCSource TargetWrite

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[rs]

Read Reg. 1 #

[rt]

Read Reg. 2 # 0

Instruc. Reg.

[rd]

1

Write Reg. # Write Data

MemtoReg

0 [15:0]

Read data 2

Register File

1 Base Reg

16

Res.

0 4

1

Offset

2 3

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

1

Sh. Left 2

32

Zero

ALUSelB Sign Extend

Target Reg.

0 Read data 1

1 Read Data

30

ALU

Read Data

RegDst]

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

ALUSelA

PC

PCWrite

0

ALU control

Eff. Addr.

2

SW Execution PCSource TargetWrite

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[25:21]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

Write Reg. # Write Data

MemtoReg

0

Read data 2

Register File

1 Base Reg

16

Write Data

© Mark Redekopp, All rights reserved

1

Sh. Left 2

32

Zero Res.

0 4

1

Offset

2 3 ALUSelB

Sign Extend

Target Reg.

0 Read data 1

1 [15:0]

30

ALU

Read Data

RegDst]

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

ALUSelA

PC

PCWrite

0

32

Sh. Left 2 [5:0]

ALU control

Eff. Addr.

2

BEQ Execution Step 1 PCSource TargetWrite

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

Write Reg. # Write Data

MemtoReg

0

Read data 2

1

16

Res.

1 2

Register File

3 ALUSelB

Sign Extend

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Zero

0 4

Target Reg.

1

Sh. Left 2

32

Target PC (PC+4+Offset)

0 Read data 1

1 [15:0]

30

ALU

Read Data

[25:21]

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

0

RegDst]

PC[31:28]

ALUSelA

PC

PCWrite

PC+4 (PC was already incremented in fetch step)

ALU control

2

BEQ Execution Step 2 PCSource TargetWrite

0

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[25:21]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

Write Reg. # Write Data

MemtoReg

0

Read data 2

1 Op. A Op. B

16

4

Res.

1 2 3 ALUSelB

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Zero

0

Register File Sign Extend

Target Reg.

1

Sh. Left 2

32

2

0 Read data 1

1 [15:0]

30

ALU

Read Data

RegDst]

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

ALUSelA

PC

PCWrite

Target PC (PC+4+Offset)

ALU control

PCWriteCond

Jump Execution PCSource TargetWrite

Jump PC

0

0 1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

[25:21]

Read Reg. 1 #

[20:16]

Read Reg. 2 # 0

Instruc. Reg.

[15:11]

1

Write Reg. # Write Data

MemtoReg

0

0 Read data 1

Read data 2

1

16

4

Res.

1 2

Register File

3 ALUSelB

Sign Extend

32

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Zero

0

1 [15:0]

30

ALU

Read Data

RegDst]

26

Reg Write

IRWrite

MemWrite

MemRead

IorD

PC[31:28]

ALUSelA

PC

PCWrite

(PC[31:28] || IR[25:0] || 00)

ALU control

Target Reg.

1

Sh. Left 2

32

2

Controlling the Datapath • Now we need to implement the logic for the control signals • This will require an FSM for our multi-cycle CPU (since we will have sub-operations or steps to execute each instruction)

© Mark Redekopp, All rights reserved

Multi-Cycle CPU IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0

1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

Control Signal Explanation Signal Name

Effect when Deasserted

Effect when Asserted

MemRead

None

Read data from memory

MemWrite

None

Write to data memory

ALUSelA

Select the PC value

Selects the rs register value

RegDst

Register to write is specified by rt field

Register to write is specified by rd field

RegWrite

None

Register file will write the specified register

MemtoReg

Reg. file write data comes from ALU

Reg. file write data comes from memory read data

IorD

PC is used as address to memory

ALU output is used as address to memory

IRWrite

None

Memory read data is written to IR

© Mark Redekopp, All rights reserved

Control Signal Explanation Signal Name

ALUSelB

ALUOp

PCSource

© Mark Redekopp, All rights reserved

Value

Effect

00

Selects the rt register value

01

Selects the constant 4

10

Selects the sign extended lower 16-bits of IR

11

Selects the sign extended and shifted lower 16-bits of IR

00

ALU performs an ADD operation

01

ALU performs a SUB operation

10

The function code field of instruction will determine ALU op.

00

Selects the ALU output to pass back to the PC input

01

Selects the target register value to pass back to the PC input

10

Selects the jump address value to pass back to the PC input

Generating a State Diagram • Start with states to fetch instruction, increment PC, & decode it – These are common to any instruction because at this point we don’t know what instruction it is

• Once decoded use a separate sequence of states for each instruction – One state for each sub-operation of each instruction

• Goal is to find state breakdown that leads to short, equal timed steps – Short: Shorter the time delay of the step => Faster clock rate – Equal-timed: Clock cycle is set by the slowest state; if the delays in states are poorly balanced, some states will have to pay a longer delay even though they don’t need it © Mark Redekopp, All rights reserved

Multi-cycle CPU FSM Reset

0

MemRead ALUSelA=0 IorD=0 IRWrite ALUSelB=01 ALUOp=00 PCSource=00 PCWrite

Instruc. Fetch

Instruc. Decode + Reg. Fetch

1 ALUSelA=0 ALUSelB=11 ALUOp=00 TargetWrite

(Op=‘JMP’) (Op=‘BEQ’)

2

Memory Access

Write-back

Execution

ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1

Mem. Addr. Computation

Memory Access

3 MemRead ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1

4

8

6

MemRead ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1 MemtoReg=1 RegDst=0 RegWrite

© Mark Redekopp, All rights reserved

5

MemWrite ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1

ALUSelA=1 ALUSelB=00 ALUOp=10

Write-back 7

ALUSelA=1 ALUSelB=00 ALUOp=10 RegDst=1 MemtoReg=0 RegWrite

9 ALUSelA=1 ALUSelB=00 ALUOp=01 PCWriteCond PCSource=01

Branch Completion

PCWrite PCSource=10

Jump Completion

State 0 = Fetch IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

MemRead ALUSelA=0 IorD=0 IRWrite ALUSelB=01 ALUOp=00 PCSource=00 PCWrite

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

State 1 = Decode / Reg. Fetch IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

0

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

[5:0]

MemWrite

MemRead

1

Zero

Instruc[31:26]

Addr.

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

0

ALUSelA=0 ALUSelB=11 ALUOp=00 TargetWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

Questions • After state 0 (fetch) we store the instruction in the IR, after state 1 when we fetch register operands do we need to store operands in temp reg’s (e.g. AReg, BReg)? • Do we need RegReadA, RegReadB control signals?

© Mark Redekopp, All rights reserved

LW/SW State 2

ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1

IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

LW State 3 IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

MemRead ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

LW State 4 IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

MemRead ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1 MemtoReg=1 RegDst=0 RegWrite

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

SW State 5 IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

MemWrite ALUSelA=1 ALUSelB=10 ALUOp=00 IorD=1

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

R-Type State 6 IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

ALUSelA=1 ALUSelB=00 ALUOp=10

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

R-Type State 7 IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

ALUSelA=1 ALUSelB=00 ALUOp=10 RegDst=1 MemtoReg=0 RegWrite

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

Questions • For R-Type or LW… – Can we turn on RegWrite one state earlier?

– Can we set the RegDst signal earlier?

© Mark Redekopp, All rights reserved

BEQ State 8 IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

ALUSelA=1 ALUSelB=00 ALUOp=01 PCWriteCond PCSource=01

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2

Jump State 9 PCWrite PCSource=10

IorD

PCSource TargetWrite ALUOp ALUSelB ALUSelA

PCWrite

Control Unit

PCWriteCond

0

1

Instruc[31:26]

Addr.

Write Data

Memory

Instruc[25:0]

0

Instruc. Reg.

[15:11]

1

0 1 [15:0] 16

Read Reg. 1 # Read Reg. 2 #

[20:16]

30

Write Reg. # Write Data

0 Read data 1

Read data 2

1

4

1 2

32

3

Sh. Left 2 [5:0]

© Mark Redekopp, All rights reserved

Res.

0

Register File Sign Extend

Zero

ALU

Read Data

[25:21]

26

Reg Write

Zero

[5:0]

MemWrite

MemRead

0

PC[31:28] RegDst MemtoReg

PC

PCWrite

IRWrite

ALU Ctrl

Target Reg.

1

Sh. Left 2

32

2