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ECE 274 - Digital Logic

Digital Design

Lecture 4

Combinational Logic Design

Lecture 4 „

Combination Logic Design Process

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Common Combinational Components „ „

Decoders Multiplexers

Counting the number of possible Boolean functions of two variables.

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Digital Design

Digital Design

Combinational Logic Design: Multiple Output Circuits

Combinational Logic Design: Combination Logic Design Process

The 16 possible Boolean functions of two variables.

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Digital Design

Digital Design

Combinational Logic Design: Design Process „

Combinational Logic Design: Design Process

Number of 1’s counter „

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Step 1: Capture the Function

We want to design a circuit that counts the number of 1s present on 3 inputs a, b, c, and outputs that number in binary using 2 outputs, y and z.

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Digital Design

Digital Design

Combinational Logic Design: Design Process

Combinational Logic Design: Design Process

Step 2: Convert to Equations

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Step 3: Implement as Gate Based Circuit

y = a’bc + ab’c + abc’ + abc

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„

a’bc + ab’c + ab(c’+c) -> a’bc + ab’c + ab

a b c a b c

z = a’b’c + a’bc’ + ab’c’ + abc

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y

a b

a b c a b c a b c a b c

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Digital Design

Digital Design

Combinational Logic Design: Not Really a Quiz

Combinational Logic Design: Examples

Use the Process Above: „

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Create a 4-bit prime number detector. The circuit has four inputs, N3, N2, N1, and N0 that correspond to a 4-bit number (N3 is the most significant bit) and one output labeled P that outputs a 1 when the input is a prime number, 0 otherwise.

Example 1: „

Create a 4-bit squared number detector. The circuit has four inputs, N3, N2, N1, and N0 that correspond to a 4-bit number (N3 is the most significant bit) and one output labeled S that outputs a 1 when the input is the square of a positive integer, 0 otherwise.

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Digital Design

Digital Design

Combinational Logic Design: Examples

Combinational Logic Design: Examples

Example 2: „

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Example 3: „

Create a greater than 5 detector. The circuit has four inputs, N3, N2, N1, and N0 that correspond to a 4-bit number (N3 is the most significant bit) and one output labeled G that outputs a 1 when the input is greater than 5, 0 otherwise. 11

z

A network router connects multiple computers together and allows them to send messages to each other. If two or more computers send messages simultaneously, they collide and the messages must be resent. Using the combinational design process, create a collision detection circuit for a router that connects 4 computers. The circuit has 4 inputs labeled M0 through M3 that are 1 when the corresponding computer is sending a message and 0 otherwise. The circuit has one output labeled C that is 1 when a collision is detected and 0 otherwise. 12

Digital Design

Digital Design

Got Decoder?

Decoder Properties „

Need to activate only one product: „ „

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Decoder

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1: activated (product released) 0: not activated

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Only one slot can be activated at a time.

i1 0 0 1 1

d0

No data inputs n control bits 2n outputs

i0

d1

2x4 Decoder

i1

d2 d3

i0 0 1 0 1

d3 0 0 0 1

d2 0 0 1 0

d1 0 1 0 0

d0 1 0 0 0

d0 d0 0 0

i0 d1 i1 d2 d3

0

0

1 0

0

0

1

d0 i0 d 1 1 i1 d 2 0

1 0

d0 i0 d 1 0 i1 d 2 1

d3 0

0

d3 0

d1

0

1 1

d0 i0 d 1 0 i1 d 2 0

d2

d3 1

d3

(a) i1

i0

(b)

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Digital Design

Digital Design

Decoder with Enable

Combinational Logic Design

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0

d0 1 1

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i0 d1 0 i1 d2 0

1 e d3

0 e d3

1 (a)

0

Using a 6x64 decoder to interface a microprocessor and a column of lights for a New Year’s Eve display. The microprocessor sets e=1 when the last minute countdown begins, and then counts down from 59 to 0 in binary on the pins i5..i0. Note that the microprocessor should never output 60, 61, 62 or 63 on i5..i0, and thus those outputs of the decoder go unused.

Microprocessor

1

d0 0 i0 d1 0 i1 d2 0

(b)

(a) e=1: normal decoding, (b) e=0: all outputs 0.

i0 i1 i2 i3 i4 i5 e

0

d0 d1 d2 d3

Happy New Year!

1 2 3

d58 d59 d60 d61 6x64 d62 dec. d63

58 59

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Digital Design

Digital Design

Combinational Design: Common Component: Decoder

Combinational Design: Common Component: Decoder a b c

d0 d1 d2 d3 d4 d5 decoder NOT(RAIN) d6 e d7

Microprocessor

a b c

zone 0

d0 d1

zone 1

d2

3

4 5

7

2 d3 d4

6

d5 d6 d7

NOT(RAIN) e

Sprinkler valve controller block diagram. Sprinkler valve controller circuit (actually a 3x8 decoder with enable). 17

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Digital Design

Digital Design

Combinational Design: Common Component: Decoder

Combinational Design: Common Component: Decoder

w0 w1

w0 w1

w2

En

y0 y1 y2 y3

w0 w1

y0 y1 y2 y3

w0 w1 En

w0 w1 w2

w0 w1

En

En

y0 y1 y2 y3

y4 y5 y6 y7

w3

w0 w1

En

En

y0 y1 y2 y3

En

w0 w1 En

w0 w1 En

y0 y1 y2 y3

y0 y1 y2 y3

y0 y1 y2 y3

y4 y5 y6 y7

y0 y1 y2 y3

y8 y9 y10 y11

y0 y1 y2 y3

y12 y13 y14 y15

A 4-to-16 decoder built using a decoder tree.

A 3-to-8 decoder using two 2-to-4 decoders.

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Digital Design

Digital Design

Combinational Design: Common Component: Multiplexer

Combinational Design: Common Component: Multiplexer „

i0

d

i1

Multiplexor n „ 2 data inputs „ n control bits „ 1 output

data inputs ... control inputs

mux d

i2

0

1 2

2x1 i0 i1 d s0

3 control lever

i3

A multiplexer is like a railyard switch, determining which input track connects to the single output track, according to the switch’s control lever.

2x1 i0 i1 d s0 0

2x1 i0 i1 d s0 1

i0 d i1

s0 2x1 multiplexer block symbol (left), connections for s0=0 and s0=1 (middle), and internal design (right).

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Digital Design

Digital Design

Combinational Design: Common Component: Multiplexer

Combinational Design: Common Component: Multiplexer

i0

Mayor’s switches 1 4x1 on/off i0 2 i1 d i2 3 Green/ i3 Red 4 s1 s0 LED

4x1 i1

Proposal

i0 i1 d i2

d i2

i3 s1 s0

i3

manager’s switches

s1 s0 4x1 multiplexer block symbol (left) and internal design (right).

Mayor’s vote display system implemented using a 4x1 mux.

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Digital Design

Combinational Design: Common Component: Multiplexer

Combinational Logic Design

4-bit 2x1 mux: (a) internal design using four 2x1 muxes for selecting among 4-bit data items A or B, and (b) block diagram of a 4-bit 2x1 mux component, (c) the block diagram uses a common simplifying notation, using one thick wire with a slanted line and the number 4 to represent 4 single wires.

s0

a3 b3

i0 2x1 i1 s0d

a2 b2

i0 2x1 i1 s0d

4

A B

4

4-bit I0 2x1 D I1 s0

a1 b1

i0 2x1 i1 s0d

a0 b0

i0 2x1 i1 s0d

s0

(a)

(b)

Simplifying notation: 4

C

4

is short for:

C

c3 c2 c1 c0 (c)

Above-mirror display. 25

Digital Design

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Digital Design

Combinational Logic Design

Combinational Logic Design: Common Component: Multiplexer

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T A 8 I 8 M 8

I0 8-bit 4x1 8 D I1 D I2 I3 s1 s0 x

s1

To the abovemirror display

From the car’s central computer

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Digital Design

s0 w0

0

w1

1

y

0 1

We’ll des ign this later

button

w2

0

w3

1

f

Above-mirror display using an 8-bit 4x1 mux.

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Digital Design Combinational Logic Design: Common Component: Multiplexer s0 s1 w0 w3

w4

s2 s3

w7 f w8 w11

w12 w15

A 16-to-1 multiplexer.

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Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.

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