4/12/2011
Digital Logic and Design (EEE-241) Lecture Dr M Dr. M. G G. Abbas Malik
[email protected]
Picture Source: http://www.vanoast.com/old-portfolio/digital-design-logo-one%5Ba%5D.jpg
Previous lecture y Introduction to design circuits with MSI and LSI y Binary Adder y BCD to Excess-3 BCD Converter y BCD Adder y Howe work: y Magnitude Comparator
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Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder y Discrete quantities of information are represented
in a digital system with binary codes. y A binary code of n-bits is capable of representing
up to 2n distinct elements of the coded information information. y A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. y The decoder are called n-to-m line decoders where m ≤ 2n 3
Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Decoder 2-to-4 Line Decoder D3 = xy x
D2 = xy’
y
D1 = x’y D0 = x’y’
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Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder 3-to-8 Line Decoder
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Dr. M. G. Abbas Malik – COMSATS Lahore
x
y
D0 D1 D2 D3
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
Each output line Di corresponds to a minterm. Thus a decoder generates the 2n minterms of n input variables.
It can be used to build a binary to octal conversion circuit.
3-to-8 line decoder can be used in general to for decoding any 3-bit code to provide eight possible outputs, one for each code.
Decoder BCD-to-Decimal Decoder y It is 4-to-10 decoder because BCD code contain 4 binary digits to code a decimal digit and there are 10 decimal digit. y With 4-bit 4 bit inputs we can represent 16 different codes, so the 6 combinations are Don’t Care conditions during the design procedure.
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Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Decoder BCD-to-Decimal Decoder y Map of simplification wx\yz
00
01
11
10
00
D0
D1
D3
D2
01
D4
D5
D7
D6
11
X
X
X
X
10
D8
D9
X
X
y D2 = x’yz’
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D9 = wz
Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder BCD-to-Decimal Decoder
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Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder Combinational Logic Implementation y A decoder provides the 2n minterms of n inputs. y Any Boolean function can be expressed in sum of minterms (canonical form), one can use a decoder to generate the minterms and an external OR gate(s) to form the sum. y A combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder and m OR gates.
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Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Decoder Combinational Logic Implementation Example: Full-Adder S(x, y, z) = Σ(1, 2, 4, 7) C(x, y, z) = Σ(3, 5, 6, 7)
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x
22
y
21
z
20
0 1 2 3 4 5 6 7
S
C
Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder with enable y Some IC decoders are constructed with NAND
gates. y Since NAND gate produces the AND operation
with an inverted output, it becomes more economical to generate the decoder minterms in their complemented form. y Most, if not all, IC decoders include one or more enable inputs to control the circuit operation.
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Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder with enable Circuit diagram and Truth Table
E x y D0 D1 D2 D3
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1 X X
1
1
1
1
0 0 0
0
1
1
1
0 0 1
1
0
1
1
0 1 0
1
1
0
1
0 1 1
1
1
1
0
Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Decoder with enable Block diagram
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Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder Demultiplexer y A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. y A decoder with an enable input can function as a demultiplexer. y The selection of specific output line is controlled by the bit values of n selection lines.
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Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder Demultiplexer E is taken as a data input line Lines A and B are taken as the selection lines Exercise: Draw the circuit diagram for this 1-to-4 demultiplexer. 15
Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Decoder 1-to-4 Demultiplexer: Circuit Diagram D3 = xy x
D2 = xy’
y
D1 = x’y D0 = x’y’
E
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A decoder with an enable input is referred as a decoder/demultiplexer p It is the enable input that makes the circuit a demultiplexer The decoder itself can use AND, OR, NAND or NOR gates.
Dr. M. G. Abbas Malik – COMSATS Lahore
Decoder y Decoder circuits can be connected together to
form a larger decoder circuit. y 4-to-16 Decoder
designed with 23 3-to-8 t 8d decoders d
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Dr. M. G. Abbas Malik – COMSATS Lahore
Encoder y An encoder is a digital function that produces a
reverse operation from that of a decoder. y An encoder has 2n (or m ≤ 2n) input lines and n
output lines. y The output lines generate the binary code for the
2n input variables. 0 1 2 3 4 5 6 7 18
22 8-to-3 encoder
21 20
Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Encoder 8-to-3 Encoder 0 1 2 3 4 5 6 7
19
22 8-to-3 encoder
21 20
Dr. M. G. Abbas Malik – COMSATS Lahore
Encoder 8-to-3 Encoder – Truth Table Inputs
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Outputs
D0
D1
D2
D3
D4
D5
D6
D7
x
y
z
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
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Dr. M. G. Abbas Malik – COMSATS Lahore
Multiplexer y Multiplexing means transmitting a large number of
information units over a smaller number of channels or lines. y A digital multiplexer is a combinational circuit that selects binary information from one of many input li lines and d di directs t it tto a single i l output t t liline. y The selection of a particular input line is controlled by a set of selection lines. y Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected. 21
Dr. M. G. Abbas Malik – COMSATS Lahore
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4/12/2011
Multiplexer 4-to-1 Multiplexer
Input lines
0 1 2 3
Output lines
4-to-1 M lti l Multiplexer
Select lines
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Dr. M. G. Abbas Malik – COMSATS Lahore
Multiplexer 8-to-1 Multiplexer
I Input t lines
0 1 2 3 4 5 6 7
8-to-1 Multiplexer
Output O t t lines
Select lines
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Dr. M. G. Abbas Malik – COMSATS Lahore
Multiplexer Self Study y How we can implement Boolean function using encoders and multiplexers? y Chapter 5: Decoder, Encoders and Multiplexers
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Dr. M. G. Abbas Malik – COMSATS Lahore
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