Does Low Cost Large Panel Processing mean Low Performance? Michael Scheffler, Didier Cottet, Gerhard Tr¨oster Electronics Lab, ETH Zurich, Gloriastr. 35, 8092 Zurich, SWITZERLAND Phone: +41-1-63 25829, Fax: +41-1-63 21210, eMail: [email protected] Abstract The Large Area Processing for thinfilm substrates can be used to reduce the cost per layer per area significantly. Various process setups exist to achieve this goal, and they differ in terms of process tolerances and cost. As different process tolerances result in different performance tolerance bands of the produced structures, customers may want to chose the right process to obtain sufficient quality. This paper presents the cross links between the two aspects quality and cost. Taking two process setups with different interconnect metalization width and dielectric thickness uniformity tolerances, we demonstrate the impact on integrated RF elements as microstrips, inductors, and antennas. Our findings show that it is suitable to offer customers two alternative types of processes: a tighter-tolerance process for highperformance RF applications, and a lower-cost process for less demanding products. Keywords: process tolerances, RF, integrated antennas, activity based cost modeling

1 Introduction Large Area Panel Processing (LAP) has for some time being perceived as the ultimate solution to lower the high cost associated with thinfilm substrates [1]. These substrates are not only interesting for use in multi-chip modules (MCMs), but also for manufacturing of recently introduced chip size/scale packages (CSPs). However, some significant difficulties occur when switching the actual production size from 4” and 6” wafers to very large panels. Process variation, being present also in small scale thinfilm fabrication as a function of location and distance to center, now becomes an even more important issue. This is due to the fact that with larger machines it is more difficult to control parameters as temperature, etchant homogeneity, plating rate, etc. Some of these variations can be reduced by choosing adjusted processing flows and different types of materials, but this would have an economical impact on the production in terms of cost and throughput. The purpose of this paper is to give a quantitative correlation of process tolerances and production cost for newly established large area panel processing lines [2]. The paper is organized as follows: in the next section the basic LAP process setup and its options under investigation is presented. Section 3 details the impact of the options on electrical performance with special attention to RF structures. The resulting cost of the different processes will be analyzed in section 4, and the last section summarizes the findings.

packages) took the effort to extend the thinfilm substrate manufacturing from 4” panel fabrication lines to rectangular panels up to 24” x 24”. Main target of the project was a significant reduction of the cost-per-area of such substrates. Where in the early ’90s a cost of 25$ per in was nothing uncommon, the project aimed for a 1$ range. Partially, this cost target would be achievable by the pure economics of scale, when enlarging the fabrication quantity. But in addition to that, new low-cost materials and more efficient processes had to be used.

2.1 Processes and materials An overview on the LAP process steps can be found in Table I, defining five groups: SC substrate cleaning; ISO deposition and structuring of the dielectric layer; M deposition and structuring of the inner metal layers; TM deposition and structuring of the top layers; FS finishing steps. The ISO and the M group have to be repeated for every interconnect layer. Where the former thinfilm processes used silicon wafers as base, polyimide (PI) as ISO layer, and aluminum as metal interconnect, the LAP project started with a different set of materials. Under investigations were

2 The LAP Project

as base materials: laminates as LinLam, Rogers 4003, cyanateester (CE), metals/alloys (CuX), and ceramics ); (e.g.

In 1998, an EU research consortium called LAP (low-cost Large Area Panel processing of MCM-D substrates and

as dielectrics: photosensitive benzocyclobutene (PBCB), polybenzoxazole (PBO), and Ormocer;

t1

t2 t1 = t2 : DOP = 0%

Fig. 1. Impact of cumulative process variations on line impedance

as interconnect metal: copper. Among the variety of combinations above, high laminates + PBCB and CuX + PBO have turned out to be the most promising ones. Although ceramics offer a better surface planarity than laminates, LAP-size panels with desired quality do not come at a reasonable cost. Table I. Overview on LAP Process Steps SC1 ISO1 ISO2 ISO3 ISO4 M1 (M1a) M2 M3 M4 M5 M6 (M7) TM1 TM2 TM3 TM4 TM5 TM6 TM7 FS1 FS2

Substrate Cleaning Dielectrics Coating Lithography Developing Curing Sputtering full Cu layer Sputtering Cu seed Coating Photoresist Lithography Developing Wet etch Plasma cleaning Electroplating Cu Sputtering Cu Coating Photoresist Lithography Developing Wet etch Plasma Electroplating Cu/Ni/Au S/O test Singularization

t1 = 0 : DOP = 100%

Fig. 2. Degrees of planarization

Metalization Basically, two metalization processes do exist: sputtering followed by etch patterning (also known as subtractive etching; M1 to M6 in Table I), and additive electroplating on a patterned resist surface requiring a sputter seed layer (M1a to M7). The sputter process exhibits a very tight thickness control and a good uniformity over a wide range. The etch process shows across-panel variations, as the etchant concentration is usually higher on the edges than in the center. So, low-frequency ripples of line width and thickness variation over the panel diagonal can be observed, as it is difficult to fully control the concentration uniformity. This uniformity is also an issue for electroplating, because it is as well a chemical process. But the plating process is much faster (10-100 x) than the sputtering, so local thickness variations and across-panel uniformity are even higher. In terms of cost, sputter equipment requires a high investment cost to be shared among the produced units, and the process has a lower throughput compared to the plating procedure. Dielectrics For the dielectric layers, especially the parameter DOP (degree of planarization, see Eq. 1 and Fig. 2) is important, as micro strip lines define their impedance by geometrical data as line-to-ground distance. Values of 80% to 90% have been reported [5].

2.2 Process options and their tolerances As reported in [3], different LAP process setups variate with regard to their line width, line thickness, dielectric thickness uniformity, etc. (for a comprehensive description of thinfilm processes see [4]). The term “process variation” defines arbitrary deviations from specified target values that are beyond control and cannot be prevented by design counter measures. These variations are referred to in design guidelines as “process tolerances”. In this framework we will focus on the process tolerances of different interconnect metalization processes and dielectric layers.

(1)

Thus, when the base carrier surface has a higher roughness, one level of dielectric material might not be sufficient to level out these imperfections. This is the case for laminate materials compared to polished ceramics. Polished

(a) RFTV1: inductors and transmission lines

(b) RFTV2: couplers, filters, and integrated antennas

Fig. 3. LAP RF test vehicles

ceramics offer a higher degree of surface smoothness (10x) than laminate materials. On the other hand, laminates have a lower cost per cm and a better availability than ceramics panels. Thus, considering dielectric thickness uniformity over large panel sizes, a two-step dielectrics layer can deliver better planarization uniformity, but this has to be paid for with an additional process step. In this study, we will investigate the following cases: Dielectrics: laminate base material with vs. without additional planarization layer; Metalization: sputtering/subtractive etching vs. seed sputtering/electroplating. The next section quantifies the observed process tolerances and shows their consequences on RF structures.

3 Impact on RF performance To assess the influence on RF performance, dedicated electrical test vehicles have been designed and fabricated using the LAP processes. The implemented structures comprise microstrip lines, inductors, couplers, and integrated antennas. Pictures of the test vehicles can be found in Fig. 3(a) and 3(b). Microstrip lines To characterize the impedance of a microstrip line, we used TDR (time domain reflectometry) measurements. Fig. 4(a) shows the TDR measurements of various striplines distributed over a panel’s surface, and we can ob. In this configuration 1 serve an impedance variation of there is only one dielectrics layer between base material and

microstrip ground plane. Fig. 4(b) shows the impedances when adding another dielectrics layer, dedicated for planarization purposes, between ground plane and base panel. With this additional planarization effort, a reduction of the impedance range to was achieved. Whereas sputtering/etching exhibits a tight thickness ) and a high uniformity over a wide range, control ( electroplating was found to end up with about thickness variation. In the frequency below 10GHz, when translating the physical tolerances to line impedances, we observed for sputtered lines and for plated lines. The line width of sputtered lines was in the range , slightly higher for the plated lines. For a of line width this translates into microstrip line using 50 impedance variations of and , respectively. Combining these variations for line width and dielectric thickness results in two different areas for a line impedance, depicted in Fig. 1. The outer, light grey area gives the uncertainty area when using a laminate without additional planarization layer and electroplating, with to. The inner dark grey area gives tal tolerance of up to the ranges when using the planarization layer and sputtering/subtractive etching, offering a smaller tolerance level of . From Fig. 1 one can conclude that dielectrics thickness variations have the much more significant impact on impedance control than line width variations, and line thickness variations does not have any influence.

Other RF structures But non-uniformity in metal width and dielectric thickness has also impact on more advanced structures as inductors and integrated antennas.

70

60

60 Impedance [Ohms]

Impedance [Ohms]

70

50

40

46.3

50

40

46.35

46.4

46.45 46.5 Time [ns]

46.55

46.6

46.65

(a) Configuration 1: laminate panel, NO add. planarization

46.3

46.35

46.4

46.45

46.5 46.55 Time [ns]

46.6

46.65

46.7

(b) Configuration 5: laminate panel, WITH add. planarization

Fig. 4. Influence of additional planarization layer

Quality Factor for 20nH Spiral Inductors 40

R = 4.5 ohms R = 5.0 ohms R = 5.5 ohms

35 30 Target Frequency = 77 GHz

Q-Factor

25 20 15 10

Bandwidth = 280 MHz

5 0 1e+09

Fig. 5. Shift of the target frequency of an integrated antenna

The first aspect to be considered follows directly from the microstrip impedance mismatches detailed above. Acting as feed lines for an integrated antenna as presented in [6], this mismatch will lead to a decreased return loss, directly affecting the specified electrical behavior. Moreover, dielectric thickness changes alter the resonance frequency reducing the usable bandwidth. Metal width tolerances as well cause frequency shifts due to patch length variations, as can be seen in Fig. 5. Second, changes in the specified ohmic resistance of an integrated inductor’s lines will influence the Q factor. Changes in the specified dielectric thickness cause again variations in the resonance frequency, as well effecting the Q factor. The change of the Q factor with the equivalent series resistance (ESR) is depicted in Fig. 6. In the following section a methodology to quantify the cost difference of the respective metalization and dielectrics processes is presented.

1.5e+09

2e+09 2.5e+09 Frequency [Hz]

3e+09

3.5e+09

4e+09

Fig. 6. Changes on Q factor due to ESR variations

4 Impact on cost To account for different production processes, during the LAP project a full parameterized cost model of the different panel productions has been developed for comparison purposes. The goal of this cost model was not only to give quantitative estimations of the actual process cost, but also, later when more detailed data is available, to analyze the manufacturing throughput and to suggest optimization strategies. In order to compare the very different setups in various European countries a common methodology had to be found. The result of this common methodology is called “activity based cost modeling”. Similar to [7], this methodology operates on fully de-bottlenecked lines and adjusts the labor staff to capacity needs. Thus, all non-idealities are hidden giving the minimum achievable cost. Of course, next to the “activity based cost”, also the

Fig. 7. Overview of Activity Based Cost Modeling

(a) Cost contributed by the subprocesses; including inner layer sputtering overhead and additional planarization layer

(b) Cost contributed by labor, material, depreciation, and overhead; including changes when switching to inner layer sputtering and additional planarization layer

Fig. 8. Cost details

“cost to be returned” is monitored, where total labor cost, total machine depreciation cost, and overhead cost are divided by the number of shipped units. A comparison of those two figures is an efficiency measure: the closer the “cost to be returned” comes to the “activity based cost”, the better the process is de-bottlenecked and equilibrated. Thus, the “activity based cost” is the bottom cost line a process can reach, and is therefore suited to characterize a specific setup. Together with the “cost to be returned”, also workforce capacity, bottleneck analysis, and annual production capacity is calculated. These figures help to improve the real process to reach its optimum. In our work we will concentrate on the “activity based cost”.

4.1 Activity Based Cost Modeling An overview of the cost modeling procedure can be found in Fig. 7. On the left side of the picture, the input parameters are listed, as e.g. machine purchase cost, machine up time, operator time per process, material cost, mass consum-

able cost, overhead cost, etc. Together with a description of each process step, the material cost, the labor cost (calculated from the operator cost per minute), and the depreciation cost according to “used” percentage of total available machine time can be computed. The sum of these cost factors gives the “activity based cost”, and it describes a fully equilibrated line, where no process bottleneck exists and sufficient workforce is available. The composition of the “activity based cost” according to the steps detailed in Table I is shown in Fig. 8(a). It can be seen that the finishing steps add a significant amount of the cost; this part of the cost has to be included because nothing else than a fully short/open-tested substrate is acceptable for customers. The contribution of the four factors material, labor, machine depreciation, and overhead is detailed in Fig. 8(b).

4.2 Results Using this fully parameterized process as a starting point, we set a 3-metal process with plated inner layers and no addi-

tional planarization step to 100%. To enhance planarization, the number of dielectric layers has to be increased by one. When replacing inner layer plating by inner layer sputtering, for the “M” subprocess in Table I M1a has to be changed to M1 and M7 has to be removed. The cost changes are summarized in Table II. The change to inner layer sputtering increases the cost per cm by 2.55%, adding the additional planarization layer results in a 10.6% raise. In total, the two cases described in section 2 differ by 13.2%. Whereas the cost increase for the additional planarization layer comes from the higher amount of material consumed, the reduction when switching to full inner plating is caused by the less expensive machine cost to be depreciated. Table II. Cost calculation results for 3 metal case

w/o planarization w/ planarization

inner layer plating subtractive etching 100% +2.5% +10.6% +13.6%

5 Discussion and summary The purpose of this paper was to evaluate and to quantify the cost and performance impacts of two process setups for large area thinfilm panel processing. The cases under investigation were an inner metal layer plating/no planarization layer process and a top-layer only plating/planarization layer process. The two metalization processes were found not to have a significant performance difference. In both cases, the line width variation (being about the same) dominates the thickness variation by an order of magnitude. The line surface finish in combination with the skin effect might lead to more significance in the frequency range above 10GHz, which will be subject to further investigations. From a cost point of view, when using inner layer plating the cost per cm goes down by about 2.5%, and being more important, the bottleneck situation in the fabrication line changes, giving a chance to extend line throughput and reducing the cost to be returned. The different planarization strategies have a much higher influence. Using a planarization layer the average tolerances can be reduced. This benefit comes with a cost penalty of about 10%, which cannot be expected to be fur-

ther reduced as this penalty is mainly driven by the dielectrics material cost. A conclusion to be drawn from these findings is that switching to inner layer plating is favorable in terms of cost and throughput. The additional planarization layer can be offered to customers requiring a tighter tolerance scheme.

Acknowledgments The Swiss Federal Office for Education (BBW) partially funded this project under 97.0286. The authors would like to thank their colleagues from the LAP consortium for their help and Janusz Grzyb for his comments.

References [1] T. Tessier and E. Myszka, “Approaches in Cost Reducing MCM-D Substrate Fabrication,” in Proc. Electronic Components and Technology Conference (ECTC’93), pp. 570–578, 1993. [2] “Esprit project 26261: Low cost large area panel processing of MCM-D substrates and packages.” http://www.ife.ee.ethz.ch/mcm/lap/, 1998-2000. [3] D. Cottet, J. Grzyb, and G. Tr¨oster, “On the Right Use of RF Structures on Low Cost High Density Substrates,” in Proc. CPD’2000, March 14 & 15, 2000, Zurich, Switzerland, pp. 88–92, 2000. [4] R. Tummala, E. Rymaszewski, and A. K. (eds.), Microelectronics Packaging Handbook, vol. II. Chapman & Hall, 2 ed., 1997. [5] K. Matsui, T. Shimoto, Y. Shimada, and K. Utsumi, “MCM-D/L Technology Based on Cu/Benzocyclobuten Thin-Film Multilayer Structure,” in Proc. Int. Symposium on Microelectronics (ISHM’95), pp. 396–401, 1995. [6] D. Cottet, J. Grzyb, B. Oswald, M. Scheffler, and G. Tr¨oster, “Integrated RF Components on Low Cost MCM-D Substrates.” to appear in Proc. IMAPS Europe 2000, Prague, CK, June 2000. [7] D. Frye, M. Skinner, R. Heistand, P. Garrou, and T. Teissier, “Cost Implications of Large Area MCM Processing,” in Proc. Int. MCM Conference (MCM-Denver ’94), pp. 69–80, 1994.