Control
Strategies
Connected
for
Balancing
IGBT/Diode
of Series and Parallel
Modules
Diss. ETH No. 15232
Control
Strategies Balancing of Series
for and
Parallel Connected
IGBT/Diode
Modules
A dissertation submitted to the SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH
for the
degree
of
Doctor of Sciences
presented by JAN THALHEIM
Dipl. Ing., University of Magdeburg born July 13th, 1969 citizen of Germany accepted
on
the recommendation of
Prof. Dr. W. Prof. Dr. J.
Fichtner, examiner W. Kolar, co-examiner 2003
Acknowledgment s I would like to thank my
supervisor, Prof. Wolfgang Fichtner, for his
overall support and for his faith in
me
to thank Prof. Johann W. Kolar for
Special thanks
co-examining the thesis.
to Dr. Norbert Felber for his
support during my work. I also
colleagues
and my work. I would also like
encouragement and
gratitude to all Christoph Balmer
want to express my
at the
Integrated Systems Laboratory, to from the Microelectronics Design Center, to Dr. Nico Karrer from the Electrical Engineering and Design Laboratory and to Heinz Riiedi and Peter Köhli from CT-Concept Technology Ltd. Thanks to Robert Reutemann for his contributions to this project. I acknowledge the financial sponsorship of KTI, the Commission for Technology and Innovation of the Swiss Government. I want to particularly thank my wife Vici, the cats Ronja and Flöckchen, and for the faith in tomorrow.
v
Contents
Acknowledgments
v
Abstract
xi
xiii
Zusammenfassung Nomenclature
1
1
1
Introduction
1
1.1
Motivation
1.2
Objective
5
of this Work
7
Synopsis of Techniques for Controlling
Power
MOS Semiconductor Switches 2
Optimal Control 2.1
2.2
of
IGBT/Diode
Optimizing Switching
11 Module
Operation
Losses
13 13
2.1.1
Modifying Switching Dynamics
15
2.1.2
Mode and
17
2.1.3
Open-Loop Control
20
2.1.4
Closed-Loop Control
26
Dynamics of Gate Driving
Device Protection
31
2.2.1
Overcurrent Protection
2.2.2
Overvoltage
Protection
Off
31
during
Fault-Current Turn35
vii
CONTENTS
viii
2.2.3
Impact of the Gate
Drive Characteristics
on
Noise
Sensitivity 3
Multiple-Switch Balancing Techniques 3.1
3.2
II
36
37
Synchronizing Switching Transients Discrete-Time Approach 3.1.1 3.1.2
Continuous-Time
3.1.3
Mixed-Mode
Balancing
in
37 38
Approach
40
Approach
Quasi-Steady
42
State
A Novel Power Conversion
43
System of Com¬
bined Parallel- and Series-Connected Switches 4
Hierarchical Controller Architecture 4.1
Outline of State-of-the-Art Gate Drive
4.2
System Topology 4.2.1 Qualifications 4.2.2 Example Control Concepts
4.3
Techniques
.
.
49 50 50 53 56
Current- and
4.3.2
57
4.3.5
Voltage Distribution Determining dic/dt via vce-Control Control System Behavior Modifying System Dynamics
4.3.6
Variable Structure Gate Driver
80
4.3.7
Synchronization of Multiple Modules Preferred Concepts for Synchronizing Combined
84
Parallel and Series Connected IGBTs
97
4.3.4
4.3.8
4.4
49
4.3.1
4.3.3
5
47
Implementation
Temperature-Distribution
Issues
....
56
65
70 76
107
4.4.1
Adaptive control
110
4.4.2
Summary
113
Local Controller ASIC
Implementation
115
5.1
Architecture
115
5.2
Driver Partitions
119
5.3
Control
124
5.3.1
126
Circuitry Digital Interface
CONTENTS
ix
5.3.2
State Detection and Structure Control
126
5.3.3
Nominal-Value
127
5.3.4
Current Reference
127
5.3.5
Conclusions
128
Management
128
5.4
Power
5.5
Measurements 5.5.1
Nominal-Value
5.5.2
Driver Partitions
Response 5.5.3
Signal
Generation
6.2
Output Current
133
to the Actual-Value
Signal
Conclusions and Outlook
141
Summary Perspective
Power Semiconductor
141 142
Compact
Models Used for Circuit
B.2
C
145
Effects of Unmatched B.l
135 135
Simulation B
130 133
Conclusion 6.1
A
Generation
130
Maximum
6
Signal
Switching
of
Multiple IGBTs
Series Connection
153
154
B.l.l
Turn-on of the IGBTs
154
B.l.2
Turn-off of the IGBTs
157
Parallel Connection
159
B.2.1
Turn-on of the IGBTs
159
B.2.2
Turn-off of the IGBTs
159
Schematics of the Local Controller ASIC
161
Bibliography
175
Curriculum Vitae
185
Abstract
high-power applications, it may be necessary to switch by connecting smaller units in parallel and series to achieve high availability, high-frequency operation, and low cost due to build-in redundancy, reduced dynamic losses, and modular use of standardized units, respectively. IGBTs are very convenient to realize such units, because of quasi-linear controllability via a gate high-voltage realize a logical
For
or
terminal. This thesis
investigates control methodologies for
conductor switches with focus tion of
with
IGBT/diode
modules.
primary local control
on
power MOS semi¬
combined
It is
parallel and series connec¬ proposed to provide each IGBT
to monitor and
adjust
the IGBT's static
dynamic behavior. Secondary (global) control synchronizes the operation of multiple IGBTs. A globally synchronous clock can also be derived locally. This makes it possible to use low-cost low-bandwidth data links between series-connected units. Thereby, a flexible masterslave approach can avoid the need of dedicated global control. That is, the entire system is manageable by the local gate drive circuitry. A prototype ASIC has been fabricated in CMOS technology with high-voltage extension. The driver is partitioned into fourteen clusters with a measured gate current capability of one Ampere each. A clas¬ sification of the IGBT's collector-emitter voltage and collector current signals allows for real-time reconfiguration of the controller structure to optimize the dynamic response of the system. The conduction state and the recovery speed of freewheeling diodes are controlled by the voltage drop across the DC link inductance, which is locally estimated and
at each IGBT.
xi
Zusammenfassung Bei
Hochspannungs-Umrichtern
kann
schen Schalter durch Parallel- und realisieren.
es
erforderlich sein, einen
Reihenschaltung
von
logi¬
Schaltelemen¬
Vorteile sind das Erreichen hoher
Verfügbarkeit durch Ausnutzung von Redundanz, hoher Schaltfrequenzen durch Aus¬ nutzung verringerter dynamischer Verluste und geringere Kosten durch
ten
zu
modularen Einsatz standardisierter Module.
geeignet für diesen Ansatz, da diese über
IGBTs sind besonders
einen Gate-Anschluss linear
gesteuert werden können. Diese Arbeit behandelt Ansätze
Ansteuerung von MOS-LeiSchwerpunkt dabei ist die kombinierte zur
stungshalbleiterschaltern. Der Parallel- und Reihenschaltung von IGBT/Diode Modulen. Es wird vorgeschlagen, das statische und dynamische Verhalten der IGBTs lo¬ kal zu beobachten und anzupassen. Eine weitere (globale) Steuerung dient der Synchronisation mehrerer IGBTs. Eine systemweit synchro¬ Dies ne Bezugszeit kann auch auf lokaler Ebene abgeleitet werden. ermöglicht den Einsatz preiswerter Datenübertragungssysteme mit geringer Kanalkapazität zwischen reihengeschalteten Modulen. Da¬ bei kann durch einen flexiblen Master-Slave Ansatz auf eine spezielle globale Steuerung verzichtet werden und das gesamte System über die lokalen Gate-Treiber gesteuert werden.
Prototypen ASIC wurde in CMOS Technologie fabriziert. Der Treiber ist in 14 Cluster mit jeweils 1 Ampere Gatestrom unterteilt. Es erfolgt eine Zustandsklassifizierung auf Grundlage der Signale der Kollektor-Emitterspanungen und Kollektorströme der IGBTs. Dies erlaubt eine Rekonfigurierung der Steuerungsstruktur in Echtzeit zur Optimierung der Systemdynamik. Die Steuerung des Leitzustandes und des Kommutierungsverhaltens der Freilaufdioden erfolgt dabei Ein
xiii
CONTENTS
xiv
auf lokaler Ebene über den
Spannungszwischenkreises.
Spannungsabfall
an
der Induktivität des
Nomenclature
The IEC nomenclature is used to
are
ther, the
terms
c
"saturation
consideration of the
-St
region" and "linear region" are used equivalent DMOS sub-device of the IGBT.
dielectric constant of
silicon,
asynchronous signal which is vce(t) or ic(t) connected modules, respectively, page 87
Agd
gate-drain overlap
Cp
gate-collector capacitance (often capacitance
or
for series
or
parallel
area, page 18
Miller
referred
capacitance),
as
reverse
transfer
page 14
CV
gate-emitter capacitance,
Cce
equivalent capacitance seen from collector to emitter of ticular single module or logical switch, page 58
Cdr
driver output capacitance, page 71
Ciss
virtual input capacitance, page 18
Cx
capacitance used
Rx,
in
page 18
a(t)
/i
That
(collector) denotes the physical emitter (anode) of IGBT, the index e (emitter) denotes the cathode. No standards used to classify physical quantities (e.g. "high-voltage" ). Fur¬
means, the index
the
the device terminals.
name
page 14
in series with
an
auxiliary damping
page 71
unity gain bandwidth (transit frequency), xv
page 73
a
par¬
resistance
CONTENTS
xvi
loop gain,
page 73
go
open
gm
saturation
ic
collector current, page 13, 14
h
gate current, page 14
îdr
driver output current, page 71
^Load
load current, page 14
Kf
empirical factor
region transconductance
to model ratio of
in saturation for
MOSFET,
gm
Kp
=
dic/dvgej
in linear
page 13
region
to that
page 18
region transconductance parameter,
Kp
saturation
La
DC link stray
Lce
inductance between the terminals from which the vce-feedback
signal Lei
is
inductance,
derived,
inductance of the ter current
path,
page 16
page 41
page 65
part of gate control loop and emit¬
common
page 16
inductance,
Le
emitter
Lg
total gate
M
number of
N
number of series connected
switches,
Nb
base
page 18
Nmob
collector-base mobile carrier concentration, page 19
Nsci
collector-base space
q
electronic
charge,
Rg
total gate
loop resistance,
Rx
auxiliary damping resistance,
page 62
loop inductance,
page 71
parallel connected switches,
doping concentration,
page 51
page 51
charge concentration,
page 18 page 16 page 71
page 18
CONTENTS
xvii
T
chip temperature,
td(off)
turn-off
delay,
page 34
i.e. time difference between the start of
in vge and the start of
td(on)
delay,
turn-on
change
in vcej page 15
i.e. time difference between the start of
in vge and the start of
change
in
ic,
(Miller plateau),
Vge at ic
vce
collector-emitter
vcg
collector-gate voltage,
Vdc
DC link
Vdr
driver output
vge
gate-emitter voltage,
vie
voltage
vnsat
saturated
vt
MOSFET channel threshold
Wgdj
gate-drain overlap depletion width,
page 18
x(t)
synchronous signal which is ic(t) connected modules, respectively,
vce(t)
iLoad
voltage,
across
voltage,
change
page 15
Vm
=
change
page 14
page 13
page 14
page 14
voltage,
page 14
page 14
the emitter
velocity
inductance,
of electrons in
page 24
silicon,
voltage,
or
page 19
page 18
for series
application specific integrated circuit,
BCD
technology providing BJT, Complementary
(DMOS),
BJT
bipolar junction transistor,
CMOS
complementary
page 9
MOS
page 27
page 1
metal oxide
semiconductor,
page 27
DMOS double-diffused metal oxide
semiconductor,
page 27
EMI
electro-magnetic interference,
F WD
freewheeling diode,
page 14
parallel
page 87
ASIC
Double-diffused MOS
or
page 16
(CMOS),
CONTENTS
xviii
GCT, IGCT (integrated) gate commutated thyristor, GTO
gate turn-off thyristor, page 1
IGBT
insulated gate
IP M
Integrated
bipolar transistor,
Power
Module,
page 1
page 1
page 6
MOSFET metal-oxide semiconductor field-effect transistor, page 1 NPT
non-punch-through (triangular
PT
punch-through (trapezoidal
SC-SOA short-circuit safe safe
VSI
voltage-source inverter,
operating
base
operating
SOA
base
E-field),
E-field),
page 2
page 2
area, page 32
area, page 32
page 8
ZCS
(ZCT)
switching (zero-current transition),
page 8
ZVS
(ZVT) zero-voltage switching (zero-voltage transition),
page 8
zero-current
Chapter
1
Introduction
Electric power conversion systems convert and control electrical power
by using semiconductor devices. Nowadays the devices operate in switching mode, which causes the power dissipation to be reduced. Since the trend is towards higher switching frequencies and higher voltage levels, the main device design problem is to attain both, low conduction losses and fast switching capability. switching devices Todays high-power conversion systems commonly use gate turn-off thyristors (GTOs) as switching devices. The main advantage of a GTO is the relative simple structure which does not require high-resolution lithography for manufacturing. So, the yield is generally high, even for very large monolithic devices. In 2001, GTOs are manufactured from 4 inch wafer technology in a range of (2500V, 4500V, 5500V)/(1000A...4500A). The gate drive circuitry of GTOs must provide high current sinking capability to turn-off the device via the base of the corresponding thyristor-internal bipolar junction transistor (BJT). The ratio of load current to gate current is typically between 3 and 5. A safe operation of switching devices requires to limit the rates of change of current and voltage at the load terminals (di/dt and dv/dt respectively). Furthermore, GTOs do not show inherent current saturation. As the static and dynamic behavior of a GTO is not controllable through the gate terminal, aux¬ iliary power-side circuitry is required to control the switching speed Semiconductor
1
Introduction
2
and for short-circuit protection.
The
complexity of GTO modules is further increased due to the auxiliary power supply required for the gate driver. This may derate the overall reliability of the system and In partic¬ cause increased cost, weight, and total power dissipation. ular, to avoid the problem of inhomogeneous current distribution in large GTOs during turn-off, low dv/dt is applied; or recently, the en¬ tire switch current is commutated via the
directly
attached to the gate drive
extraction of base
gate commutated The
circuitry
charge. Such modules thyristors (I)GCTs.
major advantages of the
field-effect transistor
(MOSFET)
gate.
are
The gate must be
in order to achieve fast
referred to
as
(integrated)
power metal-oxide semiconductor
the
high DC-impedance gate terminal and the controllability of switching speed. To make these devices suitable to higher voltage applications, a reduction of static losses has been achieved by introduction of an additional layer at the drain side to form a pn-junction region. Thereby, conductivity mod¬ ulation is provided by injecting holes as additional carriers into the low-doped (n~ doped) drift region. A wide-base bipolar transistor is formed in combination with the MOSFET well diffusion region and the low-doped drift zone. The device structure can be correctly referred to as conductivity modulated MOSFET. Commonly it is called insu¬ lated gate bipolar transistor (IGBT). Static losses have been further reduced by using a vertically aligned trench gate to enhance electron injection. A reduction of device thickness is desirable to reduce to¬ tal losses. This is achieved by increasing the doping concentration of the drift region near the drain-side p+n~ junction to prevent a punch through of the electric field. This approach is referred to as punchthrough1 (PT) approach. are
Commonly, a switch module combines a number of IGBT chips and diode chips connected in parallel, currently up to 24 plus 12 chips respectively. This requires advanced interconnection and packaging. Recently, pressure contact technology has been introduced. The ad¬ vantages are reduced thermal resistance and parasitic inductances, and enhanced reliability due to avoiding wire-bonding and soldering. xThe absence of thin
low-doped
field stop
(FS)
or
a
buffer
graded
layer is often referred to as non PT (NPT). Using a layer is also called soft punch through (SPT) or
buffer
3
Towards are
a
10 kV monolithic
available up to
[WBLF00]
a
switching device? blocking voltage of 6500 V. It
that 6500 V IGBTs that combine
proach with
Today,
IGBTs
has been shown
low-cost
planar gate ap¬ lifetime profile yield turn-off a
carefully designed carrier losses and on-state voltages comparable to the IGCT. Although there might actually be a demand of semiconductor switches beyond the 6500 V class (e.g. for a medium-voltage industrial motor drive oper¬ ating at 10 kV, 50 Hz) a further enhancement of the voltage capability is not reasonable from the economic point of view. For applications not driven by mass market there might be no reason to reduce the a
number of series connected devices from let's say 200 40
(at
125 kV
3125
V)
-
for
e.g.
high voltage
(at
625
V)
to
direct-current transmission of
series connection of
lower-voltage switching modules may result in lower total cost. This is because the high de¬ mand of 600 V... 1700V IGBTs keeps chip and packaging costs low. It is expected that high-frequency switching capability is the force There to drive the semiconductor development in the near future. is a general trade-off between on-state losses and turn-off losses. An effective approach to optimize performance is to enhance electron in¬ jection, e.g. by using trench gate structures. Another trend is to use a vertically reduced surface field (RESURF) principle. Here, the electric field is decreased by 2D-depletion; a much higher breakdown voltage is obtained on a thinner layer. An increase of on-state con¬ ductance of MOSFETs up to the factor 5 has been reported [GS00]. A commercially available device is the Cool M OS. (Cool Mos is a trade mark of Infineon Technologies.) Furthermore, a trend is towards ultrafast diodes based on SiC (by factor 10 higher breakdown voltage) and merging PiN with Schottky barrier structures (optimizing the excess carrier
-
since
rigorous
profile).
Combining multiple switching resistance
Rds(on)
of
a
devices instead?
power MOSFET is
mainly
The on-state
due to the resistance
of the drift
region which is a function of the drain-source breakdown voltage Vds(max)- The dependence is of the following type: -tl-ds(on)
where the exponent
a
CX-
is between
for conventional MOSFETs.
*ds(max)
1
\
)
for RESURF devices and 2.5
According
to
[IntOl],
the exponent of
Introduction
rated
voltage
voltage drop
@1.7A/mm2,
373K
IGBT
100
300
600
HEXFET
100
250
500
1000
IGBT
1.5
2.1
2.4
3.1
HEXFET
2.0
11.2
26.7
100
1200
Table 1.1:
Dependence of on-state voltage drop from voltage rating [IntOl]. Voltage ratings of the power MOSFETs are lower than the IGBT's to take into account their avalanche capability. (HEXFET is a
a
trade mark of International
2.5 is
=
a
Rectifier.)
misconception.
correct
value would be
1.9. The voltage drop across the IGBT typically a is the sum of the voltage drop across the anode-side p+n~ junction region and the voltage drop across the conductivity modulated drift region. Thus, unlike the power MOSFET, the on-state voltage drop a
>
1.6 and
Rather, the
across
an
=
IGBT
never
goes below
a
diode threshold.
In addition to
voltage drop, conductivity modulation virtually elimi¬ nates its dependence on the voltage rating (however at the expense of turn-off losses). This is shown in Table 1.1, where the voltage drops of IGBTs of different voltage ratings are compared to those of power MOSFETs with the same current density. These data also contradict reducing
the
the
common
misconception that
utilization at low A system
power MOSFETs have better silicon
voltages.
comprising
series connected switches may result in
a
performance similar (or improved in regard to the conventional MOS¬ FET) to a single-switch approach, since series connection offers higher electron injection per equivalent base width. To achieve
highest switching frequencies, switching losses can be distributed by interleaved operation of parallel switches. The design of recent modules does not offer a real advantage over parallel connected smaller modules. In particular, a common gate terminal is rather dis¬ advantageous in terms of controllability and reliability. Concluding, stacking of universalized medium-power IGBT modules may become a
very attractive solution.
1.1 Motivation
Motivation
1.1
Requirements of
5
high-power
conversion
systems
transmission and distribution.
ability tors
of such systems.
(or
of
more
The main
of recent power systems are
An
Parallel
or
important
criterion is
high
avail¬
series connection of semiconduc¬
complex modules like
to increase the current
traction
applications and drives, and power
power
converters)
is necessary
voltage capacity or the switching-frequency of a system. A reconfigurable system using both parallel and series connected switching devices might enhance reliability compared to systems utilizing a minimum number of switching devices. The requirements of compact and efficient systems are driving the demand for high-speed switching. In most cases, devices with lower voltage capability can be operated at higher switching frequency, such that costs, weight, and losses of auxiliary power-side components are reduced. Furthermore, these features make it easier to attain over¬ all system compatibility by controlling the impedance or harmonic content of line and output signals. For the particular case of driving traction motors, power losses and torque ripple are reduced. Addition¬ ally, high-frequency operation avoids audible acoustic noise. GTOs and IGBTs with a voltage capability higher than 2500 V are normally restricted to operate at a switching frequency of 1 kHz (where dy¬ namic losses are approaching static losses). In low-frequency systems using two-level switching, unwanted harmonics can be suppressed to This can be realized by using a certain degree by active filtering. smaller auxiliary converters which work at higher switching frequency than the main switches. Otherwise, for a given switching frequency the signal resolution can be increased by introducing a multi-level switching sequence. or
Architecture alternatives
System architectures based on series connected power devices today still use power-side components for passive power-control, e.g. dv/dt-contiol, voltage-dividing and -clam¬ ping or similar techniques, which are bulky and expensive. However, the total count of passive components is not inevitably increased as demonstrated for
[WASB00].
a
ZVS scheme of series connected switches
In the iV-level converter
divided into N-l levels
by
[SL00],
series connected
the DC link
[DHJS95], voltage
is
capacitors. (Voltage shar-
Introduction
6
by additional circuitry.) The switching devices are clamped to the corresponding voltage levels via high-voltage diodes. By applying a special switching sequence, a higher resolution of mod¬ ulated signals can be achieved at lower switching frequencies. Series connection of N converters on the AC side [SteOO] provides a voltage which is N times the capability of one sub-converter. But the DC link voltages of the N converters must not share a common node. In¬ stead, combining is realized by way of additional converters driving intermediate high-frequency (and thus low-weight) transformers or by distributed load (e.g. by driving multiple motor coils). ing
is achieved
upgradability are keys to the desired system architecture in order to reduce design effort and component costs for a particular system. Therefore, the focus of this thesis is on direct series/parallel operation of switching devices with a mini¬ mum number of auxiliary power-side components. Power MOSFETs, IGBTs, or the like offer the advantage of current saturation, adjusta¬ bility of dynamic and static behavior, and thus improved state mon¬ itoring. This simplifies synchronizing multiple switches, as control circuitry may compensate for parameter deviations. Modularity, scalability,
System integration scale of integration of
and
There
are
a
few
power conversion
approaches systems.
(calculation of switching sequence, e.g. for drive systems), integrated circuits are
to increase the
At
a
higher
level
of control
for direct torque
control
well
established, whereas gate drive circuitry is usually designed for the specific ap¬ plication. Consequently, functionality is reduced to the minimum in order to keep costs low. But eventually, maintenance and energy costs over the lifetime of a system should be considered, as advanced gate
driving
can save
energy and could
One decision is to
support
integrate gate drivers
new
system architectures.
into the power module
or
keep the driver separately. Recently, manufacturers provide a vari¬ ety of ready-to-use drivers and cooling systems suitable to particular power modules and applications. Equipped with a uniform interface and shape [LHM99], such units are often referred to as integrated
to
power modules
(IPM).
The traditional form of switch
as
close
as
possible
an
to
integrate one driver for each the IGBT chips. This results in higher IPM is to
1.2
Objective
controllability
of this Work
of the module's
inductance of the the
reliability
7
dynamics due to minimal delay and gate loop. However, thermal conditions may affect
of the driver circuit.
large number of chips, using a single gate driver requires a well thought out global gate connectivity to reduce the impact of parasitics. Modularity, scalability, and evenly For
a
module which combines
distributed load
are
a
difficult to achieve.
A further step would therefore be to
provide
one
driver per subset
of the total number of
chips which form a logical switch. This offers a good predictability of the switching behavior. These local controllers could also be used to equalize dynamic and static load of parallel operating subsets of IGBT chips. As a result, the requirements of layout symmetry could be relaxed. And so, for more complex modules, the overall design effort is reduced. Key functionality required for controlling IGBTs within the limits of safe operation area is to evaluate the collector current, e.g. by using a parallel sense-IGBT, and to limit the collector-emitter voltage, e.g. by avalanche devices. These rather simple control functions could be realized on the same technology as used for the IGBT chips [FLP+97] and could be placed on same die. But, when integrated
into the IGBT
modules, such circuitry might interfere with external control and may reduce the flexibility to adapt the driver to application requirements. Therefore, the controller should be distributed over several hierarchy layers with application-specific functionality. Although initial engineering effort is increased, this could reduce time-to-market and would find
1.2
Objective
more
acceptance.
of this Work
In the field of active control of transient and static behavior of
single
devices, much research has been focused on particular portions of the problem, e.g. di/dt-contvol or synchronizing turn-on delays. However, many solutions are actually closely related and interdependent. A combination of these techniques is therefore demanding as well as questionable. or
series connected power
In this thesis
combined
a
hierarchical controller architecture for systems of
parallel and
series connected MOS-controlled power semi-
Introduction
8
conductors
(in particular IGBT/diode modules)
is
proposed.
Local
switching transients of the IGBTs (dynamic gate control DGC in Fig. 1.1). A secondary control loop is used to man¬ age reconfiguration, global timing and parameter scheduling (power system controller in Fig. 1.1). An interface to an application-specific layer is defined, which handles central system control (Microcomputer in Fig. 1.1). Focus is on snubberless hard-switching voltage-source in¬ verters (VSI) with inductive load. Furthermore, compatibility with control optimizes the
in
operation is based
on
soft-switching2
the
modes is considered. The desired system
characteristics:
following
Topology •
combine series and
•
provide
a
parallel connected switches
redundant and
reconfigurable system
Control
operation
in the safe
operating
(SOA)
•
ensure
•
minimize transient and
•
synchronize parallel
•
provide reconfiguration management and fault processing
•
execute
steady
area
state losses
and series connected switches
system startup and shutdown procedures
Thesis Structure The first part
gives
a
synopsis of techniques for controlling single
power MOS semiconductor switches
parallel connected
power semiconductor switches
2Zero-Voltage Switching (ZVS): enabling
a
(Chapter 2)
switch current while
as
well
as
series
or
(Chapter 3).
by parallel to the main switch at turn off. Zerovoltage while current is zero, e.g. by enabling an
capacitance, connected
voltage
is zero, e.g.
in
Switching (ZCS): switch inductance, connected in series to the main switch at turn on. When the resonance circuit is controlled by auxiliary switches, this is sometimes referred to as ZVT or Current
ZCT
(... Transition).
1.2
Objective
of this Work
9
\ Figure 1.1: Architecture to hierarchically control a reconfigurable 3phase voltage source inverter with combined series and parallel con¬ nected switches.
Focus of the second part is
on
combined
parallel and
series
con¬
nected switches. In
Chapter 4, general requirements for system topol¬ ogy and controller design are derived. Local controller techniques are reviewed with regard to reconfigurable high-speed systems. A novel hierarchical controller methodology based on a sophisticated system topology is derived. In Chapter 5, implementation issues for a local controller ASIC are discussed in detail. The ASIC implements a novel
methodology
to control the
dic/dt during
turn-on.
The driver stage
satisfies the gate current demand of IGBTs up to the 3300 class. It is
partitioned
formance, the system
state.
chronous and
ple IGBTs in Chapter 6
into 14 clusters. To
optimize the dynamic
activation of these clusters is
The state detection
can
V/1200 A
depending
on
per¬
the actual
also be used to extract syn¬
asynchronous events to manage the operation of multi¬ series and parallel connection. extracts the key results and gives an outline of current
and future work.
10
Introduction
Part I
Synopsis of Techniques for Controlling Power MOS Semiconductor Switches
h
Chapter
2
Optimal
Control of
IGBT/Diode
Module
Operation This
synopsis of gate drive methodologies for MOS A simple circuit simulation semiconductor single switches.
Chapter gives
power
a
model is used to demonstrate the
ing behavior of the
capabilities
power devices.
to
In Section
optimize the switch¬
2.1,
main focus is
on
minimizing steady-state and switching losses under regular operating conditions. Section 2.2 shows how to
reliable operation under
ensure
fault conditions.
2.1
Optimizing Switching
To minimize
dynamic
losses under
derivatives of collector current
(dvce/dt)
Losses
hard-switching operation,
(dic/dt)
and collector-emitter
can
voltage
have to be controlled to stay within the limits of latch-free
and avalanche-free operation, soft recovery, and safe This
the time
be achieved
by controlling
the gate
the transconductance gm in the IGBT's
13
operating
area.
charge profile, utilizing saturation region.
Optimal Control of IGBT/Diode Module Operation
14
linear
/ saturation region
region ,'
d(on)
Figure
2.1:
First-order approximation of IGBT
response of state variables
during
-
Td(off)
dynamics (left)
turn-on transition
(right).
Switching behavior under inductive load conditions cally, switching transients are induced by a voltage applied to via
the
a
gate resistor
switching
(Fig. 2.1).
behavior is
To derive
simplified
device supports the full DC link
as
a
and
Classi¬ the gate
first-order approximation,
follows.
Before time to, the
voltage, Vdc, and the gate voltage and collector current are zero. During period to to t2 the gate-emitter capacitance CV is being charged by the gate current ig, and the gateemitter voltage Vge increases. During period t\ to t2, the collector current ic rises according to the saturation region transconductance. As long as the actual collector current is still approaching the available load current ilooA, the freewheeling diode (FWD) stays in conduction, and the voltage across the IGBT continues to be approximately the DC link voltage. Any stray inductance is neglected here. The charg¬ ing current of the reverse transfer capacitance (Miller capacitance) C^ can be neglected during this period, since the derivative of the volt¬ age across C^ is small, and C^ is much smaller than the gate-emitter capacitance C^. At time t2, ic reaches iLoad, and the diode shuts
2.1
Optimizing Switching
off.
The diode
Losses
15
neglected here. The collector cur¬ rent now stays approximately constant, according to the load current, while the collector voltage starts to fall. As long as operation remains in the saturation region, the differential resistance is increased and the collector voltage reacts very strongly to changes in the collector current. In this phase, the equivalent input capacitance is virtually infinite, due to the Miller effect. The gate voltage now stays constant at Vm- For the time being, therefore, no further charge is consumed by CV. Thus the drive current now contributes exclusively to dis¬ charging C^. At t3 the collector voltage reaches the linear region of IGBT-operation. The gate voltage is now no longer constrained by the saturation region transfer characteristics of the device, but is free to increase up to the driver output voltage VdrA similar behavior is shown during turn-off, however in reverse order. The diode forward recovery is neglected here. The turn-on delay td(on) is defined as the time difference between the starting points of gate voltage increase and of collector current increase (ti to). The turn-off delay td(0ff) is defined as the time difference between the starting points of gate voltage decrease and of collector-emitter voltage decrease (equivalent to t^ t-$). reverse
recovery is
—
—
2.1.1
Modifying Switching Dynamics
Constraints
Particularly from the time at which the sign of current through the turning-off freewheeling diode is changing, the dic/dt de¬ termines the reverse recovery behavior by controlling the actual profile of excess carrier concentration. Usually it is required to slowdown the inherent IGBT switching speed to prevent the circuit from: •
snappy1
diode behavior
•
dynamic
avalanche of the diode
•
dynamic latchup
of the IGBT
During turn-off of the IGBT the dic/dt has to be restricted considering that vce rises up to the sum of DC link voltage and dic/dt-induced volt¬ age across stray inductance. Usually, the achievable dic/dt does not 1i.e.
snappy
nation with
falling edges
of current which induce
stray inductance
voltage
overshoot in combi¬
Optimal Control of IGBT/Diode Module Operation
16
reach the critical value that initiates A
secondary
constraint is to limit the
namic avalanche. Reliable
of the IGBT.
dynamic latching
dvce/dt
in order to
operation of IGBTs and
prevent dy¬
power diodes
can
dvce/dt of about 10 V/ns or even higher. Eventually, dvce/dt-limitation is required for system compatibility
be achieved up to
reasons.
Steep
a
transients may lead to increased
EMI2
noise and to
overvoltage in case of driving long transmission lines or induction motors. According to the measured results reported in [MSBS98], the transient stress approaches the steady-state stress at voltage risetimes of about 5 us. Such low rates of increase, however, are in opposition to the goal of optimizing switching losses. Hence, to reduce motor insulation stress, the US
[Nem93]
Standard
indicates that inverter-
designed to withstand risetimes of 100 ns at DC Link voltages of 860 V. Furthermore, temporary dvce/
SI—
Overvoltage protection via gate drive control, possible to use minimum gate resistance [LLSH97].
solution is to
to the
ê
2.12:
makes it
driver.
V dic/dt
inject the avalanche
Control
stability
may be
current to the
which
input of the gate
improved by partial injection both
input of the gate driver and
to the
gate of the IGBT [RK99].
Further, nominal/actual value comparison can be performed in lowvoltage technology, using an external voltage divider to measure the collector potential. The compatibility of this approach with the tech¬ niques for optimizing the gate charge profile has been experimentally For best dynamic performance, a driver proven [GMS95, LB097]. has been realized in thick-film hybrid technique using BJT in linear, saturating mode [GMS95]. The above mentioned voltage divider may include capacitive compensation. A similar circuit is presented in non
[LLSH97];
to accelerate the controller
low-voltage driven highpass is introduced into the feedback path, see Fig. 2.12. The advantage of a low voltage scheme is the adjustability of the clamp voltage trough the control circuitry, allowing for sophisticated control reaction,
a
of series connected devices. See Section 3.1.2.
vCe-control
synchronize
Continuous-time control of series connected
switches,
see
vce(t)
is
frequently
Section 3.1.2.
used to
2.2 Device Protection
31
Device Protection
2.2 2.2.1
Overcurrent Protection
The
higher the collector current during the main voltage transition at turn-off, the higher is the dynamic space charge density in the depletion region. That is, for a given vce the electric field strength in¬ creases with ic. It may exceed the critical field strength for avalanche multiplication. This condition is referred to as dynamic avalanche, which dictates at distinctly lower voltages than determined by static avalanche requirements. As a benchmark of reliability therefore, the turn-off capability under hard-switching inductive-load conditions is specified by manufacturers. In normal operation, the IGBT collec¬ tor current is primarily determined by the operating-point-dependent transconductance and the applied gate voltage, for the linear region 6 given by: %C
r>-J
-L*-f-L*-p
(Vge
-
VT)vce
~
-kfV?e
for
Vce
ce-limiting schemes unsuitable for controlling series connected IGBTs
dynamic losses and delay are reduced + damping of oscillations caused by system parasitics o high controller speed needed (to avoid antagonizing +
control) -
Vce-Hmiting
unsuitable for
feedback of
series connected IGBTs
controlling while
exceeding a predefined die/dt-control during turn-off + improved behavior during short-circuit vce
limit
+
+ protects series connected IGBTs o mismatched transients of series connected IGBTs continuous time feedback of
Vce
vce
+ protects series connected IGBTs + die/dt-control during turn-off o
requires scheme for reducing dic/dt
(snubber, Vce
master-slave
advanced reference
deviation from
a
at turn-on
signal)
master transition sets
gate
current
+ protects series connected IGBTs + no explicit reference signal required
(also -
(due ic
works with
techniques above)
limited to 3 series connected devices
use
to
complicated measurement)
transfer function
ic(vge)
+ control of static load of
(IGBT;
to set
T(vCeic)
parallelized single-switches
diode control limited to small
variances)
discrete-time
ic{nT), Vce{nT)
synchronization of events and/or sampled data + control of dynamic and static load of IGBTs (diode control possible for parallelized half-bridges) fails under unexpected or nonlinear conditions -
(unsuitable -
for combined
does not compensate for
series/parallel IGBTs) sampling
time skew
nonlinear control Vce
cluster gate drive + suitable for combined +
dynamic
series/parallel
IGBTs
losses reduced
+ built-in fault tolerance complex control required -
Table 4.2: IGBT gate drive
techniques, closed loop control.
4.2
System Topology
—
53
reduction of load current
(locally
autonomous modification
of
globally defined switching commands, signal to higher level of control) —
Redundancy •
sending
voltage reduction (requires sending higher level of control)
DC link to
or
related to controller
a
a
status
status
signal
circuitry
provided by hardware —
—
fail-safe interface to local control
global
controller
circuitry providing system monitoring and
managing system shutdown
in
case
of failure of
a
higher
level of control •
provided by software —
hierarchical decision in tification of events
changing cal —
4.2.2
or
a
of critical state detection
(iden¬
triggering switching activity such
as
set-point during transition, identification of lo¬
system
plausibility
case
failure)
check
(based
on
knowledge
of system
behavior)
Example
provide redundancy, modules are parallelized in a The modules are driven by individual local con¬ row configuration. trollers. Each row is connected to a global controller via two fiber optical channels. The communication between the modules within a Redundancy
To
voltage technology, paying attention to the effects of transient mismatch of control-emitter potentials. Such rows The re¬ are series connected to form a cascade of rows, see Fig. 4.1. configuration algorithm is very simple: any detected single fault in a row (concerning module, gate drive, local power supply or interface) leads to permanent switching on the row, which is now dominated by the faultless modules. Thus, a possibly time variant fault behavior is irrelevant. During IGBT off-state and during switching transients the DC link voltage has to be balanced over N-1 rows. Secondary reconfiguration adapts parameters for controlling vce or dvce/dt. row can
be realized in low
Hierarchical Controller Architecture
54
IPM local control of dv/dt and di/dt
central controller
host
synchronization
§
hardware
redundancy
parallel connection of shared fiber optics interface row :=
IPMs
reconfiguration switch
a
faulty
row on
controlling module temperature
Figure
4.1:
r
Reconfigurable system topology
of
a
single-phase
VSI.
could be refined when
performing a failure clas¬ sification. In some cases a steady off-state of a single module can be guaranteed. Then, the switching activity of the row can be kept up. Secondary reconfiguration may adapt parameters for controlling ic or dic/dt, e.g. to reduce power dissipation. An effective method is to reduce the average ic, which is preferably done by higher level of Reconfiguration
control. One option is to In
case
subject
parallelize only a few, in particular two modules. of failure of one module, the other module is temporarily
to twice the nominal
switched off within To maintain
a
a
current, which suggests that it should be
definite time.
defined
Reconfiguration is done as follows: switching state, the faulty row is permanently
4.2
System Topology
switched off. The
on.
55
The faultless
voltage
across
within the maximum
of the
rows
the faultless
rating. To
rows
in
cascade
are
switched
has to be controlled to stay
switching capability, it is rows, or preferably multiple
maintain
multiple cascades of parallel (see Fig. 4.1).
necessary to connect
halfbridges,
faulty
voltage has to be balanced over the faultless rows. System state processing and parameter scheduling ask for a hierarchical controller strategy. Global control is responsible for reconfiguration management and parameter scheduling, and may include the functionality of synchronizing static and dynamic load of parallel and series connected modules. Local control is used to optimize each IGBT module's dynamics. Controllability
The cascade
Two modes of module
distinguished, IGBT mode and diode mode, depending on the actual sign of the load current. IGBT temperature control is easily attainable by means of the applied gate voltage during on-state. Turn-on timing control should be used to keep SO A conditions. The behavior of the FWD can be influenced by controlling the temperature of the IGBT/diode module. Due to the large thermal time constant, the module temperature might be kept constant during diode mode, assuming a load current time constant operation
can
be
smaller than the thermal time constant of the modules.
applications usually
meet this
Traction
requirement.
of unidirectional load current
(e.g.
for
step-down con¬ verter) the mode of operation usually remains constant. Up to a certain degree, diode temperature control in its off-state is possible by enabling small cross currents delivered from a parallel connected In
case
a
IGBT. While the control of total collector current in tion
compensates for individual leakage
distribution of vce, this current
can
be
currents and
unevenly
a
series
so
connec¬
manages the
distributed between
parallelized modules to control the device temperature. Assuming a switching period smaller than the thermal time constant, this can be utilized to influence the current-distribution during FWD on-state. The balancing capability of this principle is very limited, primarily as it is based
on
increased off-state losses.
The temperature distribution between series connected switches is controllable
by determining
an
asymmetric distribution of
vce
m
Hierarchical Controller Architecture
56
combination with the
applied ic.
So, assuming
switching period smaller than the thermal time constant, the reverse recovery charge distribution in a cascade of rows can be modified in certain degree. Thus, the transient voltage distribution during diode turn-off could be influenced. The balancing capability of this principle is limited by the increased off-state losses and by the allowable off-state voltage unbal¬ ance depending on provided redundancy. Much rather, diode voltage distribution could be controlled by the parallel connected IGBT. a
Summarizing, voltage and temperature distribution is controllable in each system state. However, the transient current-distribution of directly parallelized diodes is virtually not controllable. Moreover, the balancing capability of temperature control is strongly limited. This limits the turn-off speed of parallel connected diodes, since a partic¬ ular diode is subject to an uncertain maximum di/dt up to the total di/dt of the row. Therefore, parallel connection should be restricted to about five devices of similar
pability
should be done
4.3
Control
type. Further increase of
current
ca¬
by combining similar terminals showing lower di/dt. For example, parallelized half-bridges can be completely bal¬ anced by average current control, as described in Section 3.2. Then, temperature control of a diode-mode row can be achieved by control¬ ling the turn-off timing of the IGBT-mode row.
4.3.1
Concepts
Current- and
Temperature-Distribution
As
explained before, current-mode gate driving is preferred to opti¬ mize control dynamics during switching transitions. However, provid¬ ing an individual vge > vt to adjust the on-state current distribution of parallelized IGBTs (according to Eq. 2.7) may increase complexity and average power consumption of
a
current-mode gate driver. Fur¬
thermore, the dynamics of ic during on-state are dominated by a large time constant in the range of microseconds, determined by the IGBT's on-state differential resistance and the inductance of the wiring be¬ tween the modules, which are a typically about 4mfi and 14 nH, re¬
spectively (for planar-gate
class).
NPT IGBT modules of the 1200
The time constant could be decreased
V/300 A
by temporarily operat-
4.3 Control
Concepts
ing the IGBTs
Therefore,
57
in the saturation
suggested
it is
to
tion to control the average
region, which
use
ic of
pulse-width
a a
is controllable via vge.
module.
-density
or
modula¬
That is, the sequence of
the
command, managed by a higher level of control, is modified by local control according to the difference of an estimated actual load value and a predetermined nominal load value, e.g. device tempera¬ ture. This is done by introducing additional pulses during on-state or by deactivating a module for a long period. Basically, a predetermined subset of devices provides switching activity within a particular num¬ ber of cycles. For parallelized devices operating at a fraction of the nominal DC collector current (to provide high-frequency operation), a locally generated stochastic allocation is proposed to balance the aver¬ age current distribution while simplifying control and communication needs. In
particular
at
turn-on, adjustment of delay
or/and gain
should be
used to
synchronize the switching transitions. At the end of transition, when approaching the linear operation region, the short-time average of ic is adjustable by discrete-time control or by nonlinear hysteresis control. The latter applies a binary signal to the gate, which state is a function of the actual ic and predefined boundaries. These schemes take the advantage of alterable (via a large change in vge) dominant time constant of the control
Voltage
4.3.2 To attain
ceed the gate threshold
turn-on,
a
to achieve fast response.
Distribution
controllability,
condition is
system
inherently
the
gate-emitter voltage
voltage. During
fulfilled for IGBTs
late command within
a
is
requested
to
ex¬
the turn-off transition this
requested
to
clamp
vce-
At
series connection of IGBTs may
controllability. This holds true for clamping schemes applying avalanche devices, assuming high sinking capability of the gate drive. This problem can be avoided by using a current source driver, which current-sink path is deactivated immediately before the cause
a
lack of
IGBT turn-on transition.1
Generally, to avoid
for
a
certain
period
dfce/dt-susceptibility,
after
see
turn-off,
current-sink
Section 2.2.3.
capability
is
required
Hierarchical Controller Architecture
58
actively controlled col¬ lector current and the externally induced current charges the equiv¬ alent capacitance Cce seen from collector to emitter of a particular single module or logical switch. This might be avoided by adapt¬ ing the active current according to the measured voltage distribution. Providing active current by continuous-time operation of IGBTs has been suggested in the literature, see Section 2.1.4. In consideration of the high-current capability, overdetermining the control system (more 1 active controllers) should be avoided. Otherwise, limit¬ than N ing of active currents is required to avoid high shoot-through current. For parallel connected IGBTs, this could be guaranteed by reducing the number of activated IGBTs. Since for particular devices vge ex¬ ceeds the threshold voltage, the system is susceptible to dvce/dt-noise. During regular off-state this may be tolerated, but it is critical during a regular switching transition of any switch within the system, see Section 2.2.3. This suggests the definition of a multiple-phase transi¬ tion control, which achieves a safe state (in particular vge 0) before actual switching. This implies an adequate command coding, which Quasi-static
off-state
The difference of the
—
=
informs the switches about scheduled transitions within the system.
Apart from these effects, however, continuous-time operation of IG¬ BTs at high vce might influence the rate of failure, e.g. induced by cosmic ray
The
dvce/dt-immunity
BTs and
the
[Zel94, KSG94].
same
of up to
is correlated with the number of active IG¬
improved by activating as few IGBTs as possible at time. During regular off-state, a leakage current difference 20 mA and an equivalent capacitance Cce of 0 ^nF yt^~
can
be
only N * 40 V/us. (According to Eq. 4.1 and typical parameters of planar-gate NPT IGBT modules of the 1200V/300 A class.) Thus, discrete-time- or nonlinear hysteresis con¬ trol of vce is applicable. Within a permanent, stochastic or subse¬ quent allocation, the gate is temporarily charged when the error in vce reaches a predetermined threshold. After that, the gate is discharged to a safe level, see Fig. 4.2. Note, for a commonly used nonresonant gate drive supply somewhat higher energy demand results, depending on particular Cce, gate charge, and hysteresis. cause a
maximum
dvce/dt
of
4.3 Control
Figure a
59
Controlling
activated at the
are
of
4.2:
Concepts
nonlinear
same
hysteresis
IGBT turn-off
during off-state. As few devices as possible time to provide dvce/dt-immunity. Example
vce
control.
Initially,
IGBT rises to the DC link little
changes.2
Within
a
the collector-emitter
voltage
series
voltage
of
single current only
while the collector
a
connection, fast driven IGBTs achieve
higher vce-endpoint. Using dvce/dt-control, vce is strongly related to delay and so delay control based on a finite settling time design is applicable. Additional voltage imbalance results from different tail currents in the following transition of ic. Due to the decreased switch¬ ing speed in the tail phase, a still active conventional dzc/(it-control could interfere with an autonomous vce-limiting scheme; the control¬ lability is lost, if the inversion channel of the IGBT gate is removed. Thus, it is more advantageous to control dic/dt indirectly by observ¬ ing the overvoltage caused by the DC link stray inductance. However, conventional di/dt-control is very suitable for controlling the transient current sharing of parallelized IGBTs. a
Diode turn-on
An active diode forward current is first
the time when all series-connected diodes the direction of the current 2
The collector current
through
changes according
which at turn-off may be
capacitance Cce, capacitive part of the load impedance.
the
are
possible
forward biased.
at
Since
series connected diodes is the to the
dvce/dt
noticeably
across
increased
the
by
equivalent
the effect of
Hierarchical Controller Architecture
60
same, the
reverse
voltage
accordance with the off.
No
cause
across
each diode is
dvce/dt applied
overvoltage
can
Individual device parameters may
occur.
transient mismatch of
to the
strictly decreasing in IGBTs which are turning-
dvce/dt.
However, the diode
turn-on
switching losses do not vary significantly with load current, and are typically less than 2% of the total switching losses at nominal load current.
Diode turn-off
The
ries connected diodes. cause
an
or
current flows
However, individual
asymmetrical
less stored
same
voltage
transient
faster removed
excess
through
excess
each
carrier
distribution.
carriers earlier
one
of
profiles
se¬
may
Devices with
support the main
higher dvce/dt. This results in a mismatch of power dissipation. Synchronous switching of series connected diodes means that dvce/dt(t) is nearly the same for each device. If the total dvce/dt can be estimated, for example by using dvce/dt-control for the IGBTs, fast recovering diodes can be identified by showing higher dvce/dt than expected. The difference of actual and nominal value of dvce/dt might be used to activate a compensation current in parallel to the diode to slow down the transition according to Fig. 4.3. voltage
transition
This
or
show
straightforward approach
trol system is overdetermined
as
suffers from the fact that the
the control rule is
even
satisfied
con¬
when,
in addition to the rent is
required compensation current, a common bias cur¬ provided. To lower system complexity, it is suggested to utilize
the controllable collector current of
an
IGBT/diode-module.
Fast
ac¬
requires precharging the vge toward the threshold voltage. Consequently, unwanted gate charging induced by dvce/dt may cause
tivation
excessive collector
This
might
current, the limiting of which is
be avoided
by invalidating
an
easy task.
the activation of the
particular
not
IGBT associated with the slowest diode. A similar way is to control the gate
charge as a function of the voltage distribution of a previ¬ ous cycle. This could be realized by applying a particular vge during transition. As it seems mandatory to utilize active vce-limiting, there is enough time to identify the recovery behavior while maintaining system safety. The validity of active vce-limiting for protecting series connected diodes has been experimentally proven [GMS95], see Sec¬ tion 2.1.4. According to Fig. 4.3, combining dvce/dt-control and vce-
4.3 Control
Concepts
61
Hlc4
Hld4
v
$
'ce4 ,
dvce/dt
t'c3
fi
dvceref/dt
U'd3
|
dv/dt control H'c
y
'ce1
di/dt control
150
600
'ce3
400
100
50
1 vce3
'ce3
'ce4
'ce4
200
'ce4 0 J 0.002
,
0.0015
g
40
-,
30
0.001
< 20
500 u
10
0
0
>
10
—
100n
200n
300n
400n
500n
t(s)
600n
0
100n
200n
300n
400n
500n
600n
t(s)
during turn-off of series connected diodes. Diode with index 3 is modified by decreasing temperature by 60 K toward 340 K, and increasing active area by factor 1.02. Schemat¬ ics (top) and simulation results (bottom); controlling dv/dt to achieve balancing (left, solid lines) in comparison with natural distribution (dashed lines); additionally providing vce-limiting (right). Figure
4.3:
Voltage
distribution
E4
Hierarchical Controller Architecture
62
freewheeling diode
DC link
load current
index 2 for
N-1
higher-speed
modules
'd
tA'c C
In
68A/V and dic/dt a
1200V/300 A class (CV 2.5A/ns) the gate current is smaller than 0.88 A. A gate current viation of 20% and C^ 0.3 nF will cause dvcei/dt < 0.59 V/ns. of the
=
=
a
maximum duration of
phase As of
240
ns
this results in
a
=
de¬ For
voltage
drift of less than 142 V.
But, if conventional dic/dt-feedback control is applied, specific loop transfer parameters cause a large error in the gate current: In
Fig. 4.5, the assumed
sensor
gain of module
1 is
10% larger than that
open-loop gain is 10. Thus, dic/dt of module 1 is higher than expected, and the controller stops gate charging. The equivalent capacitance Cce is now being charged by the active current of module 2, nominal
of module 2
according
to
(4.4). (Dashed lines.)
The
resulting dvcei/dt
depends on the kind of limitation of the feedback current. In the case shown, the gate current of module 1 is controlled to zero while that of
Hierarchical Controller Architecture
64
PhaS6S
A1
A2
/"" ./"
A3
800-
o
3--
Vce2
"""""'^^
-400 -
_^
400
-
~~7^
vce 1
IC2\^S^ ^ synchronous synchronized
Figure
~~~y^
4.5:
sampling
turn-on at
sampling
time
~~~~~~
via
—-
— __
4
50n
4
vce2
200
100n
time
(s)
time
delay
Drift of vce at turn-on caused
by
conventional
dic/dt-
[Ber91, RK95, RKFR97] applied to series connected IGBTs. (Simulation results. For clearness, stray inductance related voltage drop has been removed by waveform processing.) control
module 2 is controlled to
As
a
minimum
dvce/dt
gate
2A@(t=50ns),
current is set
or
the
1
A@(t=150ns).
loop gain
is
If in
reduced,
a
phase lower
[Ger95] achieves voltage equalization in one single point, but inadequate dzc/(it-control results in a voltage drift with different sign before and after this point (solid lines). results.
Conventional
delay
control
possibility to identify dzc/(it-deviation is to use multiple sam¬ pling of vce- Referring to Fig. 4.5, the combination of delay- and A
(izc/(it-control
parameter deviation
causes
local extrema of
vce(t).
De¬
adapted until these extrema disappear. Thereafter, ad¬ equate voltage distribution will be achieved by adapting the control of dic/dt versus time. The approximate delay divergence can be ex¬ tracted by the time difference between local extremum and starting
lay
has to be
point of vce-transition. In the above
dvce/dt
example,
of approx. 1.5
a sensor
V/ns.
parameter resolution such
a
variance of
1% would
cause a
With respect to the
methodology
is
required controller virtually inapplicable un¬
dvce/dt-induced part of collector current is removed from mea¬ dic/dt, as realized by connecting an additional large capacitance
less the sured
gain
between collector and emitter.
4.3 Control
Concepts
65
Determining dic/dt
4.3.3
via
vce-Control
Preconception Controlling dic/dt via Le becomes difficult to im¬ plement when Le reduces (as expected for the future) or when Le is not directly accessible. Furthermore, at turn-on the takeover of dvce/dt is critical when approaching the peak of the reverse recov¬ ery
current, where
vce is
already sinking: Trying
to maintain
dic/dt
results in infinite
high gate current such that nonlinear effects could affect the controller speed. Overriding dic/dt-control takes a certain time required for activation of dvce/dt-control. For the time being, therefore, high ig induces rapidly falling of vce- Moreover, this dic/dtcontrol scheme is inapplicable to series connected IGBTs, as shown above.
phases A and B of higher phase A, dic/dt is deter¬ mined by controlling the collector-emitter voltage step Avce caused by the DC link stray inductance A turn-on process is divided into and lower diode conductance, Fig. 4.6b. In
Solution
AvCe
=
dic/dt
( ^r
-
Lee
(4.5)
J
where Lce is the inductance between the terminals from which the
vce-feedback signal In
is derived.
to the
opposition
delay
control
technique, where
an
iteration
dead-time is present, the vce-derived control is able to limit overvolt¬ matter of
principle. The overvoltage of a faulty or slow mod¬ ule is limited to the sum of the individually controlled Avce- Thus, in absence of global fault feedback, the maximum number of series connected modules is limited, since the controlled voltage step should be only a fraction of the maximum single module rating. To overcome this, an initial step could be introduced aimed at reaching controlla¬ bility before starting the actual set point function. Furthermore, there is an alternative to allocate a specific Avce for each module. When age
as a
the
excess
of carriers stored in the diode
p+n~ junction region
moved, the conductance of the diode approaches gate
current goes to
zero
to maintain the desired
zero.
The
is
re¬
required
Avce (according
to
Eq. 2.2). The collector-emitter voltage drops beyond this point as a result of enhanced open-loop transfer factor (see Section 4.3.4) and
Hierarchical Controller Architecture
66
dvrpref/dt command
:
max()
rc
-phase
Avceref(t)
A
or
B
Cfb'
current
'
mirrors
(a) 600A
Avce (t) 600V
phase freewheeling diode
,
A
phase
,
non
conducting
B
conducting
(b) Figure
4.6:
Integration of dzc/(it-control
into
a
vce-control scheme.
Phases A and B of different conduction states of the diode
are
structure
free-wheeling
detected to determine the set point function
according
to the
denote main criteria to
respective dic/dt
identify
or
the start of
applying dvce/dt-control (a) and simulation compact modeling (see Appendix A).
dvce/dt.
phase
result
B.
or
controller
The markers Basic concept
(b) using
nonlinear
4.3 Control
Concepts
67
Integration of dzc/(it-control into a vce-control scheme. Basic concept applying vce-control during phase B. Providing an auxiliary criterion identifying phase As required for controlling un¬ Figure
4.7:
matched series connected IGBTs.
limited gate current slew rate.
dic/dt to
is reduced
identify
these main
(according
the start of
criteria.)
detection threshold is
vce(t)
a
(The
Fig. 4.6b denote first implementation (see Chapter 5) the
phase
In a
to
Furthermore, the absolute value of Eq. 2.1). These signals are evaluated
B.
markers in
function of the average of
VLe(t)
or, alterna¬
phase A. By providing a minimum unidirectional gate current, a lower boundary for dic/dt in phase A is fulfilled even under the condition of an undesired limit cycle of control system re¬
tively,
of
in
sponse.
In Phase
B, the collector-emitter voltage either is controlled by dvce/dt (Fig. 4.6a) or by vce(t) (Fig. 4.7). The latter method is advan¬ tageous due to an introduction of a dominant pole into system dynam¬ ics, see Section 4.3.4. But higher linearity and complexity of controller circuitry is required. Note, a dominant pole could also be enabled at the start of phase B to ensure control stability within dvce/dt-control while maintaining system speed during phase A. The circuitry al¬ tering the control structure e.g. according to the marcQ-operator in Fig. 4.6a, could be simplified as follows. A shared nominal-value signal aref (t), preferably a step function, is used and the actual-value signal is a linear combination ,
a(t)
=
ci(£) vce(t)
+
c2(£) dvce/dt(t).
phase B the coefficient c\{t) is set to zero, so vce(t) can change beyond a(t). Note, \dvce/dt\ in phase A changes as a function of
In
Hierarchical Controller Architecture
68
vce(t),
but this is irrelevant in
case
of lower La.
For unmatched series connected
mentioned main criteria
IGBTs, referring to Fig. 4.4, above for detection of phase B may already be ful¬
phase A2, wherein ic remains constant and using the pro¬ posed vce-control the ig of higher-speed modules is reduced to zero (according to Eq. 2.1). To avoid this, an auxiliary criterion identi¬ fying phase As (see Fig. 4.7) to validate the main criterion could be filled in
-
elapsed after the turn-on command (con¬ sidering a maximum duration of phase A2 according to a maximum delay divergence), or according to a minimum ic exceeded, or prefer¬ ably combining these conditions. At a higher level of control, phase As could be validated by majority logic. Considering a minimum du¬ ration of phase As (typ. 240 ns), a relatively low channel capacity may be sufficient for a centralized processing. Compared with this, a cen¬ tralized identification of phase B requires very short signal delay to provide for minimum switching losses. defined
according
to
a
time
with
controlling parallelized IGBTs Both dur¬ ing turn-on and turn-off, the total dic/dt of a row is now controlled via Avce, but the individual dic(t)/dt of M parallelized subswitches are not yet determined. Particularly for high-gain control systems providing individual gate currents for parallelized IGBTs, slight pa¬ rameter variances may lead to large collector-current imbalance, and In the worst case, temporarily only a thus to thermal imbalance. single subswitch supports the desired Avce according to Eq. 4.5, re¬ sulting in a dic(t)/dt higher than scheduled by a factor of M. It could therefore be necessary to adjust individual command delay and loop gain (or in phase A, individual set point of Avce) to synchronize dic(t)/dt. Thereby, the total transconductance is also stabilized to keep the desired performance of the control system. This adaptation is preferably done during startup of the system. During regular oper¬ ation, a malfunction is temporarily restricted to one single subswitch. Compatibility
So the
dic(t)/dt
is bounded to
Since the total
dic(t)/dt
dic/dt
is
M/(M
—
1)
determined
times the nominal value.
by
the
sum
of individual
parallelized subswitches, oscillation of individual dic(t)/dt may occur while the total dic/dt follows the control law. (This prob¬ lem has also been observed for driving parallelized chips or modules of
4.3 Control
by
means
use a
Concepts
of
69
a common
secondary
direct
driver.) Thus, it may be advantageous to control of dic(t)/dt to damp these oscillations. gate
This could also be used to improve the current distribution turn-off to avoid
Minimum an
IPM
or
dynamic
during
avalanche.
functionality required
To reduce costs of
for IPMs
to limit the above mentioned
dic{t)/dt divergence,
it may
be
advantageous to apply vce-control only to a subset of parallelized IGBTs. Then, redundancy can be provided as follows. At least two subswitches offer full functionality, one of which is used as master. The system response is being monitored and, if not as requested, an¬ other subswitch is set as master. The gate current signal of the master is transmitted to the slave drivers, which control functionality can be simplified to adjustable gain (to compensate for slew rate divergence) and adjustable average gate current during the phase of achieving con¬ trollability of vce or ic (to reduce or increase delay). Note, during the main transition, introduction of delay into the gate current signal is not applicable since this would seriously affect the closed-loop control performance. One option is to combine the ber of slaves into a
a
single
functionality
ASIC which
number of IGBTs and for
driving
a
can
of
a
master and
be used for both
large single
a num¬
balancing
module.
Compatibility with soft-switching The new vce-control method is fully compatible with soft-switching. In case of ZCS turn-on, the initial Avce is set low until the start of phase A3. Hereafter, dvce/dt and Avce are set such that vce approaches zero within a certain time. Then, dic/dt is determined by Vdc/La. Detection of phase B is not required as the main transition of vce is already applied to phase As. For hard-switching turn-off it has been proposed to apply the maximum available
ig until C^ is reduced in such a way that the gate driver becomes capable of controlling the desired dvce/dt. For ZVS, this might cause high dic/dt depending on the particular application possibly affecting EMC. Short-circuit shut
case
off), dic/dt
turning-on the IGBT (when the FWD is controllable via Avce- For the case of a short
After
is not
Hierarchical Controller Architecture
70
inductance, dic/dt
circuit via low
circuitry
is very
such that the control
high,
may not be able to reduce vge to
safe level.
a
observing ic or dic/dt may vce(t) is not required for turning
control
secondary
chronization of
Therefore, be required. A syn¬ off the IGBTs under
short-circuit conditions.
4.3.4
Control
In the
Preconception tion
sic(s)/ig(s)
resistance is the
has
Laplace plane
a zero
at sce
=
L
s
ô +
=
~}r
where rce is the differential
(which basically
link). By
of resistances of FWD and DC
sum
ju, the transfer func¬
from the IGBT's collector to emitter
seen
large gate
Behavior
System
resistance of
means
of the
current-mode gate
driver, the initial sys¬ splitted into two real poles
a
tem's dominant
complex poles s3\, s32 are stç) and sti, whereby sî0 is moved toward the location of sce which pro¬ vides a constant magnitude within s%o st\, where \st\\ is lower than the frequency corresponding to Sji,Sj2 providing a first dominant pole. These modifications make it easier to set a sufficient control ...
-
system step
response.
Simplified model According to the model shown dic/dt in phase As can be approximated to si
(s)
~
_(i2H. C*
The denominator of
s2T2
Eq.
(Cm
s2
4.6
+ s2dT+l
+
can
Co)LCT
s%f^„
be rewritten
(sT,i
=
+
+
l)(sTï2
where the first and second dominant
poles
+
in
i
Fig. 2.2, the
(s\
(4 q\
+ 1
as
1)
for
d>l
are
Ttl^^-La, Tt2^^(c^+C-a The
dvce/dt
in
phase
B
can
SVce(s) Phases
Ai and A2
are
be
«
approximated
-—
Om
S
1%2 + 1
rather modeled
as
ig(s).
by Eq. 4.7, considering
conductance of IGBTs in series with still active IGBTs.
(4.7) low
4.3 Control
Concepts
71
The gate current is affected by a resonance formed by the total gate loop inductance Lg and the driver output capacitance Cdr'-
'iM
=
CdrLgS*
+
CdrRss
+ X
id"«
(4'8)
far smaller than the IGBT input capacitance, where idr is the driver output current. If the external gate resistance
assuming Ccir
is
by
would be increased to achieve
adequate damping, the high current capability of the gate driver would be lost. Hence it is suggested to use an auxiliary damping resistance Rx acting at high frequencies (via a capacitance Cx) in parallel to the driver: sig(s) 1dr\S)
CXRXS+1 _
(jdr-Lig(jx-ti>x
-\-
S
(_Gdr
Small-signal AC-response pected d, T%\, T%2 are
~T~
Cx) -L/g
For
a
S
-\- (jx
\-ttx
IGBT
large
~T
t*>g)
G-tt
d
1
21 nH
100 nF
9.1
157
ns
0.47
ns
2
8nH
60 nF
9.4
100
ns
0.28
ns
3
21 nH
600 nF
1.5
26
ns
2.8
ns
Semiconductor parameters
comply
Ttl
with 16
i
module, the
La
set
100n
0.0
-0.5
-1.0 JLa -1.0
—I—
—I—
-0.8
-0.6
—I— -0.4
-0.2
0.0
Re(nu)
Open-loop small-signal AC-response of a linearized vcecontrol system using parameter set 10 for phase A varying gm (solid) and for phase B (dashed); Bode plot (top) and Nyquist plot (bottom). Figure
4.9:
Nyquist
criterion indicates
global stability.
Hierarchical Controller Architecture
76
Modifying System Dynamics
4.3.5
IGBT Transfer Function
-
Pole
Assignment
Eqs. 2.1, 2.2, 4.6, 4.7 the IGBT transfer functions could be altered by increasing CV, C^, by modifying Rg or Le\ or by em¬
According ploying
to
inductive
formed to
a
coupling
from emitter to gate which could be trans¬
modified Le\-
In Section 2.1.3 it has been
proposed to use an additional gateemitter capacitance to modify the dynamics of an IGBT module. Having no access to the internals of a module, the path comprising Lei and gm can not be externally copied with higher accuracy. So, a proportional current sharing between internal and external CV is unattainable. At
high frequencies, the phase margin is increased due to the voltage across Le\, see Fig. 4.10 (top, the region of 7MHz). This might be an advantage: Control stability is kept up to go < 23dB considering a phase margin of 45°. By omitting Le\, absolute stability is kept up to go < 15.5 dB (go < 8 dB to retain 45° phase margin). Using Le\ and increasing CV on-chip keeps absolute stability up to g0 < 20dB (go < 14dB for 45° phase margin). Gate Driver A
promising
feedback, gate
or
see
-
Pole
Assignment
and Linearization
way is to linearize the driver
Fig.
current is
of local
(bottom). Variation of gain with temperature reduced, dvge/dt-capability and differential output
enhanced. The driver
speed
are
decreased
gain. The modified system
phase margin of
is enhanced at the cost of
is stable up to go < 21.5 dB for
45 °.
System State Variable Pole
means
4.10
resistance
a
stage by
A
assignment
Feedback Control
rigorous modification of the dynamics of the
system x
is achievable
xT in
Ax + Bu
feedback for
a
subset of the state variables
[vdr, ig, Vge, vce, ic] via a matrix F such that (A + BF) x see the scheme in Fig. 4.11.
=
x
by using
=
=
,
u
=
Fx
resulting
4.3 Control
0J
Concepts
77
-500d+ 1 OKHz
Figure 4.10: AC response of the linearized dic/dt transfer function of a large IGBT module. Capacitance CV increased to enable a higher gate current
ig
=
7.2 A to enhance driver stage bandwidth
stage linearized by
means
of local
feedback, ig
=
1.7 A
(top). Driver (bottom).
Hierarchical Controller Architecture
78
Figure
4.11:
State variable feedback control.
state variables
iary variables
(coefficients «o «2? «4) (coefficients «3,^5). •••
Direct measurement of
and approximation via auxil¬
Feeding back ig increases the imaginary part of the gate resonance frequency Im(so), while the real part Re(so) remains unchanged and so the damping factor is decreased. This is equivalent to reduc¬ ing Cdr, so a similar result can be achieved by feeding back dvdr/dt. By feeding back Vdr, the real part Re(so) is being increased and the imaginary part Im(so) is being decreased. Furthermore, to keep the IGBT's pole Sio near zero, vge must be fed back by the same factor as Vdr, but with opposite sign. This measure compensates for the voltage drop across Rg and Lg. Note, a too high coefficient for vge results in Re(sio) > 0 and thus causes instability of the control system. How¬ ever, this parameter sensitivity is not critical, since the drift of vce is slow according to \sio\ 0; so dic/dt and dvce/dt are not affected during a switching transition. (But, during quasi-static off-state this -
~
kind of feedback may be not
Implementation
sufficient.)
The simulated system response for the
case
of
feeding back Vdr vge is shown in Fig. 4.12, signal la. The initial sys¬ tem complies with that shown in Fig. 4.8. An approximation of vge is required unless there is no additional terminal available for monitoring the module internal gate potential. A suitable model simplification is to regard only the path comprising RgjLgjC^, see signal 16. —
4.3 Control
Concepts
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
79
-
-
-
-
-
-
0.0
50n
100n
150n
200n
250n
300n
t(s) 10.0 8.0 6.0 4.0 2.0 0.0
CO
-2.0
T3
-4.0 -6.0 -8.0 10.0 12.0 120.0 100.0 80.0
CD
60.0 40.0
co
20.0 0.0 -20.0 -40.0 -60.0 -80.0
-
Ssaa:;,^
^^^^^^S&ïïw
-
"^^S^j^
-
n -
^s*^i^»»^
-
***"".".*•. -
1b
-
^Ny\ """••..
1a/\
^dr vge)* approximated by measuring across additional \Lg, ^rg multiplied by 9 within controller, (lc). Compared with pas¬ sive damping of gate resonance using Rx, Cx complying with Fig. 4.8, (2a) ; or active damping of gate resonance by feeding back the current through jQ-Rx,jQ-Cx multiplied by 40 within controller, (2b). —
—
Hierarchical Controller Architecture
80
By including a resistor Ra4 in the control emitter path, a singleended signal for ig can be measured. Furthermore, by including an inductor La3, the difference Vdr vge can be estimated; system re¬ —
signal lc. However, a fast linear transconductor is required to realize the feedback circuitry which for a DC-coupled scheme with single power supply may be difficult to realize. Since even a reduced-order ob¬ server for estimating the system state is difficult to implement, a first step toward optimizing system dynamics is to feed back a highfrequency part of the gate voltage to damp the resonance formed by the gate inductance and the driver output capacitance. System re¬ sponses are shown in Fig. 4.12 for the passive scheme of Fig. 4.8 and for an active scheme feeding back a current through a scaled-down model comprising RX,CX; results are signals 2a and 26, respectively. Furthermore, feeding back dvce/dt could be used to scale up the effect of Cp to determine the dominant pole of the system, according to Eq. 4.6. In particular, this is necessary for systems having higher \sn\ (e.g. due to lower La) or lower /o (due to higher Lg); refer to Fig. 4.13, which shows a good performance for feeding back Vdr,vge sponse is
-
-
and «5
dvce/dt (solid lines)
Integrated To
provide
for the
Gate Driver Power
power
supply
for
use a
small capacitance C
when
an
a
case
of
Lg
=
320 nH.
Supply
gate driver, it is proposed in [MHK97]
through
which
a
large capacitor
IGBT is turned off. Diodes and resistors R
are
is
to
charged
used for
rec¬
current-limiting. A side effect of the RC is the increase of the damping factor of the parasitic series resonance of the DC link This may be advantageous for driving series at higher frequencies. connected IGBT modules, since in phase Ai, active damping via the transconductance of the IGBT is difficult to implement. (Generally, the active current must be strongly limited during off-state to avoid tification and
cross
conduction within
4.3.6
a
half-bridge).
Variable Structure Gate Driver
Preconception Previous studies indicate that the control circuitry should provide fewer than three dominant time constants at a fre-
4.3 Control
Concepts
81
o.o -0.2 -0.4
^
-0.6 -0.8 -1.0 -1.2 J
1
0.0
1
100n
1
200n
1
300n
400n
500n
t(s) 10.08.0-
~~~~~^^~'\.
6.0-
>sT
\(3meg, 0)
^"\.
4.0-
\.
^V
2.0-
\
0.073
X
-2.0-
N
vs.
s>v
-4.0-6.0-
\
'^x^C^/A
(2meg, 0)
-8.0-
^„
X.
-10.0-
\
\ \
\
-12.0120.0-
^"^"*-—«Z\
"^>5sv(3meg, 50)
100.0O) CD
"•\V
80.0-
T^sx^
60.0-
1
"ST 40.0m
ce
%^\
n-,\
(2meg, 76)
20.00.0-
N\
-40.0
**
\ \
\\
-
\\
-60.0-80.0
\
\
-20.0-
J II
100.0k
300.0k
1
1
1meg
1
3meg
10meg
30meg
f(Hz)
Figure
assign the gate frequency. Basic parameters comply with Fig. 4.8. Case of
4.13:
resonance
State variable feedback control used to
320 nH. For each case, feeding back 0.25(i>dr high Lg vge) and introducing an additional pole within the feedback path at s —1/1.5 ns. Simulated system response (top: closed loop tran¬ sient, bottom: open loop AC). System with initial dominant pole (dotted). Dominant pole reassigned at su := sa/(l + 0.65), where C^
very
=
—
=
is 1.65 times the initial value is
changed by
lines).
the controller
(dashed lines) by feeding
or
where the effect of
back 0.65
C^ C^ \dvce/dt\, (solid
Hierarchical Controller Architecture
82
continuously controlled
events
defining system
state
set
point
function
400.0
*
I
IIU.
•-
I
I.
—
II
I
1
M
100ns
200mV
..1-
!
I
I
I
Jll
I.
IU.
I
II.
»
*
"
'
*
*
CI BrstWd No ref cross 1st waveform
Chi Ch3 3±
current
with
..l-[J..m.l.l.u,.l...l.J-ll
il
rM
Ch2 Ch4
200mV mi
I
i
m
(2),
and an
a
100ns
200mV ill
>..IX„I.I—11..I-.JJ.
5.7: Driver output current
Figure
2k£7)
'5.00 V
(3)
!
-j-
i
_t_
t.
m
iß by
means
for resistive load
additional RC connected in
..a.._l.
-l-.-L-
I
_.J
in response to the main feedback
which is sinked at terminal
voltage step function;
j
of
a
(Rg
(r 0.833(7),
resistor =
parallel. Top: One cluster
=
acti¬
vated, operating both in nonlinear (before the first step) and linear region at nominal maximum current. Bottom: Seven clusters acti¬ vated, operating in linear region below maximum current. (Signal 36 for Rg 5 (7, scaled down by factor 5). =
Local Controller ASIC
138
Implementation
required for controlling parallel-connected IGBTs, and for clamping the collector-emitter voltage during turn-off. The deviation of the nominal-value signal of about —40% does not indicate a serious problem, as it has been proposed to use secondary control to
adjust
the actual-value
signal.
The measured maximum output current is about 30% below the nominal current.
Only for the turn-on case at low load resistance, the measured current approaches the nominal current. This is due to the following circumstances. To reduce the complexity of the turn-off par¬ titions, v(vdd\) has been used as gate potential of the turn-off output transistors
(common-gate circuit).
In
opposition
to the solution for
the turn-on case, this
voltage does not track with process and temper¬ ature variation, and the voltage is lower than the allowed maximum value. The turn-on partitions have been developed for vdd20\ 20 V and to work together with additional nonlinear partitions which have higher drive capability at high output voltages. So, the measured characteristics are satisfying the demand. According to the process data sheet, the measured current of the DMOS transistors (used in the output current mirrors) at particular =
conditions of this ASIC should be about 90% of the simulated current. A
severe
error
may be introduced
local nominal value current
mirrors)
by
the HV-PMOS
(used
in the
which measured current may
only
approach 75% of the simulated current under particular conditions. But, this should not have an influence to the maximum output current in nonlinear
higher than the boundary used in the current limiting circuitry. According to the process data sheets, the matching of currents used for control circuitry such as current limiting should be within ±10% under the particular operation,
as
the available current is
conditions. In nonlinear
operation, the LV-NMOS
transistors of the second
current mirror of the driver
partition operate
the output current
reacts
strongly
on
in linear
the output
region, where The
voltage.
inal current in nonlinear operation is set such that the current
nom¬
gain
approaches about half the nominal value of linear operation, Vds is only about 0.5 V. So, the maximum output current strongly depends on the particular transconductances of that mirror and on the gate po¬ tential used for the cascode stage. It may be that
potential for higher output
currents.
advantageous
to increase
But note, when
designing
5.5 Measurements
139
regulated cascode current mirror, the slew rate of the control signal is strongly limited and the dynamic performance will be deteriorated. Otherwise, the phase er¬ ror will strongly increase. For the turn-off case, the gate potential of the cascode stage is determined by external circuitry. As the maxi¬ a
dominant-pole control system for
mum
and
output
turn-off,
current is
it
can
be
a
basic
30% below the nominal value for both
concluded, that the
error
transconductances of the output stages. These
speed case
the
process
is approx.
mainly
is
are
turn-on
due to the
within worst-case-
specifications. (The simulated output current for this 22% below the nominal value, or 30% when considering
typical modeling error.) An extraction of distributed
parasitics has shown, that the efficient
gate-to-source voltage of the output transistor is reduced in gree
by
mum
the
voltage drop
output
in the
source
current in nonlinear
current
operation
matching of the large current mirrors, more to optimizing the layout. An advantage of partitions of
routing tances.
a
gate driver
(as
realized in this
some
path. Since the
de¬
maxi¬
strongly depending on attention should be paid a large number of small
is
ASIC)
is that two-metal
adequate to achieve good symmetry and low parasitic resis¬ Note, in this ASIC, the series output resistance due to routing is
is about 6 (7 per
gate driver partition,
rent distribution between most simulations.
For the
to avoid oscillations in the
partitions. This has
given
area
and the
cur¬
not been considered in same
architecture, this
value could be reduced below 2(7.
According to simulations, the driver output current is approx. pro¬ portional to the central reference current. According to simulations, the mismatch of the driver output current due to process variations should be within ±15%. The simulation of the reference current relies
good modeled behavior in the subthreshold region. Consequently, for a redesign it is suggested provide means for tuning this reference to avoid derating. In the current design, the maximum output cur¬ rent is fixed. The limit has been set according to the maximum vgs defined by the SOA for a worst-case-speed process. That is, for a typical-mean process a higher output current could be achieved. For best utilization, one could provide means for adjusting that current on
limit.
Chapter
6
Conclusion
Summary
6.1
A hierarchical controller architecture for systems
utilizing
combined
parallel- and series-connected IGBT/diode modules has been sented. The major benefits of this system are: •
The
proposed topology allows
ior of
•
IGBT/diode
A unified
Taking
optimize the switching behav¬
modules.
approach
to
parallel- and combination thereof is provided.
synchronize switching
series-connected modules •
to
or
into account overall
of
system loss, device and maintenance
cost, the proposed system architecture describes ternative to
Local
commonly
an
efficient al¬
used GTO systems.
medium-gain closed-loop
IGBT transfer functions.
pre¬
control is used to linearize the
Additional control enables structural and
behavioral
adaption of the feedback loop depending on the switching state. Central digital control compensates for thermal drift and static parameter variances in order to balance parallel- and series-connected power switches.
Due to
applied
to
integration of dic/dt-control into a vce-control scheme the IGBT turn-on, this approach exceeds performance and an
141
Conclusion
142
robustness of solutions realized in previous works. The main
object
is
to control the
voltage drop across the system stray inductance while the freewheeling diode is forward biased. The state of diode reverse biasing is derived from the systems state variables and determines the starting point of the main transition of the collector-emitter volt¬ age. An advanced system state classification is applied to allow real¬ time reconfiguration of the controller structure, and thereby obtaining maximum switching speed. Synchronization of multiple modules is based on an evaluation of the time difference between a globally syn¬ chronous and an asynchronous event, which both are derived locally. This avoids the need of high timing-resolution in the optical links to define a global sampling time. To attain sufficient accuracy, signal processing is generally based on a small deviation of signals from an operating point in advance of a switching process. To IPMs
ensure a are
to form
a
redundant and
directly paralleled column of
rows.
(or
to
reconfigurable system, a row.
These
The IPMs
are
rows are
driven
number M of
series-connected
by
individual gate
respectively)
controllers.
The
nected to
central controller via at least two bidirectional
a
rows
at least two rows,
a
respectively) plastic (Communication between adjacent columns local layer, which simplifies scalability). The
fiber optic channels per
the
parallelized local drives
may be based
on
are
con¬
(or
one,
direction, respectively.
could be realized at the communication between
low-cost
optocouplers.
The
reconfiguration algorithm is very simple: any detected single fault in a row leads to switching-on the entire row. Thus, the faulty 1 switches, and a possibly time variant switch is dominated by M behavior of the faulty switch does not affect system safety. Secondary reconfiguration processing might adapt software parameters, e.g. the PWM-pattern to reduce load current and switching losses. —
6.2
Perspective
Road map to driver
technology development The second gen¬ eration of CONCEPT'S SCALE gate driver ASIC chip sets are currently being developed and include the basic functionality required for con¬ trolling parallel-connected IGBTs. However, excessive experimental verifications and further research are required and still under way to
Perspective
6.2
validate the
143
methodologies introduced in this thesis or the respective patent applications. This functionality will be covered within the third generation of SCALE driver technology. new
control
Controller
design Future work could be aimed at diode voltage synchronization (e.g. according to [Tha02]) and integration of more sophisticated set point functions, in particular for the turn-on transi¬ tion. The behavior of the diode could be controlled by the tempera¬ ture
as
same an
function of the average current of the IGBTs attached to the
module
(e.g. according
upper limit of
and
matching
to
[TR01]
and
parallelability depending
on
[Tha02]). Note,
there is
the symmetry of
layout
of diode parameters.
The system controller determines the
particular delay and other
parameters required for parallel- and series-connected IGBTs.
The
algorithms covered in this thesis can be easily implemented within programmable logic devices or embedded microcontrollers. An imple¬ mentation within the local controller ASICs is also feasible.
Power module
design Rigorous paralleling of power semiconduc¬ tor chips could be simplified by applying or adapting the proposed methodology to future intelligent power modules. Further, to en¬ hance system speed and reliability, a matrix of combined paralleland series-connected chips/subsystems could be packaged. To achieve sufficient control speed, the gate loop inductance and internal delay should be reduced, and integrated gate resistors should be omitted. But, for a manufacturer of standard modules, this could be a contrary design goal, since these control parameters could be optimized to ensure safe operation under conventional driving and topology conditions. Nevertheless, a few manufacturers of applicationspecific power modules are open to the customer. System design The classification of system states, derived for VSI and inductive load, should be reviewed with regard to novel system architectures like matrix converters or secondary inverters used for active filtering. Acquisition of device parameters and events, fed back to a higher level of control, could assist linearization of sys¬ tem transfer functions as by compensation for on-state voltage and
Conclusion
144
delay [PJJ97, ML98] and slew rate parallelized inverters and the like.
of control
variables, control of
Appendix
A
Power Semiconductor
Compact
Models Used
for Circuit Simulation
Motivation
Fundamental
changes in methodology of control or topology asks for a high degree of modeling accuracy to achieve scaling and forecasting ability. Frequently, physically based modeling is the only chance to gain insight into hidden dynamics of a compact system, or to observe system
state variables which could not be measured at all
measured without
considerably modifying
the system
Most power semiconductor models available
from the field of microelectronics
scriptions of
current
were
or
not be
dynamics. either derived
or
issued from finite-element de¬
transport theory
[Let97, SWFOO]. Furthermore,
due to
high density packaging and high frequency operation, para¬ sitic effects of layout become increasingly important. An overview of inductance extraction methods is given in [LeoOl]. 145
Models Used for Circuit Simulation
146
Implementation The models used in this
concept
(e.g.
[MVS94, Vog96]
wide drift
project
are
based
which handle
on a
compact and modular
typical regions
region, MOSFET control
units
or
of power devices
diffusion
zones)
as
basic units, which allows
high flexibility to model future devices. In¬ ductances have been extracted by analyzing geometry data using a multipole-accelerated inductance analysis program [KSSW96] or by measurement. Accurate modeling strongly depends on the descrip¬ tion of the low-doped drift zone, because the behavior of the diffusion charge in this region governs the static and dynamic device charac¬ teristics. In modern devices, the charge profile has a ID form over about 90% of its volume [PJE+99]. Therefore, a one-dimensional modeling core module is used, which employs a universal and pow¬ erful numerical technique to solve the ambipolar diffusion equation. This technique is the only possibility for circuit models to consider physically semiconductor technology measures for improving device characteristics, such as particle irradiation for lifetime reduction, step doping of substrate or epitaxial layers as well as double diffused lay¬ This module accounts for all important effects under high injec¬ ers. tion conditions: nonquasistatic ambipolar diffusion, temperature- and injection-level dependent scattering and recombination effects as well as
impact
ionization.
from device
Combined with quasi-static equations derived
physics describing
the rest of the respective structure,
very accurate and CPU time efficient
modeling is achieved. Today, IGBTs are manufactured in high-density processes realizing a drawn MOSFET channel length smaller than 2.5 urn. Quasi-static models of similar integrated MOSFETs give acceptable accuracy for a signal rise time down to 1 ns, which is proportional to the square of the channel length [Aro93]. These models are implemented in an analog hard¬ ware description language (AHDL, SABER MAST has been used) for a solver which allows integration of subcode implemented in a com¬ mon computer programming language. To investigate the behavior of large systems, simulations have been done by using simplified mod¬ els for the gate drives, or by combining the complex description of the gate drives with simplified lumped charge models [MLS97] for the power devices, implemented by AHDL modeling for a common VLSI simulator
(Cadence Spectre).
147
VLSI Simulation Model The
code of power device models
original
language)
MAST behavioral
[Uwee, Hef95] (given
in
being adapted to the VLSI-simulators Spectre and ADVanceMS. The models provide various levels of approx¬ imation regarding hole current and Miller capacitance. A simplified code for an IGBT (used for simulation Fig. A.2) is as follows: /*
(4 parallel
IGBT
modeled:
gate
MOSfet drain
to
modeled:
not
dies
of
is
BSM75GAL120DN2)
transconductance,
capacitance
hole
current,
as
function
of
leakage current,
gate resistance,
temperature dependency,
gate
to
drain
avalanche
voltage
current,
inductances
e
I / —|
b
I
\
g -II I
I c
*/ module
node
igbtsimpleplus
[V,I]
parameter
(c,e,g)
(T,mosscale,Kp,jleak,typeCgd,VCEwarn, init_ic, init_vgc) //
c,g,e;
external
nodes
real
mosscale
Kp jleak init_ic
=
300
from
[0:inf),
//silicon temperature
=
4
from
[0:inf),
//paralleling
=
22
=
0
from
[0:inf),
//leakage
current
=
inf
from
[0:inf],
//initial
collector
from
//mos
[0:inf),
transconductance
//set init_ic
init_vgc
=
inf
from
[0:inf];
[K]
factor
//initial gate //set init_vgc
current
inf
=
to
inf
=
to
ic
skip
collector
voltage ic
skip
{
//vdmos parameter
real
Kf=2.2,
//velocity
theta=0.08,
//influence
saturation param of
kappa=-0.5, //temperature
//driftzone, parameter
A=1.21,
//eff.
area
of
the
whole
Agd=0.7,
//eff.
area
of
the
Miller
Vth=6.2, Coxd=14n,
//threshold voltage //oxide part of the
Cgc=8.5n;
//mos gate
emitter
real
transversal
high
coefficient
to
source
of
of
device
the
Miller
fields
theta
[1]
[cm"2] [cm"2]
capacitance n-channel
[V]
capacitance
capacitance
[F]
Models Used for Circuit Simulation
148
II
in0=20p,
//emitter
//
w=0.0180,
//max.
//
Ne=lel5, Nb=lel4;
//doping //doping
tauh0=200n;
//electron
lifetime
//internal
nodes
// node
[V,I]
b;
vge,
real
jmos, jhole, je,
real
nmobO, nmob_limit, nmobl,
jcbg,
real
veb,
base
current
width
concentration
of
the
anode
concentration
of
the
base
[cm"-3] [cm"-3]
//voltages
real
vbc,
saturation
vbg;
//current
densities
iege; //for modeling
Nb_eff,
Cgd, Cgdj;
//modeling gate
vmi,
//intermediate
//gate
wgd; const
real
ni
const
real
epsi
const
real
qel
const
real
vnsat
=
rbg (b, g)
resistor
(g, c)
rgc
carrier
density
constant
/*saturation velocity
0.9e7;
resistor
capacitance
of
silicon*/
of
silicon*/
of
electrons*/
/*electron charge*/
1.602e-19;
=
doping
width
depletion
/*dielectric
1.0536e-12;
=
drain
to
effective
variable
/*intrinsic
1.45el0;
=
drain
(r=10e6);
//convergence
aid
(r=le6);
//use
predefined
devices
in
Spectre
capacitor cgdmin (b, g) (c=20p); capacitor cbc (e, c) (c=50p); //hole
is
current
not
modeled
resistor
reb
(e, b)
capacitor
ceb
(e, b)
//sdiode
(e, b)
deb
(r=60m/mosscale); (c=10n/mosscale); (Ad
A,
=
scale
mosscale);
=
analog { vbc
V(b,c);
=
vge
V(g,c); V(b,g);
=
vbg
=
veb
V(e,b);
=
//vdmos
current
(check dependency
($analysis("ic")
if
jmos
&&
from
vbc
!=
inf))
{
(vbc>=0)
&
(init_ic
if
hole
current
is
modeled)
1/A*init_ic;
=
} else
{
if((
vbc
>
( vge
-
Vth)/Kf)
&
(vgOVth)) {
Vth),2)/ l/A*0.5*Kp*pow((vgc (1+(vgc-Vth)*theta*pow((T/300),kappa));
jmos
=
-
} else
if((
vbc
Vth)
&
(vbc>0)
(vge >Vth l/A*Kp*Kf*(vbc*(vgc-Vth)-Kf*0.5*pow(vbc,2)) jmos /(1+(vgc-Vth)*theta*pow((T/300),kappa)); &
=
} else
jmos
{ =
0;
149
} }
/*effective doping
jhole nmobO
-0.8*jmos/(Agd*qel*vnsat);
=
nmob_limit if
(not implemented)
0.18*jmos;
=
(nmobO nmobl
=
-Nb
=
ni
nmob_limit) {
0.9*nmob_limit
+(0.l*nmob_limit*tanh((nmobO/nmob_limit-0.9)/0.1)); } else
{
nmobl
=
nmobO;
} Nb_eff
=
Nb
+
nmobl;
*/ else
{
//approximat ion Nb_eff=Nb; }
if(vbg
>
vmi
=
1)
{
vbg;
} else
{
vmi
=
l/$limexp(l)*$limexp(vbg)+lu; //lu
}
wgd
=
Cgdj Cgd
=
=
sqrt(2*epsi/qel*vmi/Nb_eff); epsi
*
Agd / wgd;
Coxd
*
Cgdj /
(Coxd
+
Cgdj);
dot(Cgd*(vbg)); dot(Cgc*(vgc)); icgc (jmos+jhole+jleak); je flow(b, c)
turnonoroff
o
±
3
CO
:
^
r*"1 ^
\ Pin in
ts in
m
ro
:
S
3
S>
>
,_
y
c u
ta m
ihi |
5
CO
V
CD
V
-
*-
a>
'S
CM
g
c
1»
01
D.
ÏÏ
ib25
vbout
w
ng=1
l=18u
Wtot=40u
i25u1
Wtot=40u
w
ng=1
1=1 Bu
u
£ o
a
£ o
a
^^
"
1 8u
ng=56
1=
Wtot=2240u
CN
5
II
II—
J3
A CO
II
O
CO
II
V
A I-»
V
A to
II
CD CJ
V
A
swgenctriz
II
^e
II
Oy
-Û -,
1
|r1 and1
ir"
vdd1
ir'gnd1
»
1
fcr 05
o o
92
Figure C.12: State detection circuitry swgenctrl2 phase A and B.
-
processing of dic(t)/dt and ic(t)
i—j
to
identify
start of
O o
fcs c-t-
o I—J I—J
05
173
•o
turnon
VCE_com0«
Y—
T
-
currcompj3en
-Ov
out
gnd1
cnT
f^T
^"T
^T
H^ suiO—^ gnd1
^ ^^^E: 16
sum
^^
64
32 of
6
bits
128
256
3 uA
504uA
E^h
vb11
ii
lu—rw—rs—rjprTSi—Tp i >1 i >1 i al i >! i sJ=5
m al
bk L-ini U^ Lk LIi
LIi
LL
Lii
Lii
FfB
f|3=5 tf
Lk
M
tir
8uA
H
Bui
18uB
iSu2
(Bu4
(Bu3
(Bu5
DBu6
18u7
S3 d?
tr 05
ra
92 c-tf—».
U^h Uji=W^
P CO
O c-t-
^
fcr
22 0nA
y
05
setling
time
20isec
o o
92 i—j
a
£00u
É
-|M
o
weak nversionon
fcs
3
^H
HuZi
c-t-
o
-©
I—J I—J
05
Figure C.14: Global bias
current
circuitry
curr2
(top)
with constant-current
source
currcell7
(bottom). a
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Dipl.Ing. (M.Sc.) degree in electrical engineering from the University of Magdeburg, Germany, in 1996. My diploma thesis is on new concepts of auxiliary power supply via CAN bus data lines. In 1996 I joined the Integrated Systems Laboratory (IIS) of the Swiss Federal Institute of Technology (ETH) Zurich, Switzerland as a research and teaching assistant. I was involved in a joint project of CT-Concept Technology Ltd. and IIS. Main goal was the development of a Synchronous Intelligent Gate Unit (SIGU). SIGU is aimed on acceleration and synchronizing the operation of series and parallel
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2003
