## Digital Circuits ECS 371? Digital and Analog Quantities. Applications of Logic Design. Digitization. Binary System. Analog and Digital Systems

Digital vs. Analog Data Representation y Problems with analog? Digital Circuits y Hard to measure an exact value. y Noise (or interference) may disr...
Digital vs. Analog Data Representation y Problems with analog?

Digital Circuits

y Hard to measure an exact value. y Noise (or interference) may disrupt signal. y Signal is hard to maintain across large distances.

ECS 371

y Digital systems can process, store, and transmit data more

Dr. Prapun Suksompong

efficiently but can only assign discrete values to each point. y Noise (unwanted voltage fluctuations) does not affect digital data

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nearly as much as it does analog signals.

Introductory Concepts

y Can use error-correcting codes. y Can use compression.

y Analog systems can generally handle higher power than digital

systems. y The real world is analog! 1

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y Even digital systems are really analog deep down.

Digital and Analog Quantities

ECS 371?

y An analog quantity is one having continuous values.

y We study digital logic circuits.

y A digital quantity is one having a discrete set of values

y In particular, this course introduces procedures for the

y The real world is analog!

analysis and design of digital logic circuits. y Two important ideas that you should keep in mind:

y Most things that can be measured quantitatively occur in nature in

analog form.

y Abstraction

y Examples: air temperature, pressure, distance, sound.

y Interfacing between analog and digital is important.

y Hierarchy

y Digitization

Sampling: Discretize the time

1. y

Get sampled values of the analog signal.

Quantization: Discretize quantity values

2. y

Convert each sampled value to a binary code.

2

6

Digitization

Applications of Logic Design

Vertical lines are used for sampling

y Conventional computer design y CPUs, busses, peripherals

y The digital world is much bigger than just PCs!

111 111

111 110

y Networking and communications

101

101 100 100

y Phones, modems, routers

100

100

y Embedded products 011

011 010

y y y y

010 001

001 000

001 000

y Scientific equipment

Time

Horizontal lines are used for quantization

Cars (ABS, carburetion, light controls) Toys (motion and talking) Appliances (timing and sensing) Entertainment devices (games)

y Testing, sensing, reporting 100111111100001000010100011001

3

7

Analog and Digital Systems

Binary System

y Many systems use a mix of analog and digital electronics to

y Digit: A symbol used to express a quantity.

take advantage of each technology. y A typical CD player accepts digital data from the CD drive and converts it to an analog signal for amplification.

y Digital: Related to digits or discrete quantities; having a set of

discrete values as opposed to continuous value. y Digital electronics involves circuits and systems in which there

are only two possible states represented by two digits.

CD drive

y The two-state number system is called binary system y Its two digits are 0 and 1. Each of the two digits is called a bit, which

is a contraction of the words binary digit. 10110011101 Digital data

Digital-to-analog converter

y Information in circuits are represented by voltage values.

Linear amplifier Analog reproduction of music audio signal

y Positive Logic System: 0 and 1 are represented by two different Speaker

voltage levels. y 1 is represented by the higher voltage level (HIGH) y 0 is represented by the lower voltage level (LOW)

Sound waves

4

8

Digital Abstraction

Timing Diagram

y Q: So, what does “digital” mean anyway?

y A timing diagram is a graph of digital waveforms showing the actual

time relationship of two or more waveforms and how each waveform changes in relation to the others.

y A: For now, “digital” means a binary system y Only 2 recognized values y Low or High y 0 or 1 y Negated or asserted y False or True y Off or On

y By looking at a timing diagram, you can determine y the states (HIGH or LOW) of all the waveforms at any specified point in

time and y the exact time that a waveform changes state relative to the other

waveforms. 9

13

Logic Level

Basic Logical Operation

y Information in circuits are represented by

y What can you do with 0 and 1?

y y

y

y 10

voltage values. The voltages used to represent a 1 and nd a 0 are called logic levels. In a practical digital circuit a HIGH can be any voltage between a specified minimum value and a specified maximum value. Likewise, a LOW can be any voltage between a specified minimum and a specified maximum. There can be no overlap between the accepted range of HIGH levels and the accepted range of LOW levels.

y Basic Building Blocks:

VH(max)

y The NOT operation HIGH

VH(min)

Unacceptable

The NOT operation changes one logic level to the opposite logic level.

VL(max)

LOW VL(min) 14

Digital Waveforms

Basic Logical Operation

y Digital waveforms consist of voltage levels that are changing

y The AND operation

back and forth between the HIGH and LOW levels or states. y These waveforms represent sequences of bits which contains binary information. y Each bit in a sequence occupies a defined time interval called a bit time.

Produce a HIGH output only when all the inputs are HIGH.

y The OR operation

Produce a HIGH output when one or more inputs are HIGH.

y A group of several bits can be used as a piece of binary

information, such as a number or a letter. 11

15

Clock Waveform

Summary: Truth Table

y In digital systems, all waveforms are synchronized with a clock. y The clock waveform itself does not carry information.

y The clock is a periodic waveform in which each interval between

X 0 0 1 1

pulses (the period) equals the time for one bit.

y Notice that change in level of waveform A occurs at the leading

edge of the clock waveform. 12

16

Y 0 1 0 1

NOT X 1 1 0 0

X AND Y 0 0 0 1

X OR Y 0 1 1 1

Binary Number System y The binary system with its two digits is a base-two system.

Digital Circuits

y The two binary digits (bits) are 1 and 0.

y The position of a 1 or 0 in a binary number indicates its weight or

ECS 371

value within the number. y The weight structure of a binary number is

Dr. Prapun Suksompong

Weight of the MSB for n-bit binary number

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Number Systems

2n1

Weight of the LSB for binary number

23 22 21 20

y The weights increase from right to left by a power of two for each bit. y The right-most bit is the LSB (least significant bit) in a binary

whole number and has a weight of 20 = 1. y The left-most bit is the MSB (most significant bit); its weight depends on the size of the binary number. 1

5

Previously on ECS 371

Binary Number System

y Digital vs. Analog quantity

y Example: Determine the weight of the 1 in the binary

number 10000.

y Advantages of digital system y Digitization: Conversion from analog to digital

representation y Sampling y Quantization

y Digital symtem = binary system

20 1

y Only 2 recognized values y Low or High

21 2

22 4

23 8

24 16

25 32

26 64

27 28 128 256

y 0 or 1 2

6

Decimal Number System

Binary-to-Decimal Conversion

y The decimal system with its ten digits is a base-ten system

y Add the column values of all of the bits that are 1 and

y You use decimal numbers every day.

discarding all of the bits that are 0. y Example: Convert the binary whole number 1101101 to decimal.

y Each of the ten digits (symbols), 0 through 9, represents a

certain quantity. y The position of each digit in a weighted number system is

assigned a weight based on the base or radix of the system. y The radix of decimal numbers is ten. y The weights for whole numbers are positive powers of ten that

y Example: What is the largest decimal number that can be

increase from right to left, beginning with 100 = 1.

represented in binary with seven bits? y The largest decimal number that can be represented in binary

with n bits is 2n-1.

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7

Decimal Number System

Decimal-to-Binary Conversion

y Example: Express the decimal number 47 as a sum of the

y Two methods

values of each digit.

1.

47 = (4 u 101) + (7 u 100) = 40 + 7

2.

y Example: What weight does the digit 7 have in each of the

y Sum-of-Weights Method: determine the set of binary

following numbers? (a) 1370

(b) 6725

weights whose sum is equal to the decimal number.

(c) 7051

y Example: Convert the following decimal numbers to binary:

y Example: Express each of the following decimal numbers as a

1.

sum of the products obtained by multiplying each digit by its appropriate weight

2.

(a) 51 = (5 u 10) + (1 u 1) (b) 137 = (1 u 100) + (3 u 10) + (7 u 1)

4

Sum-of-Weights Method Repeated Division-by-2 Method

3.

8

12 25 58 20

21

22

23

24

25

26

1

2

4

8

16

32

64

27

28

128 256

Decimal-to-Binary Conversion

y Repeated Division-by-2 Method:

y Example: Add the binary numbers 0111 and 1101 and show

y The remainders form the binary number.

y The first remainder to be produced is the LSB.

1 111 0111+ 7 + 1101 13 101 0 0 = 20

y Example: Convert the following decimal number to binary. (a) 12

(b) 45

9

13

Binary Counting

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A binary counting sequence for numbers from zero to fifteen is shown. Notice the pattern of zeros and ones in each column. Digital counters frequently have this same pattern of digits: Counter

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

Decoder

Representation of Negative Numbers

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

10

y Positive integers and the number zero can be represented as

unsigned numbers. y To represent negative integers, we need a notation for

negative values. y In ordinary arithmetic, a negative number is indicated by a

minus sign. y Computer must represent everything with 1’s and 0’s,

including the sign of a number. y As a consequence, it is customary to use the MSB to

represent the sign. y First, we will study some important operations that will be

useful for representing negative numbers. 14

1’s and 2’s Complement y Some important operations:

The rules for binary addition are re 0+0= 0 Sum = 0, carry = 0 0+1= 1 Sum = 1, carry = 0 1+0= 1 Sum = 1, carry = 0 1 + 1 = 10 Sum = 0, carry = 1 When an input carry = 1 due to a previous result, the rules are 1 + 0 + 0 = 01 Sum = 1, carry = 0 1 + 0 + 1 = 10 Sum = 0, carry = 1 1 + 1 + 0 = 10 Sum = 0, carry = 1 1 + 1 + 1 = 11 Sum = 1, carry = 1

2.

y

If a number D is complemented twice, the result is D.

y An alternative method of finding the 2's complement:

Change all bits to the left of the least significant 1. 1.

Start at the right with the LSB and write the bits as they are up to and including the first 1. Take the 1's complements of the remaining bits.

15

Truth Table

Example

y Truth table: A table showing the inputs and corresponding

The 1’s complement of 11001010 is 00110101 (1’s complement) To form the 2’s complement, add 1: +1 00110110 (2’s complement)

output(s) of a logic g circuit. Inputs Outputs A 0 0 1 1

B 0 1 0 1

Cout 0 0 0 1

6 0 1 1 0

Inputs A 0 0 0 0 1 1 1 1

12

If the addition produces a result that requires more than n digits, we throw away the extra digit(s).

y

2. 11

1's complement: Change all 1s to 0s and all 0s to 1s. 2's complement: Add 1 to the LSB of the 1's complement.

1.

B 0 0 1 1 0 0 1 1

1

1

0

0

1

0

1

0

0

0

1

1

0

1

0

1

1

Outputs Cin 0 1 0 1 0 1 0 1

Cout 0 0 0 1 0 1 1 1

6 0 1 1 0 1 0 0 1

Input bits Carry in

0

16

0

1

1

0

1

1

0

Implementation

Example The positive number 58 is written using 8-bits as 00111010 (true form). Sign bit Magnitude bits The negative number 58 is written as: 58 = 11000110 (2’s complement form) Magnitude bits Sign bit An easy way to read a signed number that uses this notation is to assign the sign bit a negative weight (128 for an 8-bit number). Then add the column weights for the 1’s.

11’s ’’ss Complement Co C om mpl mp p plleem eme men me ntt

2’s 22’ ’’ss Complement C Co om mpl mp p pllem em meen ntt

Weights: 128 64 32 16 8 4 2 1. 1 1 0 0 0 1 1 0 128 +64 +4 +2 = 58 21

Signed Binary Number

2’s Complement (con’t)

y Fix the number of bits.

y The number of different combinations of n bits is 2n

y A signed binary number consists of both sign and magnitude

y For n bit 2’s complement signed g numbers, the range

information.

is

y The sign indicates whether a number is positive or negative y In a signed binary number, the left-most bit (MSB) is the sign bit. y 0 indicates a positive number, and 1 indicates a negative number y The magnitude is the value of the number.

0

001

1

010

2

one:

011

3

y If m > n, append m-n copies of the sign bit. y This is called sign extension. y If m < n, discard n-m leftmost bits y The result is valid only if all of the discarded bits are the same as the sign bit of the result.

100

-4

101

-3

110

-2

111

-1

y This number does not have a positive counterpart.

y To convert n-bit 2’s complement number into m-bit

can be represented in binary: sign-magnitude, l's complement, and 2's complement.

y Of these, the 2's complement is the most important

1’s Complement

2’s Complement

22

Sign-Magnitude

18

000

0

0

0

y In sign-magnitude representation: 10001001

001

1

1

1

y In 1’s complement representation: 11110110

010

2

2

2

y In 2’s complement representation: 11110111

011

3

3

3

100

-0 -3 -4

101

-1 -2 -3

110

-2 -1 -2

111

-3 -0 -1

2’s Complement

19

1’s Complement

(1) Sign-Magnitude Form y The magnitude bits are in true (uncomplemented) binary for both positive and negative numbers. y Negate a number by changing its sign. (2) 1’s Complement Form y A negative number is the 1's complement of the corresponding positive number. There are two possible representations of zero, “+0” and “-0”, but both have the same value.

Sign-Magnitude

Signed Binary Number

000

0

0

0

001

1

1

1

010

2

2

2

011

3

3

3

100

-0 -3 -4

101

-1 -2 -3

110

-2 -1 -2

111

-3 -0 -1

Signed Binary Number (2)

20

000

y Has one extra negative number b

y There are three forms in which signed integer (whole) numbers 1. 2. 3.

 2n 1 to  2n 1  1

(3) 2’s Complement Form y A negative number is the 2's complement of the corresponding positive number. y Has only one representation of zero. y Zero is considered positive because its sign bit is 0. y The weight of the sign bit is given a negative value. y Decimal values are determined by summing the weights in all bit positions where there are 1s and ignoring those positions where there are zeros.

2’s Complement

17

Example y There is only one way to represent +9 using eight bits:

00001001 y We have three different ways to represent -9 using eight bits:

23

Caution y Both signed and unsigned binary numbers consist of string of

bits when represented in a computer. y The user determines whether the number is signed or unsigned.

24

Review

AND Gate

y Convert the following decimal numbers to binary:

y Logic Expressions: The AND operation is

(a) +29

(b) +85

usually shown with a dot between the variables but it may be implied (no dot). y X = A .B or X = AB.

y Express the following decimal numbers in binary as an 8-bit

sign-magnitude number: (a) +29

(b) -85

Inputs

Output

A

B

X

0 0 1 1

0 1 0 1

0 0 0 1

y Express the following decimal numbers as an 8-bit number in

the 1’s complement form: (a) +29

(b) -85

y Express the following decimal numbers as an 8-bit number in

the 2’s complement form: (a) +29

(b) -85

25

4

AND Gate (Con’t)

Digital Circuits ECS 371

Dr. Prapun Suksompong [email protected]

Logic Gates

1

5

Logic Gates

OR Gate y OR gate produces a HIGH output when one or more inputs

are HIGH. y Expression: Use plus sign (+) between the variables. y X = A + B.

2

Output

A B

X

0 0 1 1

0 1 1 1

0 1 0 1

6

NOT Gate

OR Gate (con’t)

y The inverter (NOT circuit) performs the operation called

inversion or complementation. y Complement :The inverse or opposite of a number. y LOW is the complement of HIGH y 0 is the complement of 1.

y The negation indicator is a "bubble" (o) that indicates

inversion or complementation y Later, we will “play” with this bubble. 3

Inputs

7

Application

XOR

Inputs A

B

X

y A simplified intrusion detection tion

y Exclusive-OR (XOR)

system using an OR gate. y The sensors are magnetic switches witches that produce a HIGH outputt put when when open and a LOW output closed. y As long as the windows and the door are secured, the switches are closed and all three of the OR gate inputs are LOW. y When one of the windows or the door is opened, a HIGH is produced on that input to the OR gate and the gate output goes HIGH.

gate produces a HIGH output only when its two inputs are at opposite levels. y XOR and XNOR gates are formed by a combination of other gates already discussed.

0 0 1 1

0 1 0 1

0 1 1 0

y Because of their fundamental

importance in many applications, these gates are often treated as basic logic elements with their own unique symbols.

It then activates and latches an alarm circuit to warn of the intrusion.

8

12

NAND Gate y NAND gate produces a LOW output

only when all the inputs are HIGH.

Inputs

Output

A

B

X

0 0 1 1

0 1 0 1

1 1 1 0

XOR and XNOR y Exclusive-NOR gate: A logic gate that produces a LOW

only when the two inputs are at opposite levels. Inputs

9

Output

A

B

X

0 0 1 1

0 1 0 1

1 0 0 1

13

NAND Gate (Con’t)

Logic Gates & Application

y The NAND gate is a popular logic element because it can be

used as a universal gate. y NAND gates can be used in combination to perform the AND,

OR, and inverter operations. y In fact, all other basic gates can be constructed from NAND

gates. y Ex. Inverter y We will revisit this property.

y The NAND operation is shown with a dot between the

Inputs Outputs

variables and an overbar covering them. yX=A

.B

A

(Alternatively, X = AB.)

B 10

6

A 0 0 1 1

6 Cout

B 0 1 0 1

Cout 0 0 0 1

6 0 1 1 0

6 A

Cout

B

14

NOR Gate y NOR gate’s output is LOW when one or more of the inputs

are HIGH. Inputs

1. The truth table for a 2-input AND gate is Inputs A

Output

A

B

X

0 0 1 1

0 1 0 1

1 0 0 0

y Can also be used as a universal gate.

11

Output

a.

0 0 1 1

B

0 1 0 1

Inputs

c.

Output

Inputs

X

0 1 1 0

b.

Output

A

B

X

0 0 1 1

0 1 0 1

0 0 0 1

B

X

0 0 1 1

0 1 0 1

1 0 0 0

Inputs

d.

Output

A

Output

A

B

X

0 0 1 1

0 1 0 1

0 1 1 1

2. The truth table for a 2-input NOR gate is Inputs A a.

0 0 1 1

B

Inputs

X

0 1 0 1

Inputs

c.

Output

0 1 1 0

b.

Output

A

B

X

0 0 1 1

0 1 0 1

0 0 0 1

A

B

X

0 0 1 1

0 1 0 1

1 0 0 0

Inputs

d.

6. A 2-input gate produces a HIGH output only when the inputs agree. This type of gate is a(n)

Output

a. OR gate b. AND gate

c. NOR gate d. XNOR gate

Output

A

B

X

0 0 1 1

0 1 0 1

0 1 1 1

Fixed Function Logic y Typical dual in-line (DIP) and small-outline (SOIC) packages

3. The truth table for a 2-input XOR gate is Inputs A a.

0 0 1 1

B

Inputs

X

0 1 0 1

Inputs

c.

Output

0 1 1 0

b.

Output

A

B

X

0 0 1 1

0 1 0 1

1 0 0 0

Inputs

Output

A

B

X

A

B

X

0 0 1 1

0 1 0 1

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

d.

showing pin numbers and basic dimensions.

Output

21

Pin configuration diagrams 4. A logic gate that produces a HIGH output only when all of its inputs are HIGH is a(n) a. OR gate b. AND gate c. NOR gate

d. NAND gate

Misc. y Fan-out: The number of equivalent gate inputs of the same

5. A 2-input gate produces the output shown. (X represents the output.) This is a(n)

family series that a logic gate can drive. y Unit load: A measure of fan-out. One gate input represents one unit load to the output of a gate within the same IC family. y Propagation delay time: The time interval between the occurrence of an input transition and the occurrence of the corresponding output transition in a logic circuit.

a. OR gate b. AND gate

c. NOR gate d. NAND gate

A B X 23

C.E. Shannon (Con’t) y “The fundamental problem of communication is that of

Digital Circuits

reproducing at one point either exactly or approximately a message selected at another point.”

ECS 371 Dr. Prapun Suksompong [email protected]

Boolean Algebra and Logic Simplification

1

5

Boolean Algebra

Exercise

y The mathematics of logic circuits.

y The algebra of two values.

The associative law for addition is normally written as

y Usually taken to be 0 and 1.

a. A + B = B + A

y Developed in 1854 by George

b. (A + B) + C = A + (B + C)

Boole in his book An Investigation of the Laws of Thought. y Provide a concise way to express the operation of a logic circuit formed by a combination of logic gates.

c. AB = BA d. A + AB = A

2

C. E. Shannon (1916-2001) 001)

Exercise

y 1938 MIT master's thesis: A Symbolic

Analysis of Relay and Switching Circuits y Insight: The binary nature of Boolean

y y y

y

logic was analogous to the ones and zeros used by digital circuits. The thesis became the foundation of practical digital circuit design. The first known use of the term bit to refer to a “binary digit.” Possibly the most important, and also thee most famous, master's thesis of the century. It was simple, elegant, and important.

The Boolean equation AB + AC = A(B+ C) illustrates a. the distributive law b. the commutative law

c. the associative law d. DeMorgan’s theorem

3

C. E. Shannon (Con’t) y 1948: A Mathematical Theory

of Communication y Create the architecture and concepts governing digital communication. y Invent Information Theory: Simultaneously founded the subject, introduced all of the major concepts, and stated and proved all the fundamental theorems. 4

The science of information theory tackles the following questions [Berger] 1. What is information, i.e., how do we measure it quantitatively? 2. What factors limit the reliability with which information generated at one point can be reproduced at another, and what are the resulting limits? 3. How should communication systems be designed in order to achieve or at least to approach these limits?

Exercise The Boolean expression A . 1 is equal to a. A b. B

c. 0 d. 1

Exercise

Proving Identities/Rules/Laws Example: Check that

The Boolean expression A + 1 is equal to

AB  A B  C

a. A

Method 1: Use Algebraic Manipulation

b. B

A B  C

Method 2: Use Truth Table A 0 0 0 0 1 1 1 1

c. 0 d. 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

13

Exercise

Comparison Algebraic Manipulation

Draw the logic circuits represented by X

X

A B

X

A B

X

A B

X

A  B C  B

A B

10

14

Truth Table

•Quick (usually) •Simple

•Need to remember many •Tedious/Boring/Ti rules/laws. me-wasting •Need to know when to apply them.

•Straightforward

For ECS371, make sure that you know both method. Later, we will use another method (K-map).

Remark

Principle of Duality

y Precedence:

Any theorem or identity remains true if 0 l 1 l Example:

A  B  C is the same as A  B  C

X 1 1 X 0 0

A  B  C is NOT the same as A  B  C A  B is NOT the same as A  B

XX

1

X X

0

Caution: X  X  Y X y Parenthesize an expression fully before taking its dual!

X Y  X  Z

X Y  X  Z 11

X Y Z

15

Three Useful Rules

Duality Principle in Action

These rules do not exist in elementary algebra

A  B A  C A  AB

A

Examples:

A  BC

A  AB

A B

Examples:

XY  XYZ

XY

W XY  WY

WY

A  AB XY  XYZ

A A B C 12

X  Y  Z

A B XY  Z A B C 16

DeMorgan’s Theorem

Example

Part 1:

Show that A1  A2 

 An

A1  A2 

A  B A  C A  D

 An

Part 2: A1  A2 

 An

A1  A2 

X NAND Y

X Y

X  Y (Negative-OR)

A  BCD

 An

Example: X NOR Y

X Y

X  Y (Negative-AND)

17

21

Play with the bubbles

Example

Recall that each bubble means a “NOT” operation. 1. You can create a pair of bubbles out of nothing and move them freely on the wire. 2. DeMorgan’sThorem: When you move bubble through the AND gate or the OR gate, the gate changes. 3. If you want to leave an isolated bubble in your final design/answer, write an actual inverter instead of a bubble.

Using Boolean algebra, simplify

18

B  BC B  BC B  D

22

Example

Example

Using Boolean algebra, simplify

Using Boolean algebra, simplify

BD  B D  E  D D  F

19

ABCD  AB CD  AB CD

23

Example

Example

Using Boolean algebra, simplify

Using Boolean algebra, simplify

ABC AB  C BC  AC

ABC  ( A  B  C )  ABCD

20

24

A

Example

B

Example

Using Boolean algebra, simplify

X

A  AB  ABC

X

C

ABC  ABC  ABC  ABC  ABC

ABC  ABC  ABC  ABC  ABC

ABC  ABC  ABC  ABC  ABC

ABC  B AC  AC  AC  AC

Direct construction of a circuit from this equation will be complicated.

Simplification

ABC  B AC  B Construction of an equivalent circuit from this equation is simpler. 25

X

AC  B

29

Our Goals

Example: Designing Logic Circuit

y Ultimate goals:

1. Suppose we want to build a circuit that perform a one-bit addition

Analyze digital circuits. 2. Design digital circuits to do something useful. 1.

A

6

6

2. We can summarize its task by a truth table.

1. Analyze digital circuit:

B

Cout Inputs Outputs

y Given a digital circuit, find out what it does.

A 0 0 1 1

y One way to achieve this goal is to look at the truth table.

B 0 1 0 1

Cout 0 0 0 1

6 0 1 1 0

3. Can we turn this truth table into a simple circuit? 6 A 26

30

Example: Analyzing Logic Circuit

B

Cout

Example: Designing Logic Circuit (2) 1. Suppose we want to build a circuit that perform a one-bit addition with input carry

1. Suppose we are given a digital circuit. 2. Analyze it via the truth table

X A 0 0 1 1

B 0 1 0 1

A B  A B

X 0 1 1 0

It may be useful to find a Boolean expression first.

22. We can summarize its task by a truth table. Inputs

3. Can we turn this truth table into Boolean expression?

How? 3. Interpretation: This is a circuit that checks whether A ≠ B. Output X = 1 if A and B are not the same. Output X = 0 if A is the same as B. 27

We can apply the same technique to more complicated circuits.

Sometimes, we may be able to simplify the circuit by simplifying its Boolean expression.

B 0 0 1 1 0 0 1 1

Outputs Cin 0 1 0 1 0 1 0 1

Cout 0 0 0 1 0 1 1 1

6 0 1 1 0 1 0 0 1

31

Our Goals

Truth Table

y Ultimate goals:

y How can we turn a truth table into Boolean expression?

Boolean Expression?

y Let’s first study the relationship between truth table and

Analyze digital circuits. 2. Design digital circuits to do something useful. 1.

Boolean expression. y It is easier to convert a Boolean expression into a truth table.

1. Analyze digital circuit: 2. Design digital circuits:

y There are some forms of Boolean expressions that are easily

y Given a task, build a SIMPLE digital circuit that perform the

converted into their corresponding truth tables.

y Sum-of-products form y Product-of-sums form

y Directly determine a Boolean expression corresponding to the task or

start with a truth table and then turn it into a Boolean expression. y Simplify the expression. y Construct a circuit from the simplified expression. 28

A 0 0 0 0 1 1 1 1

32

Product Term A single literal or a product of two or more literals. Example: A  B  C

Conclusion: 1.

Q : When does A  B  C 1?

It is easy to find the case when a product term = 1. A  B  C 1 iff A, B, C

2.

AC A

1,0,1

It is easy to find the case when a sum term = 0. 0 iff A, B, C

A B C

A B C  D

0,1,0

A B C

Caution: A  B  C is not a product term.

33

37

Product Term A single literal or a product of two or more literals. Example: A  B  C AC A A B C  D A B C

Caution: A  B  C is not a product term.

Example Find the value of X for all possible values of the variables when

Q : When does A  B  C 1? A : IFF A, B, C 1,0,1

X

So, it is very easy to construct a truth table for X A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

A 0 0 0 0 1 1 1 1

A B C X 0 0 0 0 0 1 0 0

34

C 0 1 0 1 0 1 0 1

38

Sum Term A single literal or a sum of two or more literals. Example:

Example Find the value of X for all possible values of the variables when

Q : When does A  B  C 1?

X

A B C AC A

A 0 0 0 0 1 1 1 1

A BC  D A B C

Caution: A  B  C is not a sum term.

35

B 0 0 1 1 0 0 1 1

AB  ABC

C 0 1 0 1 0 1 0 1

39

Sum Term A single literal or a sum of two or more literals. Example: A B C AC A

A BC  D

Example

Caution: A  B  C is not a sum term.

Find the value of X for all possible values of the variables when

Q : When does A  B  C 1?

X

It might be easier to ask: Q : When does A  B  C 0? A : IFF A, B, C 0,1,0

A 0 0 0 0 1 1 1 1

Q : When does A  B  C 1? A : IFF A, B, C z 0,1,0

A B C It is easy to construct a truth table for X 36

B 0 0 1 1 0 0 1 1

ABC  ABC  ABC  ABC  ABC

A B C

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

X 1 1 0 1 1 1 1 1

40

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

AB  C  ABC

Example

Domain

Find the value of X for all possible values of the variables.

Domain of an expression:

X A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

B  AC  ABC

X

C 0 1 0 1 0 1 0 1

A 0 0 0 0 1 1 1 1

Set of variables contained in the expression.

B  C  ABC  ABC B 0 0 1 1 0 0 1 1

Example: Domain of AB  ABC is ^ A, B, C`.

C 0 1 0 1 0 1 0 1

So, a standard SOP expression is one in which all the variables in the domain appear in each product term in the expression. Alternative definition for a standard SOP expression.

41

45

Sum-of-Product (SOP) Form

Row Number of the Truth Table

A product term or a sum of product terms Example: AB  ABC

Example: Develop a truth table for X Observe that when a product term does not contain all variables, it corresponds to multiple 1s in the output column of the truth table. This is because the missing variable does not affect the product term and hence can be 0 or 1.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

AB  ABC

X 0 0 0 0 1 1 0 1

Observe that when a product term contains all the variables, it corresponds to a unique 1 in the output column of the truth table.

42

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

X

Think of these as one unsigned binary number. The corresponding decimal value is the row #.

46

Standard SOP (Canonical Sum)

Minterm/Row Number & Truth Table

Each product term contains all variables. Example:

Row #

A

B

C

Minterm

0

0

0

0

1

0

0

1

2

0

1

0

Example : ABC  ABC  ABC contains 3 minterms

3

0

1

1

y A minterm is equal to 1 for only one combination of variable

4

1

0

0

5

1

0

1

6 7

1 1

1 1

0 1

A  B C A  B C A  B C A  B C A  B C A  B C A  B C A  B C

Nonstandard product term

AB  ABC is not a standard SOP expression. ABC  ABC  ABC is a standard SOP expression.

Observe these!

Minterm: A product term in a standard SOP expression. values. y A minterm corresponds to a unique 1 in the output column of the truth table. y A minterm corresponds to a unique row of the truth table. y A canonical sum is a sum of minterms.

43

Summary: Each row of the truth table corresponds to 1. A combination of input (A,B,C). 2. A row #. 3. A minterm.

47

Review

Binary Representation (of minterm and of any Boolean expression)

Nonstandard AB  C  ABC

X

Example: Consider a canonical sum:

Expression in SOP (Sum-of-Products) Form

ABCD  ABC D

Standard (Canonical Sum)

= 1 IFF (A,B,C,D) = (0,1,1,0)

= 1 IFF (A,B,C,D) = (0,1,0,1)

All variables appear in each product term.

ABC  ABC  ABC

Row # 6

Row # 5

ABCD  ABC D

Note: Each minterm corresponds to one combination of input variables. 44

A 0 0 0 0 1 1 1 1

Row # 0 1 2 3 4 5 6 7

AB  C ABC  CDE

48

¦

A, B ,C , D

5,6

ABCD  ABC D A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

This is called a minterm list It means “the sum of minterms 5,6 with variable A, B, C, D”

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

X 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

Canonical Sum and Minterm List

Karnaugh Map

y Example: Convert ABC  A  B into canonical sum.

AB

X 1 X  Y  Y

0

AB

1

0

2

3

6

B

7

11 4

A

5

10

53

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

B

10

Row #

49

10

0

11

A

A B C

0 1 2 3 4 5 6 7

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

11

01

01

canonical sum (which is equivalent to a minterm list).

01

00

X Y  X Y

y Any logic function/expression can be expressed as a

00

1

00

y Example: Convert ABC  A  B into a minterm list.

C

CD

D

0 1 0 1 0 1 0 1

The small number inside each cell is the corresponding row number in the truth table, assuming that the truth table inputs are labeled alphabetically from left to right (e.g. A, B, C) and the rows are numbered in binary counting order.

Row #

Hint : X

C

C

A

B

C

D

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

(A Revisit!)

Truth Table

Boolean Expression

Karnaugh Map: Basic Layout y Similar to a truth table.

Add all the minterms corresponding to a 1 in the output column of the truth table. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

X 1 0 0 1 1 0 1 1

y Present all of the possible values of input variables and the resulting

output for each value. y Instead of being organized into columns and rows, it is an array

of cells. y The number of cells in a K-map, as well as the number of rows in

X

a truth table, is equal to the total number of possible input variable combinations (which is the same as the total number of minterms). y The cells are arranged in a way so that simplification of a given expression is simply a matter of properly grouping the cells. y Used for simplifying Boolean expressions to their “minimum form”.

A B C  A B C  A B C  A B C  A B C

Alternatively, we may write

X

¦

A, B ,C

0,3,4,6,7

AB

C

C

AB

C

CD

B

B A

A

50

54 D

Minimization (A Revisit!)

Example: Truth Table v.s. K-map X

AB  ABC

Input Columns

A 0 0 0 0 1 1 1 1

“The process that results in an expression containing the fewest possible terms with the fewest possible variables.” We have done some minimization using Boolean algebra.

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

AB

X 0 0 0 0 1 1 0 1

C

C 0

0

0

0

0

1

1

1

B A

Output Column

The expression can then be implemented with fewer logic gates. 51

55

It can be difficult (especially for large K-map) to remember which cell in K-map corresponds to a particular row in the truth table. We also want to get the K-map directly from Boolean expression without writing down truth table first.

The 2-variable Karnaugh Map (2x2 K-Map) We will study K-maps for logic

Recall: Old Way

functions of 2, 3, and 4 variables

y We have studied Boolean algebra.

Domain

y We can use algebraic manipulation to simplify Boolean

^ A, B`

Each row of the truth table corresponds to one minterm.

B

Input Columns

y Need to remember many rules/laws.

A 0 0 1 1

y Need to know when to apply them.

B X 0 1 0 1

Minterm

A B A B A B A B

Output Column

52

Each cell of the K-map corresponds to one minterm.

56

A

Use these to find the corresponding minterm for each cell.

The 3-variable Karnaugh Map

Mapping Canonical Sum

^ A, B, C `

Domain

For a canonical sum (SOP expression in standard form): y A 1 is placed on the K-map for each minterm in the expression. y Each 1 is placed in a cell corresponding to the minterm that produces it. y When the canonical sum is completely mapped, there will be a number of 1s on the K-map equal to the number of minterms in the canonical sum. y The cells that do not have a 1 are the cells for which the expression is 0.

57

61

The 4-variable Karnaugh Map Domain

Ex: Mapping (Canonical Sum)

^ A, B, C , D`

Map the following expression on an appropriate Karnaugh map ABC  ABC  ABC  ABC AB

 ABCD  ABC D

C

C

ABCD  ABC D  ABCD  ABCD  ABC D

AB

C

CD

B

1

1

0

1

0

0

0

1

1

1

0

0

0

0

1

B

A

58

0

A

D

62

K-Map

Ex: Mapping (Canonical Sum)

Convention: We use the following maps to define our K-maps AB

C

C AB

Map the following expression on an appropriate K-map

C

CD

ABC  ABC  ABC  ABC AB B

B A

A

 ABCD  ABC D

C

C 0

1

1

0

1

1

0

0

ABCD  ABC D  ABCD  ABCD  ABC D

AB

B

1

1

0

1

0

0

0

1

1

1

0

0

0

0

1

A

There are many ways to define the K-map. Once you are familiar with one convention, you may try to work with different convention. 59

0

B

A

D

C

CD

D

63

Alternative K-Maps

Caution When you see ABC or ABC on quiz/HW/exam, please always double-check whether the bars on the top are disconnected.

This convention is used in the textbook by Wakerly.

This is the K-map for X which is equivalent to

This is the K-map for X

ABC which is the

same as X AB

X

A B C

A B C

C

C

AB

1

0

0

0

C

C 1

1

1

1

1

0

1

1

B

B 0

0

0

A

A

We will NOT follow this convention in ECS371. 60

0

64

ABC

AB

C

CD

Grouping the 1s

0

0

0

1

0

0

0

1

1

1

0

0

1

1

0

0

B A

Why do we arrange the cells in this “strange” ordering? AB

C

C 0 0

AB

1

CD 00

1

01

D

11

10

0

1

3

2

2

3

4

5

7

6

12

13

15

14

8

9

11

10

ABC D  ABC D

00

00

AC D B  B AC D

01

01 6

B

7

11

A

C

B

Summation of these four

11 4

A

5

10

minterms gives AC

10

D

65

The K-map is used to “visualize” the combining theorem. AB  AB B

69

Rules: Grouping the 1s

y The cells in a K-map are arranged so

You can group 1s on the K-map according to the following rules Each time that we make a group larger, it will cover twice as many cells. y A group must “rectangular” and contain 2k cells. y Each cell in a group must be adjacent to one or more cells in that same group,

that there is only a single-variable change between adjacent cells. y Definition: Cells that differ by only one variable are adjacent. y Physically, each cell is adjacent to the

y but all cells in the group do not have to be adjacent to each

cells that are immediately next to it on any of its four sides.

other. y Always include the largest possible number of 1s in a group.

y Note that a cell is not adjacent to the

y Each of this group is called “prime implicant”

cells that diagonally touch any of its comers.

AB

C

CD 0

0

0

1

0

0

0

1

1

1

0

0

1

1

0

0

B A

66

70 D

Example:

Find all prime implicants in each K-map.

The cells in the top row are adjacent to the corresponding cells in the bottom row.

ABC ABC

AB

ABC ABC

ABC

ABC

ABC

ABC

C

CD

AB

1

1

1

1

1

C

CD

1

1

1

1

B

1

1

A

1

1

D

71

Example:

CD

CD

CD

AB AB AB AB

68

1

A 1

D 67

1

B

Why is this adjacency concept useful?

Find all prime implicants in each K-map.

The cells in the top row are adjacent to the corresponding cells in the bottom row and the cells in the outer left column are adjacent to the corresponding cells in the outer right column.

AB

C

CD

AB

1

1

1

1

1

1

1 B

1

1

A

This is called "wrap-around" adjacency because you can think of the map as wrapping around from top to bottom to form a cylinder or from left to right to form a cylinder.

C

CD

D 72

B

1

1

1

A 1

1

1

1

D

Prime Implicant to Product Term

Mapping (SOP)

y Each prime implicant is a product term

Map the following expression on a Karnaugh map

y Composed of all variables that occur in only one form (either

A  AB  ABC

uncomplemented or complemented) within the group y Variables that occur both uncomplemented and complemented within the group are eliminated.

AB

BC  AB  ABC  ABCD

C

C

AB

C

CD

y These are called contradictory variables. B

B

AC D

A

A

AC D 73

77

Prime Implicant to Product Term

Minimal Sum

Turn out that we can read the product term(s) off the K-map directly For each variable, say X, in

y Definition: A minimal sum is a SOP expression such that

AB

C

CD 0

0

0

1

0

0

0

1

1

1

0

0

1

1

0

0

no equivalent SOP expression has fewer product terms, and any equivalent SOP expression with the same number of product terms has at least as many literals. y Prime-Implicant Theorem: A minimum sum is a sum of prime implicants

the domain, determine whether the group is inside the region AC D associated with X. 1)If it is inside, write X in the product term. 2)If it is outside, write X in the product term. AC 3)If it is both inside & outside, skip X in the product term.

B A

D 74

78

Product Term to K-Map AB

K-Map to Minimal Sum y Group the cells that have 1s according to the rules on earlier

C

CD

slide. This creates many prime implicants.

0

0

0

1

0

0

0

1

AC D

Put 1s in the “intersection” area of the regions

y Each prime implicant creates one product term. y Each 1 on the map must be included in at least one prime

implicant.

B 1

1

0

0

1

1

0

0

y The sum of all the prime implicants of a logic function is called

A

the complete sum.

AC

y It is a legitimate way to realize a logic function.

Overlapping is OK

y It’s not always minimal.

y “Minimize the number of prime implicants.” licants

D

We first find ALL prime implicants. Then, we eliminate as many of them as possible.

y Add up all the “surviving” product terms 75

79

Mapping (SOP)

Example:

Map the following expression on a Karnaugh map

Find the minimal sum from each K-map.

A  AB  ABC AB

C

BC  AB  ABC  ABCD

C AB

AB

C

CD

C

CD

AB

1

1

1

1

1

C

CD

1

1 B

B A

1

B

1

A

D D 76

80

B

1

1

1

A 1

A

1

1

1

D

Example:

Example

Here are all prime implicants. AB

C

CD

AB

1

1

1

1

1

C

CD

1

1

1

B 1

1

B

1

1

A

1

A 1

1

1

D

D

81

85

Example:

Solution

We need only these… AB

C

CD

AB

1

1

1

1

1

C

CD

1

1 B

1

1

B

1

A

1

1

1

A 1

D

1

1

82

D  BC  ABC

AC  AB  ABD

D 86

Example

Example Use a K-map to minimize the following expression X

83

ABC  ABC  ABC  ABC  ABC

87

Solution olution

Solution Use a K-map to minimize the following expression X

ABC  ABC  ABC  ABC  ABC

X

ABC  AB  BC 84

B  AC  AC 88

B  AC

Non-uniqueness

New Perspective: 0

Use a K-map to minimize the following expression AB  AB  ABC AB

C

y So far, all of our techniques focus on the 1s in the truth

1

1

tables/K-maps. y We can look at the 0s as well.

0

1

C

Solution 1:AB  AB  AC B

1

1

0

0

Solution 2:AB  AB  BC

A

89

Caution: From this perspective, you are in a different world. In fact, it is a dual world. Techniques used here will be the dual of what we used before. 93

“Don’t Care” Input Combinations

Canonical Product

y Sometimes the output doesn’t matter for certain input

y Product-of-Sums (POS) Form

Example: A  B  A  B  C

combinations. y For example, the combinations are not allowed in the first

y Standard POS Form (Canonical Product)

place.

Example: A  B  C  A  B  C  A  B  C

y These combinations are called “don’t care”.

y Convert expression in POS form into canonical product:

y The “don’t care” term can be used to advantage on K-map. y For each “don’t care” term, place an X in the corresponding

Hint:

cell. y When grouping the 1s,

X 0

X

X  Y Y

y the Xs can be treated as 1s to make a larger grouping y or as 0s if they cannot be used to advantage. 90

X Y  X Y 94

Example

Truth Table for Canonical Product Find the value of X for all possible values of the variables when X

A  B  C  A  B  C  A  B  C

Old way: Convert to SOP form X

A 0 0 0 0 1 1 1 1

A  B  C  A  B  C  A  B  C A  B  A  B  A  B  C A  B  A  B  B  C A  B  A  C A  B  C

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

X 1 1 0 1 0 1 0 1

A B

C

Then, construct the truth table. 91

95

We can use the property of sum terms to construct the truth table directly.

Alternative Methods

Maxterm

y A sumterm in a canonical product is called a maxterm.

y Not applicable for more than five variables y Practical only for up to four variables y Difficult to automated in a computer program

y A maxterm is equal to 0 for only one combination of variable

values.

y There are other ways to minimize Boolean functions.

A B C

y More practical for more than four variables y Easily implemented with a computer 1. Quine-McClusky method y Inefficient in terms of processing time and memory usage 2. Espresso Algorithm y de facto standard

A B C

0 iff A, B, C

0,1,0 0 iff A, B, C 0,1,1 0 iff A, B, C 0,0,0

y We say that the maxterm A  B  C has a binary value of 010

(decimal 2) y Maxterm list: A  B  A  B  C because

92

A B C

96



A, B ,C

0, 2,3

A  B  A  B  C A  B  C  A  B  C  A  B  C

Truth Table for Canonical Product

Conversion

Find the value of X for all possible values of the variables when

Row # A

A  B  C  A  B  C  A  B  C

X New way:

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

X 1 1 0 1 0 1 0 1

This tells that the output column of the truth table is 1 on row # 0, 1, 2, 3.

A B C

B

C

Minterm

Maxterm

0

0

0

0

A  B C

1

0

0

1

2

0

1

0

3

0

1

1

4

1

0

0

5

1

0

1

6

1

1

0

7

1

1

1

A  B C A  B C A  B C A  B C A  B C A  B C A  B C A  B C

A  B C A  B C A  B C A  B C A  B C A  B C A  B C

This tells that the output column of the truth table is 0 on row # 4, 5, 6, 7.

A B C A B C

97

101

Example

K-Map POS Minimization

Find the value of X for all possible values of the variables when

y Goal: Find the “Minimal Product”

X A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A  B  A  B  C  A  B  C

y Appendix B in the textbook. y For a POS expression in standard form, a 0 is placed on the

C 0 1 0 1 0 1 0 1

K-map for each sumterm in the expression. y The cells that do not have a 0 are the cells for which the

expression is 1. y Group 0s to produce instead of grouping 1s.

98

102

Example Find the value of X for all possible values of the variables.

B A  C A  B  C

X A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

X

Digital Circuits

B C A  B  C A  B  C A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

ECS 371

C 0 1 0 1 0 1 0 1

Dr. Prapun Suksompong [email protected]

Combinational Logic Analysis

99

1

Minterm/Maxterm & Truth Table

100

Row #

A

B

C

Minterm

Maxterm

0

0

0

0

A BC

1

0

0

1

2

0

1

0

3

0

1

1

4

1

0

0

5

1

0

1

6

1

1

0

7

1

1

1

A B C A B C A B C A B C A B C A B C A B C A B C “1”

“0”

A B C A B C A B C A B C A B C A B C A B C

Combinational Logic y We studied the theoretical principles used in

In the same way that each minterm corresponds to a unique row of the truth table,

combinational logic design. y We will build on that foundation and describe many of the devices, structures, and methods used by engineers to solve practical digital design problems. y A complex circuit or system is conceived as a collection of smaller subsystems, each of which has a much simpler description.

each maxterm corresponds to a unique row of the truth table (in a dual way).

2

SOP Implementation: AND-OR Circuit

Remark

In Sum-of-Products (SOP) form, basic combinational circuits can be directly implemented with AND-OR combinations: first forming the AND terms; then the terms are ORed together.

1.

Product terms

A

B C

AB CD

AB + CD + . . . + JK

D J K

Sum-of-products JK

Product term

This is called the AND-OR configuration.

3

From any logic expression, you can construct a truth table. 2. From the truth table you can get a canonical sum or a minterm list. (This can be simplified to a minimal sum. In any case, you get a SOP expression) 3. Any SOP expression can be implemented using AND gates, OR gates, and inverters.

7

Example

AND-OR-Invert (AOI) circuit

Write the output expression of the following circuit as it appears in the figure and then change it to an equivalent ANDOR configuration.

When the output of a SOP form is inverted, the circuit is called an AND-OR-Invert circuit. The AOI configuration lends itself to product-of-sums (POS) implementation. A B C

Solution:

X

A  B  C  D A  B C  A  B  D

ABC X = ABC + DE

D

SOP

E

DE

X = ABC + DE

AOI

X = (ABC)(DE) DeMorgan X = (A + B + C)(D + E) POS

AC  BC  AD  BD 4

8

Example

Universal gate

Write the output expression of the following circuit as it appears in the figure and then change it to an equivalent ANDOR configuration.

y The term universal refers to a property of a gate that

5

permits any logic function to be implemented by that gate or by a combination of gates of that kind. y Example: NAND gates, NOR gates

9

Solution X

NAND Gate as a Universal Gate NAND gates are sometimes called universal gates because they can be used to produce the other basic Boolean functions.

A  B  B C  D A  B  B C  D

A

A  B  B C  D

A B

A

Inverter

A B  D

AB

AND gate

A

A A+B

A+B B

B

OR gate

6

10

NOR gate

Example Implement the following logic circuit using only NAND gates:

Digital Circuits ECS 371

Dr. Prapun Suksompong

C

[email protected]

C

Solution: Negative-OR { NAND

MSI

C

11

1

Example

Digital System Concept

Implement the following logic circuit using only NAND gates:

Negative-OR { NAND

Solution:

A digital system is an arrangement of the individual logic functions connected to perform a specified operation or produce a defined output.

It is easy to turn AND-OR configuration into a NANDgate-only circuit

12

2

NOR Gate as a Universal Gate

Combinational Building Blocks

NOR gates are also universal gates and can form all of the basic gates.

y There are several straightforward structures that turn up

quite regularly as building blocks in larger systems. y Encoder

A

A B

A

Inverter

y Decoders

A+ B

y Comparators

OR gate

y Multiplexers

A

A

AB

AB B

B

AND gate

Where can we find these building blocks?

NAND gate

13

3

Example

Fixed-function IC

Implement the following logic circuit using only NOR gates:

y An integrated circuit (IC) is an electronic circuit that is

constructed entirely on a single small chip of silicon. y Two broad categories of digital ICs. 1. 2.

Fixed-function logic Programmable logic

y In fixed-function logic, the logic functions are set by the

manufacturer and cannot be changed.

Solution:

14

4

Fixed-function IC package

5

Cutaway view of DIP (Dual-In-line Pins) chip

Families 74

Original, standard TTL

74S

TTL built with Schottkey transistors which provide better performance

74LS

TTL with Schottkey transistors and low power consumption

74AS

Advanced SchottkeyTTL. Twice as fast as “S” series.

74ALS

TTL with advanced Schottkey transistors, less power consumption, and better performance

74F

Fast TTL – falls somewhere between 74AS and 74ALS

74HC

Chips built with high-speed CMOS transistors – for use with CMOS-only circuits

74HCT

High-speed CMOS with TTL-compatible logic levels

74VHC

Very-high speed CMOS

74VHCT

Very-high speed CMOS with TTL compatibility

9

Complexity Classifications

MSI

Fixed-function digital lCs are classified according to their complexity. y Small-scale integration (SSI) y up to ten equivalent gate circuits on a single chip y basic gates and flip-flops.

y Medium-scale integration (MSI) y from 10 to 100 equivalent gates on a chip. y encoders, decoders, counters, registers, multiplexers, arithmetic

For the next couple lectures, we will study most of these 74-series MSI.

circuits, small memories y Large-scale integration (LSI) y Very large-scale integration (VLSI) y Ultra large-scale integration (ULSI) 6

10

7447

7442

SSI

MSI

A B C D

inst1

A B C D LTN RBIN BIN

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N

inst2

A0 B0 A1 B1 ALBO A2 AEBO B2 AGBO A3 B3 ALBI AEBI AGBI inst3 COMPARATOR

BCD TO 7SEG

BCD TO DEC

74138

74139

Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N inst4 3:8 DECODER

inst5

74147

Y10N Y11N Y12N Y13N Y20N Y21N Y22N Y23N

A1 B1 A2 B2 G1N G2N

A B C G1 G2AN G2BN

74x00

7485

OA OB OC OD OE OF OG RBON

1N 2N 3N 4N 5N 6N 7N 8N 9N

2:4 DECODER

inst6

74151 A B C D0 D1 D2 D3 D4 D5 D6 D7 GN

74154

Y WN

A B C D G1N G2N

inst8 MULTIPLEXER

7

11

Example of Data Sheet

inst

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N O10N O11N O12N O13N O14N O15N

AN BN CN DN

ENCODER

74157 SEL A1 B1 A2 B2 A3 B3 A4 B4 GN inst9

74148 0N 1N 2N 3N 4N 5N 6N 7N EIN inst7

EON GSN A0N A1N A2N

ENCODER

74280

Y1 Y2 Y3 Y4

A B C D E F G H I inst10

74283 CIN A1 B1 A2 B2 A3 B3 A4 B4

ODD EVEN

PARITY GEN.

4 inst11

SUM1 SUM2 SUM3 SUM4 COUT

MULTIPLEXER

DECODER

Signals and Their Active Levels y Each input and output in a logic circuit should have a y y y y y

A NAND gate

y 8

12

descriptive alpha-numeric label, the signal’s name. A signal is active high if it performs the named action or denotes the named condition when it is HIGH (H) or 1. A signal is active low if it performs the named action or denotes the named condition when it is LOW (L) or 0. If not specified, assume active-high signal. A signal is said to be asserted when it is at its active level. A signal is said to be negated (or, sometimes, deasserted) when it is not at its active level. A bus is a collection of two or more related signal lines.

The “_L” suffix is used to indicate active-LOW signal

Simple Decoder

BIN/DEC Decoder

A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Input A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

13

A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Output X 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Two simple decoders that detect the presence of the binary code 0011 are shown below. The first has an active HIGH output; the second has an active LOW output.

A3 0 0 0 0 A0 0 X_L 0 A1 0 0 A2 1 1 1 A3 1 1 1 Active-LOW decoder for 0011 1 1

A0 X

A1 A2 A3 Active-HIGH decoder for 0011

(A0 is the LSB and A3 is the MSB)

y The input has n bits

y The output has 2n bits. Only one bit is asserted at any time. Input A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Decoding gates

Output X_L 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

y Also known as “1-out-of-m” (where m

2n )

y Zero or more EN (enable) lines

Decoder Input

map Output

Enable Inputs 17

4:16 Decoder

I0 I1 I2 I3

Simple Decoder

Putting 16 simple decoders (and hence 16 decoding gates) into one package! I3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Two simple decoders that detect the presence of the binary code 0011 are shown below. The first has an active HIGH output; the second has an active LOW output. A0

A0 X

A1

14

map

4:16 Decoder

A decoder is a logic circuit that detects the presence of a specific combination of bits at its input.

X

A1

A2

A2

A3

A3

Active HIGH decoder for 0011

Active LOW decoder for 0011

(A0 is the LSB and A3 is the MSB)

Input I2 I1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

I0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

O15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

O14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

O13 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

O12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

O11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

O10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

O0 O2 O1

O15

Output O 9 O8 O7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

18

O 6 O5 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

O4 O 3 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

O2 O1 O 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Note: All signals here are active-HIGH.

Most MSI decoders were originally designed with active-LOW output.

Exercise

4:16 Decoder with Active-LOW outputs

Assume the output of the decoder shown below is a logic 1. What are the inputs to the decoder? A0 = 0

A1 = 1 1 A2 = 0

A3 = 1

15

19

Binary-to-Decimal (BIN/DEC ) Decoder

4:16 Decoder with Active-LOW outputs

y Many output lines.

The binary-to-decimal decoder shown here has 16 outputs – one for each combination of binary inputs.

y Only one of the output line is asserted at any time. y To find out which output line is asserted, consider the inputs

Bin/Dec

as one binary number. Convert this binary number to a decimal number. This decimal number tells which output line is asserted by the inputs. 4-bit binary input

Alternative Names: •4-line-to16-line decoder •1-of-16 decoder

map Output

Enable Inputs 16

0 1

Decoder Input

1 1

20

A0 A1 A2 A3

The bubbles indicate activeLOW outputs. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1

Decimal outputs

The BIN/DEC label indicates that a binary input makes the corresponding decimal output active.

4:16 Decoder with EN

74x154: Logic Diagram

Don’t be afraid! Conceptually, the logic diagram for decoder is not difficult. We will study the logic diagram of the 2:4 decoder in detail. 21

Note: All signals here are active-HIGH.

4:16 Decoder

25

(Active-HIGH EN) Active-LOW output

What do you need to know? y On the exam/quiz/hw, when you see a

logic symbol, you should be able to write down the following items on your own:

74154

y The description of its function. y The truth table.

A B C D G1N G2N

y The logic diagram.

inst

22

DECODER

26

4:16 Decoder

Active-LOW EN Active-LOW output

Exercise Find the truth table of the 1-to-2 line decoder below. Then, implement the 1-to-2 line decoder. I

23

Y0 Y1

27

74x154: 4:16 Decoder Active-LOW EN Active-LOW output

A LOW level on each chip select input is required to make the enable gate output (EN) HIGH.

Application: Port Address Decoder y Decoder can be used in

computers for input/output selection. y Computers communicate with peripherals by sending and/or receiving data through what is known as input/output (I/O) ports. y A decoder can be used to select the I/O port so that data can be sent or received from a specific external device.

Alternative logic symbol 74154

24

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N O10N O11N O12N O13N O14N O15N

Include two active-LOW enable (CS) lines which must be at their active level to enable the outputs. These lines can be used to expand the decoder to larger inputs.

A B C D G1N G2N

The number here indicates the location on the IC

inst

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N O10N O11N O12N O13N O14N O15N

DECODER

28

How can we build a larger decoder from smaller ones?

The Logic Diagram for 2:4 Decoder

Decoder Expansion

2-to-4 line decoder with enable input

Construct a 3-to-8 decoder from two 2-to-4 decoders 3:8 DEC

1 1 0

A0 A1 A2

0 0 0 1

D4 D5 D6 D7

0 0 0 0

What should be put in here?

0112 = 310

Y1

D0 D1 D2 D3

EN  I1  I 0

29

33

Truth Tables of Basic Decoder

Decoder Expansion

How can we build a larger decoder from smaller ones?

Construct a 3-to-8 decoder from two 2-to-4 decoders

2:4 DEC 2:4 DEC

Input Output I1 I0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

Y0 Y1 Y2 Y3

I0 I1

3:8 DEC

0 1 1

A0 A1 A2

D0 D1 D2 D3

0 0 0 0

D4 D5 D6 D7

0 0 1 0

3:8 DEC

30

Input A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

Output A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0

Decoder Expansion

3:8 DEC D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 A2

What should be put in here?

1102 = 610

34

How can we build a larger decoder from smaller ones?

Decoder Expansion

Construct a 3-to-8 decoder from two 2-to-4 decoders

Construct a 3-to-8 decoder from two 2-to-4 decoders

3:8 DEC

3:8 DEC D0 D1 D2 D3

A0 A1 A2

How can we build a larger decoder from smaller ones?

1 1 1

What should be put in here?

A0 A1 A2

31

0 0 0 0

D4 D5 D6 D7

0 0 0 1

What should be put in here?

1112 = 710

D4 D5 D6 D7

D0 D1 D2 D3

35

Decoder Expansion

How can we build a larger decoder from smaller ones?

Decoder Expansion

Construct a 3-to-8 decoder from two 2-to-4 decoders

Construct a 3-to-8 decoder from two 2-to-4 decoders: Observe that the truth table of the 3:8 DEC contains two truth tables of the 2:4 DEC.

3:8 DEC

0 1 0

0102 = 210

D0 D1 D2 D3

A0 A1 A2

0 0 1 0

3:8 DEC A2 0 0 0 0 1 1 1 1

What should be put in here? D4 D5 D6 D7

0 0 0 0

Input A1 0 0 1 1 0 0 1 1

A0 D7 D6 D5 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0

Output D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2:4 DEC Input Output I1 I0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

Two large areas of 0s (negated) These areas correspond to A2.

32

36

Decoder Expansion

Decoder Expansion

Construct a 3-to-8 decoder from two 2-to-4 decoders:

A2 is connected to the EN of each 2:4 decoder to choose the 1 that we want.

2:4 DEC A0 A1

2:4 DEC Y0 Y1 Y2 Y3

I0 I1

A2

D0 D1 D2 D3

1 1 1

A0 A1 A2

Y0 Y1 Y2 Y3

I0 I1

112 = 310

D0 D1 D2 D3

0 0 0 0

D4 D5 D6 D7

0 0 0 1

EN

1112 = 710

2:4 DEC Y0 Y1 Y2 Y3

I0 I1

D4 D5 D6 D7

2:4 DEC I0 I1

112 = 310

Y0 Y1 Y2 Y3

EN

37

41

Decoder Expansion

Decoder Expansion: Summary

Construct a 3-to-8 decoder from two 2-to-4 decoders:

y To increase the input by one bit (2:4 to 3:8) y Use two smaller decoders. y Connect the lower significant bits to both decoders.

2:4 DEC

1 1 1

A0

I0

A1 A2

Y0 Y1 Y2 Y3

I1

112 = 310

1112 = 710

D0 D1 D2 D3

0 0 0 1

y Use the MSB to control which decoder is enabled.

y To increase the input by two bits (2:4 to 4:16)

We don’t want a 1 here!

y Start with four smaller decoders. y Connect the lower significant bits to all four decoders. y Use the two higher significant bits to control which decoder is

2:4 DEC Y0 Y1 Y2 Y3

I0 I1

D4 D5 D6 D7

0 0 0 1

enabled.

112 = 310

38

42

How can we build a larger decoder from smaller ones?

Decoder Expansion

Example (A Revisit)

Construct a 3-to-8 decoder from two 2-to-4 decoders:

Construct a 3-to-8 decoder from two 2-to-4 decoders

2:4 DEC

1 1 0

A0 A1 A2

Y0 Y1 Y2 Y3

I0 I1

112 = 310

0112 = 310

D0 D1 D2 D3

0 0 0 1

D4 D5 D6 D7

0 0 0 1

Notice that this part is equivalent to a 1:2 decoder.

2:4 DEC Y0 Y1 Y2 Y3

I0 I1

112 = 310

We don’t want a 1 here!

39

How can we add an active-HIGH enable input? Low order bits (A1, A0) select within decoders. High order bit (A2) controls which decoder is active.

43

Decoder Expansion

74x139: Dual 2:4 Decoder

A2 is connected to the EN of each 2:4 decoder to choose the 1 that we want.

y “Dual”: Two independent 2:4 decoders

y The outputs and the enable (E) input are active-LOW. y When E_L is HIGH all outputs are forced HIGH.

2:4 DEC

1 1 0

A0 A1 A2

Y0 Y1 Y2 Y3

I0 I1

112 = 310

Most MSI decoders were originally designed with activeLOW output.

D0 D1 D2 D3

0 0 0 1

D4 D5 D6 D7

0 0 0 0

E

EN

0112 = 310

2:4 DEC I0 I1

112 = 310

Y0 Y1 Y2 Y3

O3

EN

40

44

Notice that all of the signal names inside the symbol outline are active-HIGH, and that bubbles indicate active-LOW inputs and outputs.

74x139

Example (A Revisit) Construct a 4:16 decoder with an active-LOW enable from three 74x139.

n=2 k=2

n-to-2n decoder

k-to-2k decoders 45

49

74x139: Logic diagram

74x138: 3:8 Decoder y Active-LOW outputs

y Three enable inputs.

ActiveLOW Enable

This is a usual 2:4 decoder.

46

Active-LOW output because NAND gates are used instead of AND gates

50

Four 2:4 DEC in this column.

Example

This means “1”.

Example

Construct a 4:16 decoder with an active-LOW enable from three 74x139.

Construct a 4:16 decoder with an active-LOW enable (EN) from two 74x138 decoder.

Use one more 2:4 DEC to control which of the four decoders is enabled.

Because the 74x138 have both active-LOW EN and active-HIGH EN, we can use the extra bubble to replace the extra NOT gate.

47

51

n = 1, k = 2

Expansion: Summary (2) y To construct 1. 2.

(k+n)-to-2n+k

Example

decoders, can use

Construct a 5:32 decoder with two activevelow enable and one active-high enable from four 74x138 and one 74x139.

2n of k-to-2k decoders with EN and one n-to-2n decoders.

y Assume that the k+n bits inputs are

An+k-1,…,Ak+2,Ak+1,Ak,Ak-1,…,A2,A1,A0 y The connections are:

k-to-2k decoders n-to-2n decoder

y For each of the k-to-2k decoder with EN, connect A0,…,Ak-1 to its k inputs.

y EN of the rth decoder is connected to the rth output of the n-to-2n decoders. y The inputs of the n-to-2n decoder get Ak to An+k-1.

y Basically, each k-to-2k decoder works on the last k bits.

y We use the first n bit, via the n-to-2n decoder, to select which one (and

only one) of the k-to-2k decoders will be enabled.

48

n=2 k=3 52

This means “0”.

Four 2:4 DEC in this column.

Example

Construct a 5:32 decoder with active-LOW outputs from two 74x154 and one inverter.

Example

4:16 DEC

Implement a full adder circuit with a decoder and OR gates y S = ¦X,Y,Z(1,2,4,7) y C = ¦ X,Y,Z (3,5,6,7) Inputs

Outputs

A B Zin X Y C 0 0 0 0 1 1 1 1 53

57

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Cout C 0 0 0 1 0 1 1 1

S6 0 1 1 0 1 0 0 1

Note: If the decoder’s output is active-LOW, then we use NAND gates instead of the OR gates.

(Midterm: July 30!)

Exercise (Sample Exam Problem)

Other Decoders

y Construct a 5:32 decoder with active-LOW outputs and one

In general, a decoder converts coded information, such as binary number, into non-coded form.

active-LOW EN. y Use two 74x154 and one inverter.

Later, (if time permitted) we will talk about other types of decoder. 74154

A B C D G1N G2N

54

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N O10N O11N O12N O13N O14N O15N

58

Solution

Seven-Segment Display

74154

A0 A1 A2 A3 A4

A B C D G1N G2N

EN_L

inst

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N O10N O11N O12N O13N O14N O15N

DECODER

DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L

74154

A B C D G1N G2N

inst1

O0N O1N O2N O3N O4N O5N O6N O7N O8N O9N O10N O11N O12N O13N O14N O15N

DEC16_L DEC17_L DEC18_L DEC19_L DEC20_L DEC21_L DEC22_L DEC23_L DEC24_L DEC25_L DEC26_L DEC27_L DEC28_L DEC29_L DEC30_L DEC31_L

DECODER

55

59

Decoder as General Purpose Logic

Multiplexing/Demultiplexing

Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n-line decoder and m OR gate

y The multiplexer, or mux for short, is a logic circuit that

switches digital data from several input lines onto a single output line in a specified time sequence. y The demultiplexer (demux) is a logic circuit that switches digital data from one input line to several output lines in a specified time sequence

Observe that the 3:8 decoder generates all possible minterms. This is called TDM.

56

60

Multiplexer (Data Selector)

Multiplexer Expansion

y Select binary information from one of many input lines and

Use two 4:1 MUXs and one 2:1 to create 8:1 MUX.

directs the information to a single output line. y Allow digital information from several sources to be routed onto a single line for transmission over that line to a common destination. y Basic multiplexer has 1. 2.

3.

Data-input lines Data Select Single output line. Data-select (control) inputs

Y

D0 D1 D2 D3

S

2:1 MUX Y

MUX

Data Inputs

4:1 MUX

S0 S1

S0 S1

D0 D1

4:1 MUX Y

D0 D1 D2 D3

Output

61

65

Example: 4-to-1-line multiplexer

Multiplexer Expansion S0 S1 S2

S0 S1

4:1 MUX Y

D0 D1 D2 D3

S

2:1 MUX Y

D0 D1 D2 D3 D4 D5 D6 D7

62

S0 S1 D0 D1 D2 D3

Y

D0 D1

4:1 MUX Y

66

Multiplexer Expansion

4:1 MUX: Logic Diagram & Truth Table

Control signals S0, S1 simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7

Control variables 1 1 0

S0 S1 S2

4:1 MUX S0 112 = 310 S1 D0 D1 D2 D3

0112 = 310

Y

Control signal S2 chooses between the upper MUX’s output and the lower MUX’s output S=0

S

2:1 MUX Y

I0 I1 I2 I3 I4 I5 I6 I7

Data lines

63

D0 D1 D2 D3 D4 D5 D6 D7

4:1 MUX S0 11 = 3 2 10 S1 D0 D1 D2 D3

Y Y=I 3

D0 D1 Y

67

Example

Multiplexer Expansion Control signals S0, S1 simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7 1 1 1

S0 S1 S2

4:1 MUX S0 112 = 310 S1 D0 D1 D2 D3

1112 = 710

Y

Control signal S2 chooses between the upper MUX’s output and the lower MUX’s output S=1

S

2:1 MUX Y

I0 I1 I2 I3 I4 I5 I6 I7

64

68

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1

4:1 MUX S0 11 = 3 2 10 S1 D0 D1 D2 D3

Y

Y Y=I 7

MUX and Minterms

74x151: Logic Diagram

Mathematically, we may say that the output of the MUX is the weighted sum of all minterms (generated from the control variables) where the weights are the data inputs.

69

73

MUX as a Logic Function Generator

74x157 Quad 2-Input MUX y Four separate 2-input multiplexer.

2n:1 MUX can be used to implement any function of n variables.

y Each of the four multiplexers shares a common data-select

line and a common Enable. Example:

F

¦

A, B ,C

0,2,6,7

Note that no extra gate is needed!

Explanation:

Z

A  B  C  I 0  A  B  C  I1  A  B  C  I 2  A  B  C  I 3  A  B  C  I 4  A  B  C  I5  A  B  C  I 6  A  B  C  I 7

70

74

74x151: 8:1 MUX

Demultiplexer (DEMUX) y Reverse the multiplexing function.

y Take digital information from one line and distributes it to a

given number of output lines.

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75

74x151: 8:1 MUX

1:4 DEMUX y The data-input line goes to all of the AND gates.

y The two data-select lines enable only one gate at a time, and

the data appearing on the data-input line will pass through the selected gate to the associated data-output line.

This is the very similar to the logic diagram of the 2:4 decoder!

72

76

Decoder and DEMUX

y A half-adder can add two 1-bit numbers. y A full-adder adds three 1-bit numbers: A, B, Cin. y Let’s add A and B first and then add Cin to the result. Example: Find A+B+Cin when A = B = Cin = 1.

Observe that the logical connections inside are exactly the same. The only difference is how the signals are named. 77

First, we add A and B: 1 A: 1 + B: 1 A+B: 10

2:4 DEC

1:4 DEMUX

A+B: Cin: A+B+Cin:

0 10 + 1 ? 1

Do we need a third half-adder?

81

Example: Decoder as Demultiplexer

We can use the EN line of the decoder as the data-input line of the DEMUX.

y We will construct a full adder by first adding A and B using a

1:4 DEMUX

Data Input S0 S1

2:4 DEC

I1

A

B

B

6

6

S1

A

Cout

C1

B

6

6

S2

Cout

C2

6

Cin

D0 D1 D2 D3

Y0 Y1 Y2 Y3

I0

A

Cout

y Then, we use a second half-adder to add Cin to the result of

EN

y Need to think about an easy way to find Cout. 78

82

Half-adder: A digital circuit that adds two bits and produces a sum and an output carry. It cannot handle input carries.

Full-adder: A digital circuit that adds two bits and an input carry to produce a sum and an output carry.

The Output Carry of Full-Adder Cout

AB  BCin  ACin

This is from K-map.

AB  A  B Cin

AB  A  B  AB Cin

AB  A  B Cin  ABCin AB  A  B Cin C1  S1Cin A B

A B

6

6

S1

Cout C1

C1  C2 A B

6

6

S2

Cout

C2

6

Cin

79

1+1+0 = 210 = 102

Cout

Caution: The “+” here means binary addition (not the “OR” operation).

83

y The basic difference between a full-adder and a half-

y When one (multiple-bit) binary number is added to another,

each column generates a sum bit and a 1 or 0 carry bit to the next column to the left.

A: B:

6

A

Cout

B

6 Cout

80

1111 0111+ 7 + 1101 13 1010 0 = 20

y To add binary numbers with more than one bit, we must use

A B AB

additional full-adders. y For 2-bit numbers, two adders are needed; y for 4-bit numbers, four adders are used; y and so on. 84

y Example: Add the binary numbers 0111 and 1101 and show

y Example: Add the binary numbers 0111 and 1101 and show

1111 0111+ 7 + 1101 13 1010 0 = 20

A: B:

y 4 4-bit bit adder 0 1

11

1 0

The carry output of each adder is connected to the carry input of the next higher-order adder. These are called internal carries.

1111 0111+ 1101 0 10 0

A: B:

11

0 1

11

11

1 0

0

1

0

1 1

1 0

0

1 0

1

85

89

0

1 1

1 0

1 0

0+1+1 = 210 = 102

y Example: Add the binary numbers 0111 and 1101 and show

y Example: Add the binary numbers 0111 and 1101 and show

10 0111+ 1101 0

A: B:

y 4 4-bit bit adder 0 1

11

1 0

the equivalent decimal addition. Input Carry If there is no input carry to the LSB, then either a half-adder can be used or the carry input of a fulladder can be made 0 (grounded)

1111 0111+ 7 + 1101 13 1010 0 = 20

A: B:

11

0 1

11

11

1 0

0

0

1 0 86

1

0

1 1

1 0

1 0

90

1+1+0 = 210 = 102

y Example: Add the binary numbers 0111 and 1101 and show

y Two categories (based on the way in which internal carries from

y 4 4-bit bit adder 0 1

11

stage to stage are handled)

Carry bit from the right column

1. 2.

11 0111+ 1101 00

A: B:

1 0

1 0 87

y Externally, both types of adders are the same in terms of inputs

and outputs. y The difference is the speed at which they can add numbers. y The look-ahead carry adder is much faster than the ripple-carry

11

adder. y The speed with which an addition can be performed is limited by

0

the time required for the carries to propagate, or ripple, through all the stages of a parallel adder.

1 0 91

1+0+1 = 210 = 102

y Example: Add the binary numbers 0111 and 1101 and show

y A ripple carry adder is one in which the carry output of each

full-adder is connected to the carry input of the next higher-order stage (a stage is one full-adder). y Practical consideration: real devices/gates have propagation time.

111 0111+ 1101 10 0

A: B:

y 4 4-bit bit adder 0 1

11

1 0

y The sum and the

output carry of any stage cannot be produced until the input carry occurs. y This causes a time delay in the addition process

11 0

1 1 88

The output carry from the leftmost full-adder becomes the MSB in the sum

1 0

1+1+1 = 310 = 112

1 0 92

Error (Overflow)

y Speedup the addition process by eliminating ripple carry delay.

y Note that if the number of bits required for the answer is

y Reduce delay at the price of more complex hardware.

exceeded, error will occur. This occurs only if both numbers have the same sign. y The error will be indicated by an incorrect sign bit. y Some textbooks use the word “overflow” to denote this error.

y Anticipate the output carry of each stage.

10000001 = 127 10000001 = 127 100000010 = +2

01000000 = +128 01000001 = +129 10000001 = 126

Discard carry Wrong! The answer is incorrect and the sign bit has changed.

93

97

Adding two positive numbers produces an overflow if the sign of the result is negative.

Some textbooks denote this case by “underflow”.

Adding two negative numbers produces an underflow if the sign of the result is positive

Subtraction y Rules for subtraction: 2’s complement the subtrahend and

add the numbers. Discard any final carries. The result is in signed form. Example: Repeat the examples done previously, but subtract:

00011110 (+30) 00001110 (+14) 11111111 (1)  00001111 –(+15)  11101111 –(17)  11111000 –(8) 2’s complement subtrahend and add:

Minuend: Subtrahend:

00011110 = +30 11110001 = 15 1 00001111 = +15 Discard carry 94

98

00001110 = +14 00010001 = +17 00011111 = +31

11111111 = 1 00001000 = 8 1 00000111 = +7

Comparator y A comparator compares two quantities and indicates whether

or not they are equal.

95

99

Arithmetic Operations with Signed Numbers

74x85: 4-bit Magnitude Comparator

y Using the signed number notation with negative numbers in

2’s complement form simplifies addition and subtraction of signed numbers. y Rules for addition: Add the two signed numbers (as if they are unsigned number). Discard any final carries. The result is in signed form. Examples: 00011110 = +30 + 00001111 = +15 00101101 = +45

00001110 = +14 + 11101111 = 17 11111101 = 3

11111111 = 1 + 11111000 = 8 1 11110111 = 9

100

Encoder

Programmable Logic Devices

In general, the encoder converts information, such as a decimal number or an alphabetic character, into some coded form. Essentially, it performs a “reverse” decoder function.

1. 2.

d-function logic Fixed-function Programmable rammable logic

1001

This encoder accepts an active level on one of its inputs representing a digit, and converts it to a binary output.

101

BCD

Decimal

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

y Binary coded decimal (BCD) is

a weighted code that is commonly used in digital systems when it is necessary to show decimal numbers such as in clock displays. y Express each of the decimal digits with a binary code.

Binary

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Today, we will take a look at this device.

105

PLD (Programmable Logic Device)

BCD

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 00010000 00010001 00010010 00010011 00010100 00010101

102

y Historically, the first PLDs were

programmable logic arrays (PLAs) y A PLA is a combinational, two-

level AND-OR device that can be programmed to realize any SOP logic expression. y Hence, it can also be used to

implement minimal sum. y Most PLDs also have a

programmable inverter/buffer at the output of the AND-OR array. y Hence, it can also be used to

implemented POS expression and minimal product. 106

Decimal-to-BCD Encoder

Programmable link in PAL y Generally, PALs are implemented with fuse process

The decimal-to-BCD is an encoder with an input for each of the ten decimal digits and four outputs that represent the BCD code for the active digit. 1

technology and are, therefore, one-time programmable (OTP).

A0

2 3

A1

4 5 6 7 8

A2 A3

9

103

A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.

Example

Simplified Notation for PAL

y Q: Show how the decimal-to-BCD encoder converts the

y Actual PAL devices have many AND and OR gates.

decimal number 3 into a BCD 0011. y A: The top two OR gates have ones as indicated with the red lines. Thus the output is 0011.

y Most diagrams that you may see on a data sheet use simplified

1 0

1

2 0 1 3

1

4 5 6 7 8 9 104

107

0 0 0 0

0

0

0

0

notation to keep the schematic from being too complicated.

A0

A1 A2 A3 108

PLA (Programmable Logic Array) y PAL has a programmable AND array followed by a fixed OR array. y PLA has a programmable AND array followed by a programmable

OR array.

109

4u3 PLA with Six Product Terms Potential connections in the array are indicated by X’s; the device is programmed by establishing only the connections that are actually needed.

110