Device Operation & Timing Diagram

x16 DDR SDRAM

Device Operation & Timing Diagram

Device Operation & Timing Diagram

x16 DDR SDRAM

BURST MODE OPERATION Burst mode operation is used to provide a constant flow of data to memory locations(write cycle), or from memory locations(read cycle). There are two parameters that define how the burst mode operates. These parameters including burst sequence and burst length are programmable and determined by address bits A 0 ~ A 3 during the Mode Register Set command. The burst type is used to define the sequence in which the burst data will be delivered or stored to the DDR SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the below table. The burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. The burst length can be programmed to have values of 2, 4 or 8.

BURST LENGTH AND SEQUENCE Burst Length

Starting Address(A 2, A 1, A0 ) xx0

2

4

8

Sequential Mode

Interleave Mode

0, 1

0, 1

xx1

1, 0

1, 0

x00

0, 1, 2, 3

0, 1, 2, 3

x01

1, 2, 3, 0

1, 0, 3, 2

x10

2, 3, 0, 1

2, 3, 0, 1

x11

3, 0, 1, 2

3, 2, 1, 0

000

0, 1, 2, 3, 4, 5, 6, 7

0, 1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

011

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

BANK ACTIVATION COMMAND The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The DDR SDRAM has four independent Banks, so two Bank Select addresses(BA 0, BA 1) are supported. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time(t RCDRD / t RCDWR min ). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(t RRD min ). Bank Activation Command Cycle (CAS Latency = 3) 0

1

2

n

n+1

n+2

CK, CK Address

Bank A Row Addr.

Bank A Col. Addr.

Bank A Bank B Row Addr. Row. Addr. RAS-RAS delay time( tRRD )

RAS-CAS delay timet(tRCDRD for Read)

Command

Bank A Activate

NOP

NOP

READ A with Auto Precharge

ROW Cycle Time( tRC )

Bank A Activate

NOP

Bank B Activate

: Don ’t care

Device Operation & Timing Diagram

x16 DDR SDRAM

BURST READ OPERATION Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock after t RCD from the bank activation. The address inputs (A 0~A 7) determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4 and 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe adopted by DDR SDRAM until the burst length is completed. < Burst Length=4, CAS Latency= 3,4,5 > 0

1

2

3

4

5

6

7

8

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK CK Command

READ

NOP

t RPRE

DQS

tRPST

CAS Latency=3 DQ’s

Dout 0 Dout 1 Dout 2 Dout 3

t RPRE

DQS

tRPST

CAS Latency=4 DQ’s

Dout 0 Dout 1 Dout 2 Dout 3

t RPST

t RPRE

DQS CAS Latency=5 DQ’s

Dout 0 Dout 1 Dout 2 Dout 3

BURST WRITE OPERATION The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no real write latency required for burst write cycle. The first data for burst write cycle must be applied at the first rising edge of the data strobe enabled after t DQSS from the rising edge of the clock that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. < Burst Length=4 > 0

1

2

3

4

5

6

7

8

NOP

NOP

NOP

NOP

NOP

CK CK Command DQS DQ’s

NOP

WRITEA

NOP

t DQSSmax

WRITEB

t WPST

t WPREH t WPRES

Din a0 Din a1 Din a2 Din a3 Din b0 Din b1 Din b2 Din b3

Device Operation & Timing Diagram

x16 DDR SDRAM

BURST INTERRUPTION Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 tck. < Burst Length=4, CAS Latency=3 > 0

1

READ A

READ B

2

3

4

5

6

7

8

NOP

NOP

NOP

NOP

NOP

NOP

CK CK Command

NOP

DQS CAS Latency=3 DQ’s

Douta 0 D out a1 Doutb 0 Doutb1 Doutb 2 Doutb 3

Read Interrupted by Burst stop & a Write To interrupt a burst read with a write command, Burst stop command must be asserted to avoid data contention on the I/ O bus by placing the DQ ’s(Output drivers) in a high impedance state at least one clock cycle before the Write command is initiated. Refe to the below for the READ to WRITE latency without the burst stop between Read and Write command.

< Burst Length=4, CAS Latency=3 > 0

1

2

3

4

5

6

7

8

CK, CK Command

READ

Burst Stop

NOP

NOP

NOP

CAS Latency=3

NOP

NOP

tDQSS t WPREH

t RPRE

DQS

WRITE

Preamble

tWPRES

DQ’s

Dout 0

Dout 1

Read to write command latency at no burst stop between read and write command. CL3

CL4

CL5

BL2

5

6

7

BL4

6

7

8

BL8

8

9

10

(Clock)

Din 0

Din 1

Din 2

Din 3

Device Operation & Timing Diagram

x16 DDR SDRAM

Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read to precharge interval. A precharge command to output disable latency is equivalent to the CAS latency.

< Burst Length=8, CAS Latency=3 > 0

1

2

3

4

5

6

7

NOP

NOP

8

CK CK 1tCK

Command

READ

Precharge

NOP

NOP

NOP

NOP

t RPST

tRPRE

DQS

NOP

CAS Latency=3 DQ’s

Dout 0 Dout 1

Dout 2

Dout 3 Dout 4

Dout 5

Dout 6 Dout 7

Interrupted by precharge

Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by the new Write Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. < Burst Length=4 > CK CK

0

1

2

3

4

5

6

7

8

NOP

NOP

NOP

NOP

NOP

NOP

1tCK

Command DQS

NOP

WRITE A

WRITE B

tWPREH

t WPRES

DQ’s

Din a0

Din a1

Din b0

Din b1

Din b2

Din b3

Device Operation & Timing Diagram

x16 DDR SDRAM

Write Interrupted by a Read & DM • Write Interrupted by a Read function is not supported .

Write Interrupted by a Precharge & DM A Burst Write operation can be interrupted before completion of the burst by a precharge of the same bank. A Write Recovery time(tWR) is required before a Precharge command to finish the Write operation. When Precharge command is asserted, any residual data from the burst write cycle must be masked by DM.

< Burst Length=8 > 0

1

2

3

4

5

6

7

8

CK, CK Command

NOP

WRITE A

NOP

NOP

NOP

NOP

Precharge

tWR

tDQSSmax

NOP

tDQSSmax

DQS

tWPREH tWPREH t WPRES

Max tDQSS

WRITE B

DQ’s

Dina0

tWPRES Dina1

Dina2

Dina3

Dina4

Dina5

Dina6

Dina7

Dina0

Dina1

DM t WR

t DQSSmin

t DQSSmin

DQS t WPRES t WPREH

t WPRES t WPREH

Min tDQSS

DQ’s DM

Dina0

Dina1

Dina2

Dina3

Dina4

Dina5

Dina6

Dina7

Dinb0

Dinb1

Dinb2

Device Operation & Timing Diagram

x16 DDR SDRAM

BURST STOP COMMAND The Burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock only . The Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. When the Burst Stop command is issued during a burst read cycle, both the data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. The Burst Stop command, however, is not supported during a write burst operation. < Burst Length=4, CAS Latency= 3,4,5 > 0

1

2

3

4

NOP

NOP

5

6

7

8

NOP

NOP

NOP

CK CK Command

READ

Burst Stop

NOP

NOP

DQS CAS Latency=3 DQ’s

Dout 0 Dout 1

The burst ends after a delay equal to the CAS latency.

DQS CAS Latency=4 The burst ends after a delay equal to the CAS latency.

DQ’s

Dout 0 Dout 1

DQS CAS Latency=5 DQ’s

Dout 0 Dout 1

The burst ends after a delay equal to the CAS latency.

DM FUNCTION The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation the write data is masked immediately(DM to Data-mask Latency is zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge. < Burst Length=8 > CK CK Command

0

1

WRITE

NOP

2

3

4

5

6

7

8

NOP

NOP

NOP

NOP

NOP

NOP

NOP

tDQSS

DQS DQ’s

t WPREH tWPRES Din 0

Din 1 Din 2

DM masked by DM=H

Din 3 Din 4

Din 5

Din 6

Din7

Device Operation & Timing Diagram

x16 DDR SDRAM

AUTO-PRECHARGE OPERATION The Auto precharge command can be issued by having column address A 1 0 High when a Read or a Write command is asserted into the DDR SDRAM. If A 1 0 is low when Read or Write command is issued, then normal Read or Write burst operation is asserted and the bank remains active after the completion of the burst sequence. When the Auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during read or write cycle after tRAS (min) is satisfied.

Read with Auto Precharge If a Read with Auto-precharge command is initiated, the DDR SDRAM automatically starts the precharge operation on BL/2 clock later from a Read with Auto-Precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the Precharge time(t RP) has been satisfied.

< Burst Length=4, CAS Latency= 3> 0

1

2

3

4

5

6

7

8

NOP

NOP

NOP

NOP

NOP

CK, CK Command

BANK A ACTIVE

NOP

NOP

READ A Auto Precharge

t RCDRDmin) tR P

t RAS(min)

* Bank can be reactivated at completion of t RP

DQS CAS Latency=3 DQ’s

Douta0Douta1Douta2Douta3 Auto-Precharge starts

tRC(min)

When the Read with Auto precharge command is issued, new command can be asserted at T4,T5 and T6 respectively as follows.

Asserted command

For same Bank

For Different Bank

4

5

6

4

5

6

READ

READ + No AP *1

READ+ No AP

Illegal

Legal

Legal

Legal

READ+AP

READ + AP

READ + AP

Illegal

Legal

Legal

Legal

Active

Illegal

Illegal

Illegal

Legal

Legal

Legal

Precharge

Legal

Legal

Illegal

Legal

Legal

Legal

*1

: AP = Auto Precharge

Device Operation & Timing Diagram

x16 DDR SDRAM

Write with Auto Precharge If A 1 0 is high when Write command is issued , the write with Auto-Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). < Burst Length=4 > 0

1

2

3

4

5

6

7

8

CK CK BANK A ACTIVE

Command

NOP

WRITE A Auto Precharge

NOP

NOP

Din 0

Din 1 Din 2

NOP

NOP

NOP

NOP

DQS DQ’s

* Bank can be reactivated at completion of tR P

Din 3

t WR

*Note 1

t RP

Internal precharge start

Asserted command

For same Bank

For Different Bank

3

4

5

6

7

8

3

4

5

6

7

WRITE+ No AP *1

WRITE+ No AP

Illegal

Illegal

Illegal

Illegal

Legal

Legal

Legal

Legal

Legal

WRITE+ AP

WRITE+ AP

WRITE+ AP

Illegal

Illegal

Illegal

Illegal

Legal

Legal

Legal

Legal

Legal

READ

Illegal

READ+NO AP+DM

READ+NO AP+DM

READ+ NO AP

Illegal

Illegal

Illegal

Illegal

Illegal

Legal

Legal

READ+AP

Illegal

READ+ AP+DM

READ+ AP+DM

READ+ AP

Illegal

Illegal

Illegal

Illegal

Illegal

Legal

Legal

Active

Illegal

Illegal

Illegal

Illegal

Illegal

Illegal

Legal

Legal

Legal

Legal

Legal

Precharge

Illegal

Illegal

Illegal

Illegal

Illegal

Illegal

Legal

Legal

Legal

Legal

Legal

WRITE

Note : 1. For the case of tWR = 2 clock

Device Operation & Timing Diagram

x16 DDR SDRAM

PRECHARGE COMMAND The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and W E are low and CAS is high at the rising edge of the clock, CK. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA 0, BA 1 ) are used to define which bank is precharged when the command is initiated. For write cycle, tWR (min.) must be satisfied from the start of the last burst write cycle until the precharge command can be issued. After t RP from the precharge, an active command to the same bank can be initiated. < Bank Selection for Precharge by Bank address bits > A 10 /AP

BA1

BA 0

Precharge

0

0

0

Bank A Only

0

0

1

Bank B Only

0

1

0

Bank C Only

0

1

1

Bank D Only

1

X

X

All Banks

AUTO REFRESH

1

2

3

4

CKE =High

Auto Refresh

PRE

6

~

Command

5

~

0 CK, CK

~ ~

An Auto Refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock, CK. All banks must be precharged and idle for a t RP(min) before the Auto Refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the t RFC( min).

tR P

t RFC

7

8

9

10

CMD

11

Device Operation & Timing Diagram

x16 DDR SDRAM

SELF REFRESH

t IS

~ ~ ~ ~

~ ~

CKE

Read

~ ~

~ ~ ~ ~

Active

~ ~

Self Refresh

Command

~ ~ ~ ~

CK CK

~ ~

A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL.

tXSA t XSR

* Before/After self refresh mode, burst auto refresh cycle is recommended.

POWER DOWN MODE

3

CK, CK

Command

Precharge

Precharge power down Entry

4

5

6

7

8

Precharge power Active down Exit

9

Active power down Entry

10

~ ~

2

~

1

~

0

~ ~

The power down is entered when CKE Low,and exited when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. The all banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tCK+tIS prior to Row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period(t REF ) of the device.

NOP

11

12

Active power down Exit NOP

CKE tIS

~

~

tPDEX tIS

t IS

t IS

13

Read

14

Device Operation & Timing Diagram

x16 DDR SDRAM

SIMPLIFIED TRUTH TABLE CKEn-1

CKEn

CS

RAS

CAS

WE

DM

Extended Mode Register

H

X

L

L

L

L

X

OP CODE

Mode Register Set

H

X

L

L

L

L

X

OP CODE

L

L

L

H

X

X

COMMAND Register

Auto Refresh

H Entry

Refresh

Self Refresh

Exit

H

BA 0,1 A 10/AP

L

H

L

H

H

H

H

X

X

X

X

3

L

L

H

H

X

V

Read & Column Address

Auto Precharge Disable

H

X

L

H

L

H

X

V

Write & Column Address

Auto Precharge Disable

Auto Precharge Enable L

H

L

L

X

V

Auto Precharge Enable H

X

L

H

H

L

X

H

X

L

L

H

L

X

All Banks H

L

Active Power Down Exit Entry

L H

H L

Precharge Power Down Mode Exit

L

Column Address

L

Column Address

H

Bank Selection

Entry

Row Address

H X

L

DM

H

No Operation Command

H

H

X

X

X

L

V

V

V

X

X

X

X

H

X

X

X

L

H

H

H

H

X

X

X

L

H

H

H

H

X V

L

X

H

5 5 5 5, 7 8

X 6

X X X X X X

X X

3

X

X

Precharge

3 3

H

H

Note

1, 2

L

Bank Active & Row Addr.

Burst Stop

Address*4

H

X

X

X

L

H

H

H

V

X

X

X

9

(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code. A 0 ~ A10 & BA 0 ~ BA 1 : Program keys for 4Mx16 DDR (@EMRS/MRS) A 0 ~ A11 & BA 0 ~ BA 1 : Program keys for 8Mx16 DDR (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycle of EMRS/MRS 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4.

4Mx16 DDR

8Mx16 DDR

A9 ~ A 0

A 11, A9 ~ A 0

Device Operation & Timing Diagram

x16 DDR SDRAM

5. BA 0 ~ BA 1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. 6. If A10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 7. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 8. Burst stop command is valid at every burst length. 9. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

Device Operation & Timing Diagram

x16 DDR SDRAM

FUNCTION TRUTH TABLE Current State CS RAS IDLE

ROW ACTIVE

READ

CAS WE

Address

Command

Action

H

X

X

X

X

DESEL

NOP

L

H

H

H

X

NOP

NOP

L

H

H

L

X

TERM

NOP

L

H

L

X

BA, CA, A 10

READ/WRITE

ILLEGAL*2

L

L

H

H

BA, RA

ACT

Bank Active, Latch RA

L

L

H

L

BA, A 1 0

PRE/PREA

NOP*4

L

L

L

H

X

REFA

AUTO-Refresh*5

L

L

L

L

Op-Code, Mode-Add

MRS

Mode Register Set*5

H

X

X

X

X

DESEL

NOP

L

H

H

H

X

NOP

NOP

L

H

H

L

X

TERM

NOP

L

H

L

H

BA, CA, A 10

READ/READA

Begin Read, Latch CA, Determine Auto-Precharge

L

H

L

L

BA, CA, A 10

WRITE/WRITEA

Begin Write, Latch CA, Determine Auto-Precharge

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 1 0

PRE/PREA

Precharge/Precharge All

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add

MRS

ILLEGAL

H

X

X

X

X

DESEL

NOP(Continue Burst to END)

L

H

H

H

X

NOP

NOP(Continue Burst to END)

L

H

H

L

X

TERM

Terminate Burst

L

H

L

H

BA, CA, A 10

READ/READA

Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3

L

H

L

L

BA, CA, A 10

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 1 0

PRE/PREA

Terminate Burst, Precharge

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add

MRS

ILLEGAL

WRITE/WRITEA

ILLEGAL

Device Operation & Timing Diagram

x16 DDR SDRAM

FUNCTION TRUTH TABLE(continued) Current State

CS

RAS

CAS

WE

WRITE

H

X

X

X

X

DESEL

NOP(Continue Burst END)

L

H

H

H

X

NOP

NOP(Continue Burst END)

L

H

H

L

X

TERM

ILLEGAL

L

H

L

H

BA, CA, A 1 0

READ/READA

ILLEGAL

L

H

L

L

BA, CA, A 1 0

Terminate Burst, Latch CA, WRITE/WRITEA Begin new Write, Determine AutoPrecharge*3

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 10

PRE/PREA

Terminate Burst With DM=High, Precharge

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add MRS

ILLEGAL

H

X

X

X

X

DESEL

NOP(Continue Burst END)

L

H

H

H

X

NOP

NOP(Continue Burst END)

L

H

H

L

X

TERM

ILLEGAL

L

H

L

X

BA, CA, A 1 0

READ/WRITE

ILLEGAL*2

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 10

PRE/PREA

ILLEGAL*2

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add MRS

ILLEGAL

H

X

X

X

X

DESEL

NOP(Continue Burst to END)

L

H

H

H

X

NOP

NOP(Continue Burst to END)

L

H

H

L

X

TERM

ILLEGAL

L

H

L

X

BA, CA, A 1 0

READ/WRITE

ILLEGAL*2

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 10

PRE/PREA

ILLEGAL*2

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add MRS

READ with AUTO PRECHARGE

WRITE with AUTO RECHARGE

Address

Command

Action

ILLEGAL

Device Operation & Timing Diagram

x16 DDR SDRAM

FUNCTION TRUTH TABLE(continued) Current State

CS

RAS

CAS

WE

PRECHARGING

H

X

X

X

X

DESEL

NOP(Idle after t RP)

L

H

H

H

X

NOP

NOP(Idle after t RP)

L

H

H

L

X

TERM

NOP

L

H

L

X

BA, CA, A 10

READ/WRITE

ILLEGAL*2

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 1 0

PRE/PREA

NOP*4(Idle after tRP )

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add

MRS

ILLEGAL

H

X

X

X

X

DESEL

NOP(ROW Active after t RCD )

L

H

H

H

X

NOP

NOP(ROW Active after t RCD )

L

H

H

L

X

TERM

NOP

L

H

L

X

BA, CA, A 10

READ/WRITE

ILLEGAL*2

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 1 0

PRE/PREA

ILLEGAL*2

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add

MRS

ILLEGAL

ROW ACTIVATING

Address

Command

Action

Device Operation & Timing Diagram

x16 DDR SDRAM

FUNCTION TRUTH TABLE(continued) Current State

CS

RAS

CAS

WRITE RECOVERING

H

X

X

X

X

DESEL

NOP

L

H

H

H

X

NOP

NOP

L

H

H

L

X

TERM

NOP

L

H

L

H

BA, CA, A 1 0

READ

ILLEGAL*2

L

H

L

L

BA, CA, A 1 0

WRITE/WRITEA

New Write, Determine AP.

L

L

H

H

BA, RA

ACT

ILLEGAL*2

L

L

H

L

BA, A 10

PRE/PREA

ILLEGAL*2

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add

MRS

ILLEGAL

H

X

X

X

X

DESEL

NOP(Idle after t RP)

L

H

H

H

X

NOP

NOP(Idle after t RP)

L

H

H

L

X

TERM

NOP

L

H

L

X

BA, CA, A 1 0

READ/WRITE

ILLEGAL

L

L

H

H

BA, RA

ACT

ILLEGAL

L

L

H

L

BA, A 10

PRE/PREA

ILLEGAL

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-Add

MRS

ILLEGAL

REFRESHING

WE

Address

Command

Action

ABBREVIATIONS : H=High Level, L=Low level, V=Valid, X=Don’t Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Same Bank¢s previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed. ILLEGAL = Device operation and/or data-integrity are not guaranteed.

Device Operation & Timing Diagram

x16 DDR SDRAM

FUNCTION TRUTH TABLE for CKE CKE n-1

CKE n

CS

RAS

CAS

WE

Add

H

X

X

X

X

X

X

INVALID

L

H

H

X

X

X

X

Exit Self-Refresh*1

L

H

L

H

H

H

X

Exit Self-Refresh*1

L

H

L

H

H

L

X

ILLEGAL

L

H

L

H

L

X

X

ILLEGAL

L

H

L

L

X

X

X

ILLEGAL

L

L

X

X

X

X

X

NOP(Maintain Self-Refresh)

H

X

X

X

X

X

X

INVALID

L

H

H

X

X

X

X

Exit Power Down*2

L

H

L

H

H

H

X

Exit Power Down*2

L

H

L

H

H

L

X

ILLEGAL

L

H

L

H

L

X

X

ILLEGAL

L

H

L

L

X

X

X

ILLEGAL

L

L

X

X

X

X

X

NOP(Maintain Power Down)

ALL BANKS

H

H

X

X

X

X

X

Refer to Function True Table

IDLE

H

L

H

X

X

X

X

Enter Power Down*3

H

L

L

H

H

H

X

Enter Power Down*3

H

L

L

H

H

L

X

ILLEGAL

H

L

L

H

L

X

X

ILLEGAL

H

L

L

L

H

H

RA

Row (& Bank) Active

H

L

L

L

L

H

X

Enter Self-Refresh*3

H

L

L

L

L

L

OP Code

L

X

X

X

X

X

X

Refer to Current State=Power Down

Any State

H

H

X

X

X

X

X

Refer to Function True Table

other than

H

L

X

X

X

X

X

Begin Clock Suspend next cycle*4

L

H

X

X

X

X

X

Exit Clock Suspend next cycle*4

L

L

X

X

X

X

X

Maintain Clock Suspend

Current State SELFREFRESHING

Both Bank Precharge POWER DOWN

listed above

Action

Mode Register Access

ABBREVIATIONS : H=High Level, L=Low level, X=Don’t Care Note : 1. After CKE’s low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to hig h transition to issue a new command. 2. CKE low to high transition is asynchronous as if restarts internal clock. A minimum setup time "tSS + one clock" must be satisfied before any command other than exit. 3. Power-down and self refresh can be entered only from the all banks idle state. 4. Must be a legal command.

Device Operation & Timing Diagram

x16 DDR SDRAM

SIMPLIFIED STATE DIAGRAM

SELF REFRESH REFS REFSX MRS

MODE REGISTER SET

REFA

AUTO REFRESH

IDLE CKEL CKEH

POWER DOWN

ACT

POWER DOWN

CKEL CKEH ROW ACTIVE

BST

WRITE

READ WRITEA

READA

WRITE WRITEA

READ

WRITEA

READA READA PRE

WRITEA

READA PRE

POWER APPLIED

POWER ON

PRE

PRE

PRE CHARGE

Automatic Sequence Command Sequence WRITEA : Write with autoprecharge READA : Read with autoprecharge

x16 DDR SDRAM Device Operation & Timing Diagram

Basic Timing (Setup, Hold and Access Time @BL=2, CL=3)

CK, CK CK E CS RA S

CAS

BA[1:0]

A10/A P ADDR*

WE

DQS

DQ

DM COMMAND

2

3

4

tC H tCK

tCL

6

1

5

0

HIGH

tIH

BA c

tIS

BA b

tD QSS

tDQSH

7

8

Dc1

tWPST

Dc0

tDQSL

tDH

Db 1

tDH tDS

Db0

WRITEC

tWPREH

B Aa

t WPRES

Cc

tRPST

Qa1

WRITE B

tDS

Cb

tRPRE

tDQSQ

Qa0

Ca

READA

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

Hi- Z

Hi- Z

x16 DDR SDRAM Device Operation & Timing Diagram

Multi Bank Interleaving READ (@BL=4, CL=3)

CK, CK

CKE

CS

RAS

CAS

B A[1:0]

A10/AP A DDR*

WE

DQS

DQ

DM

1

2

BAb

0

BAa

ACTIVEB

Rb

Rb tRRD

Ra

Ra

COMMA ND ACTIVEA

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

3

4

HIGH

6

7

BAb

5

BAa

Cb

READB

Ca

READA

8

Qa0

Qa1

9

Qa2

Qa3

10

Qb0

x16 DDR SDRAM Device Operation & Timing Diagram

Multi Bank Interleaving WRITE (@BL=4, CL=3)

CK, CK

CK E

CS

RA S

0

B Aa

CA S

B A[1:0]

Ra

Ra

A10/AP A DDR*

WE

DQ S

DQ

DM tRCDWR COMMAND A CTIVE A

1

B Aa

Ca

tRRD

WRITEA

Da0

2

BA b

Rb

Rb

3

B Ab

Cb

Da3

WRITE B

Da2

tRCDWR

Da 1

A CTIVE B

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

4

Db1

HIGH

Db0

Db 2

5

Db 3

6

7

8

x16 DDR SDRAM Device Operation & Timing Diagram

Auto Precharge after READ Burst (@BL=8)

CK, CK CK E CS RA S

CA S BA[1:0] A 10/A P ADDR*

WE

DQS (CL=3) DQ (CL=3) DM CO MMAND

0

1

BAa

Ca

READA

2

3

tRA S(min )

4

Qa 1

HIG H

Q a0

Note 1. The r ow active comma nd of th e pre ch arg e ban k can b e issu ed after tRP fro m this po int.

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

5

Q a3

6

tRP

Q a4

Q a5

Au to p recha rge start Note 1

Qa2

7

Q a6

Q a7

8

B Aa

Ra

Ra

A CTIV EA

x16 DDR SDRAM Device Operation & Timing Diagram

Auto Precharge after WRITE Burst (@BL=4)

CK, CK

CK E

CS

RA S

CA S

B A[1:0]

A 10/A P ADDR*

WE

DQS

DQ

DM

0

B Aa

Ca

COMMA ND WRITE A

1

Da0

tWP REH

tWP RES Da1

2

Da2

Da 3

3

4

HIGH

tWR

Note 1. The r ow acti ve comma nd of th e pre ch arg e ban k can b e issu ed after tRP fro m this po int.

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

5

6

Au to p recha rge start

Note 1

tRP

7

8

B Aa

Ra

Ra

ACT IVEA

x16 DDR SDRAM Device Operation & Timing Diagram

Normal WRITE Burst (@BL=4)

CK, CK

CKE

CS

RAS

CAS

B A[1:0]

A10/AP ADDR

WE

DQS

DQ

DM

COMMA ND

0

1

B Aa

Ca

WRITEA

2

Da 0

tWP RE H tWP RE S

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

Da 1

3

Da2

Da3

4

HIG H

5

tWR

6

BA a

PRE C HARGE

7

8

x16 DDR SDRAM Device Operation & Timing Diagram

Write Interrupted by Precharge & DM (@BL=8)

CK , CK

CKE

CS

RAS

CAS

BA [1 :0 ]

A10/AP A DDR

WE

DQ S

DQ

DM

0

BA a

Ca

1

Da0

tWP REH

tWP RES

COMMAND WRITEA

Da1

2

Da2

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

Da3

3

Da4

tWR

Da 5

4

HIGH

BAa

Da6

PRE CHARGE

Da7

BAb

5

Cc

B Ac

6

WRITE C

Db0

Cb

WRITE B tCCD

Db1

7

Dc0

Dc1

8

Dc2

x16 DDR SDRAM Device Operation & Timing Diagram

Read Interrupted by Precharge (@BL=8)

CK , CK CK E CS RA S CA S BA [1 :0 ]

A 10/A P ADDR

WE

DQS( CL=3)

DQ( CL=3)

DM

CO MMAND

0

1

BAa

Ca

READA

2

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

3

4

HIGH

B Aa

Qa 0

PRE CH AR GE

Qa 1

5

Q a2

Qa 3

6

Q a4

Qa5

7

8

x16 DDR SDRAM Device Operation & Timing Diagram

Read Interrupted by Burst stop & Write (@BL=8, CL=3)

CK, CK

CKE

CS

RAS

CAS

B A[1:0]

A10/AP ADDR

WE

DQS

DQ

DM

0

1

2

3

4

HIG H

5

BA b

Qa1

BA a

Qa 0

WRITE B

Cb

Burst Stop

Ca

CO MMAND RE ADA

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

6

Db 0

Db 1

7

Db2

Db3

8

Db 4

Db

x16 DDR SDRAM Device Operation & Timing Diagram

Read Interrupted by a Read (@BL=8, CL=3)

CK , CK

CK E

CS

RA S

CA S

BA [1 :0 ]

A 10/AP ADDR

WE

DQ S

DQ

DM

COMMAND

1

BA b

0

B Aa

READB

Cb

tCCD

Ca

READA

2

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

3

Qa0

Qa 1

4

HIG H

Qb 0

Q b1

5

Q b2

Q b3

6

Q b4

Q b5

7

Qb6

Qb7

8

x16 DDR SDRAM Device Operation & Timing Diagram

DM Function (@BL=8) only for write

CK, CK

CK E

CS

RA S

CA S

B A[1:0]

A 10/A P ADDR

WE

DQ S( CL =3 )

DQ( CL =3 )

DM

CO MMAND

0

1

BAa

Ca

2

Da0

tWP RE H

tWP RE S

WRITEA

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

Da1

Da2

3

Da3

4

HIGH

Da4

Da 5

Da6

5

Da7

6

7

8

x16 DDR SDRAM

CK, CK

CKE

0

High -Z

1

~

2

3

4

HIGH

t RP

~ ~ ~

~

~ ~

~ ~

~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

~ ~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

~

~ ~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

~

~

~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

~ ~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

~

~

~

~ ~

~

~

~

6

7

tMRD

~ ~

~ ~

~

Mod e Register Se t Command

t RFC

ADDRE SS K EY

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

t RF C

2 nd A uto Re fr esh Co mmand

~ ~ ~ ~ ~ ~

~

1 st Au to Refresh Comman d

~ ~

~

t MRD

~

A DDRESS K EY

t MRD

MRS DLL Reset Co mmand

Minimu m o f 2 Refresh Cycles are re qui red

P recha rge Co mmand All B ank

~ ADDRES S KE Y

~

High -Z

tR P

A 11, A 9 ~ A 0

8Mx16 DDR

EMRS Comman d

A9 ~ A0

4Mx16 DDR

Note*

Inp uts must be Pr echar ge stab le for 200 us Comma nd All Ba nk

HIGH

~

CS

RAS

CAS

B A[1]

B A[0]

A10/AP A DDR

WE

DQS DQ DM

~

Device Operation & Timing Diagram

Power up Sequence & Auto Refresh(CBR)

8

A ny Command

x16 DDR SDRAM Device Operation & Timing Diagram Mode Register Set

CK , CK

CK E

CS

RA S

CA S

BA [1 :0 ]

A 10/AP ADDR

WE

DQ S

DQ

DM

0

Hig h-Z

Hig h-Z

Hig h-Z

1

P recha rge Al l B ank Co mmand

2

A 11, A 9 ~ A 0

8Mx16 DDR

Note*

A9 ~ A0

4Mx16 DDR

t RP

3

4

L OW

A DDRE SS K EY

Mo de Resister Set Co mmand

5

t MRD

6

A ny Comman d

7

8