Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G) K. Mori, M. Suzuki, Y. Ohara, S. Matsuo and A. Asano

Toshiba Corp. Semiconductor Company Jan. 25, 2007 ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Outline „ System Overview „ Chip Specification „ Power Comparison „ Low Power Analysis - Multi-Vth Technique - Clock Gating Techniques - Software Architecture „ Summary ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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S1G in Mobile Phone System Digital TV Tuner OFDM

TS

RF

BB LSI Audio

MODEM 3G/GPRS/

Video/JPEG

BT

TV in TV out

S1G

ARM

MCP

PS regulator

2D/3D Graphic

eDRAM

H.264 MPEG4 AAC MP3 WMA AMR

Audio Audio DAC DAC Camera module

Camera High speed I/F serial bus

DSP Dynastron

LCD module

LCDC High speed serial bus

LCDD

Back Light

NAND, MCP

Memory Module (NAND)

Memory Card-I/F (Security)

LCD

SD, mini SD Hard Disk

ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Block Diagram B.B. LSI

RF

Audio DA/AD

Audio I/F

Sub LCD Main LCD

System Clock Input

DBUS SIO I2C

BUSIF

I2C I2C (2port)

SDHC NAND GPIO (CPRM) Cont.

IO Bus S W I T C H

NTSC Encoder LVDS Panel

Memory

S W I T C H

LVDSL I/F LPLL DPLL (System) DPLL (Audio)

ASP-DAC 2007 YOKOHAMA

Indirect Bus MPG-MeP LCDC @DSP + VA

GMM-MeP 2D/3D

JPEG Cont.

Scaler

Memory Bus

Camera I/F LVDSC I/F

DRAM Controller TS I/F

eDRAM ( 16Mbit + 4Mbit ) Jan. 25, 2007

Psedo Sync.

Camera 1 Camera 2 LVDS Camera DTV Tuner 27MHz 4

ISDB-T 1-seg Data Flow RF

Audio DA/AD

B.B. ⑤ Memory LSI Output of Audio data Audio I/F

Sub LCD Main LCD NTSC Encoder LVDS Panel System Clock Input

DBUS SIO I2C

BUSIF

IO Bus S W I T C H

S W I T C H

LVDSL I/F LPLL DPLL (System) DPLL (Audio)

④ Scaling for display

③ H.264 & Audio decoding

I2C I2C (2port)

SDHC ② NAND GPIO (CPRM) Cont. De-multiplexing

of TS packet

Indirect Bus MPG-MeP LCDC @DSP + VA

GMM-MeP 2D/3D

JPEG Cont.

Scaler

① Camera Camera TS Packet 1 I/F Receiving &Camera Buffering 2

Memory Bus

LVDSC I/F

DRAM Controller

⑤ Output of Video data

ASP-DAC 2007 YOKOHAMA

TS I/F

eDRAM ( 16Mbit + 4Mbit ) Jan. 25, 2007

Psedo Sync.

LVDS Camera DTV Tuner 27MHz 5

S1G Floor plan and Chip specification „ Technology Toshiba 90nm CMOS 5 layer metal Multi-Vth Embedded DRAM „ Package 289pin TFBGA „ Logic Gate 2.7MGate „ Memory SRAM 1.3Mbit eDRAM 20Mbit „ Supply Voltage 1.2V Core 2.5V eDRAM 1.8V/3.0V IO „ Operation Frequency 162MHz ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Evaluation Environment Power is measured by this environment. Not simulation

42mW ISDB-T 1-seg S1G PCI Board Host CPU (PC)

ISDB-T Receiving picture

UHF input

Control of ISDB-T Tuner Module by PC application ASP-DAC 2007 YOKOHAMA

TS IF

I2C

ISDB-T Tuner Module Jan. 25, 2007

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Core Power [mW]

Power Comparison 180 160 140 120 100 80 60 40 20 0

MPEG4 Decode operation (Condition: QVGA, 15fps, 384kbps)

Hardware Solution Software Solution

Product A (130nm) ASP-DAC 2007 YOKOHAMA

Product B (90nm) Jan. 25, 2007

S1G (90nm) 8

Breakdown of Power Consumption

Total Power

Applied techniques for Low Power in S1G 90nm technology

Data Path

Low operation frequency

+ IDLE Power Clock Tree

Module level clock gating Clock gating by S/W control H/W Clock gating by Tool

+ Leak ASP-DAC 2007 YOKOHAMA

Multi-Vth Technique Jan. 25, 2007

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Multi-Vth Technique for Low Leak Design Met

(a)

(b)

(c)

Path delay

First achievement

HS ratio becomes low but timing violation occurs

LP cells in violation paths replaced to HS cells again

25℃ 85℃ LP: Low Power LP LP ratio Leak Power ⊿ Leak Leak Power ⊿ Leak transistor (High Vth) Replacement [%]

HS: High Speed transistor (Low Vth) ASP-DAC 2007 YOKOHAMA

Before After

51.0 75.3 Jan. 25, 2007

[mW] 1.99 1.39

[mW] 0.59

[mW] 13.44 8.65

[mW] 4.79 10

Clock Hierarchy in S1G MeP

MeP

ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Relation between Gate counts and IDLE power

IDLE (offset) power is proportional to module gate counts

0.036mW/KGate

0.024mW/KGate

Clock gating by Power Compiler

Additional Clock gating makes further low power

ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Software architecture Host CPU

Tuner

Pre-processing Non routine task Syntax analysis etc Routine task Signal processing Composition by H/W ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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H.264 Decoder in MPG module Pipeline

MPG-MeP Syntax Analysis

MeP Local Data Memory

@DSP Signal Processing

Frame Memory

Load balance Peak MIPS

Peak MIPS

Simultaneous Operation ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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MeP User Custom Instruction User can define and implement UCI to reduce operation MIPS of target application

From profiling result of H.264 decoder, 1)Table search, 2)Bit manipulation etc… 10 kinds of UCIs are implemented

10% MIPS Reduction ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Summary of Application Power Application

ISDB-T 1-Seg. H.264 Decode MPEG4 Encode MPEG4 Decode AAC Decode

Mode

Video Condition Frame Size Rate [pxl*pxl] [fps]

Audio Condition Core Bit Sampling Bit Power Rate Mode Frequency Rate [mW] [Kbps] [KHz] [Kbps] AAC+SBR 214 48 32 42 Stereo AAC 384 44.1 32 49 Stereo

H.264

320x180

15

H.264

320x240

15

MPEG4 320x240

15

384

AMR-NB

8

12.2

63

MPEG4 320x240

15

384

-

-

-

45

-

-

AAC Stereo

48

128

13

-

ASP-DAC 2007 YOKOHAMA

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Jan. 25, 2007

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Relation between MIPS and Power Core Power vs Operation MIPS 130 120

Audio+Video

Product A

110

P = DataPath + IDLE

100

Core Power [mW]

90

S1G

80 70 IDLE state of H/W accelerator

60 50 40

⊿37mW

30

Audio

Sleep 20 State 10

MPEG4 Enc Operated at 162MHz

Audio + Video Video

H.264 Dec MPEG4 Dec

ISDB-T 1-seg.

P: Total Core Power DataPath: Actual operation power (Frequency x Slope) IDLE: IDLE Power (Sysclk is provided)

AAC Dec

0 0

20

40

60

80

100 120 140 160 180

Operation MIPS ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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Summary „ Multi-Vth technique is effective for low leak design „ Additional clock gating by sleep instruction of MeP processor realizes lower IDLE power „ RUN and IDLE control in fine grain by S/W is effective for low power operation „ Good load balance between processors leads low operation frequency We have accomplished low power ISDB-T One-segment in 42mW. ASP-DAC 2007 YOKOHAMA

Jan. 25, 2007

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