Design of Digital Systems II Combinational Logic Design Practices (2)
Moslem Amiri, V´aclav Pˇrenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic
[email protected] [email protected]
November, 2012
through 2n−1. Sometimes an n-bit binary code is truncated to repr than 2n values. For example, in the BCD code, the 4-bit combin through 1001 represent the decimal digits 0–9, and combinations 10 A decoder is1111 a multiple-input, are not used. multiple-output logic circuit that converts coded inputs intocommonly coded outputs, where input outputcode, wh The most used output code is a and 1-out-of-m codes are different bits, where one bit is asserted at any time. Thus, in a 1-out-ofm Input code generally has fewer bits than output code active-high outputs, the code words are 0001, 0010, 0100, and There is a one-to-one mapping from input code words into output code active-low outputs, the code words are 1110, 1101, 1011, and 0111. words
Decoders
DO NOT C DO NOT C DO NOT C DO NOT C
In a one-to-one mapping, each input code word produces a different output code word Decoder
input code word
Figure 5-31 Decoder circuit struc
ma p
output code word
enable inputs
Figure 1: Decoder circuit structure. Copyright © 1999 by John F. Wakerly Moslem Amiri, V´ aclav Pˇrenosil
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Decoders Enable inputs must be asserted for decoder to perform its normal mapping function Otherwise, it maps all input code words into a single, ”disabled,” output code word
Most commonly used input code is an n-bit binary code An n-bit word represents one of 2n different coded values
Most commonly used output code is a 1-out-of-m code m bits where one bit is asserted at any time
Moslem Amiri, V´ aclav Pˇrenosil
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O NOT COPY O NOT COPY O NOT COPY O NOT COPY
for some combination of the remaining inputs, they are marked with an “x” for Decoders: Binary Decoders that input combination. This convention can greatly reduce the number of rows in the truth table, as well as make the functions of the inputs more clear.
n decoder Binary decoder is code an n-to-2 The input of an n-bit binary decoder need not represent the integers
n 3-bit Gray-code output from 0 through −1. Forinput example, shows the output code It has an n-bit2nbinary code Table and a5-5 1-out-of-2
I0′ I0 I1′ I1 EN
I0
2 der: outputs; am.
Y0
2-to-4 decoder
I0 I1
Y1
I1
Y0 Y1 Y2 Y3
EN
Y2
Y3
EN
(a)
(b)
Figure 2: A 2-to-4 decoder: (a) inputs and outputs; (b) logic diagram. Copyright © 1999 by John F. Wakerly
Moslem Amiri, V´ aclav Pˇrenosil
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Decoders: Binary Decoders Table 1: Truth table for a 2-to-4 binary decoder.
Inputs EN 0 1 1 1 1
I1 x 0 0 1 1
Outputs I0 x 0 1 0 1
Y3 0 0 0 0 1
Y2 0 0 0 1 0
Y1 0 0 1 0 0
Y0 0 1 0 0 0
Input code of an n-bit binary decoder need not represent integers from 0 through 2n − 1 E.g., it can be in Gray code (appropriately assign inputs to outputs)
It is not necessary to use all of outputs of a decoder, or even to decode all possible input combinations E.g., a BCD decoder decodes only first ten binary input combinations 0000-1001 to produce outputs Y0-Y9 Moslem Amiri, V´ aclav Pˇrenosil
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Decoders: The 74x139 Dual 2-to-4 Decoder 74x139 is a single MSI part containing two independent and identical 2-to-4 decoders
Moslem Amiri, V´ aclav Pˇrenosil
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
74x139 dual 2-to-4 decoder: (a) logic diagram, including pin FigureThe 5-35 The Decoders: 74x139 Dual 2-to-4 Decoder numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol; (c) logic symbol for one decoder. (4)
1G_L
1Y0_L
(1)
74x139
1
(5)
1Y1_L
1G
2 3
(6)
1A
(7)
1B
(a)
(3)
(12)
2G_L
1Y2_L
15
(2)
1Y0 1Y1 1Y2 1Y3
1A 1B
2G
2Y0 2Y1 2Y2 2Y3
14
1Y3_L
2A 13 2B
6 7
12 11 10 9
(b)
2Y0_L
2Y1_L
1/2 74x139
G
(10)
2Y2_L
(14)
(9)
2B
5
(15)
(11)
2A
4
(13)
2Y3_L
Y0 Y1 Y2 Y3
A B
(c)
© 1999 bydual John F.2-to-4 Wakerly decoder: (a) logic Copying Prohibited including pin Figure 3:Copyright The 74x139 diagram, numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol; (c) logic symbol for one decoder. Moslem Amiri, V´ aclav Pˇrenosil
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Decoders: The 74x139 Dual 2-to-4 Decoder Outputs and enable input of ’139 are active-low Inverting gates are generally faster than noninverting ones
’139 has extra inverters on its select inputs Without these inverters, each select input would present three AC or DC loads instead of one, consuming much more of fanout budget of device that drives it Table 2: Truth table for one-half of a 74x139 dual 2-to-4 decoder.
Inputs GL 1 0 0 0 0 Moslem Amiri, V´ aclav Pˇrenosil
B x 0 0 1 1
Outputs A x 0 1 0 1
Y3 L 1 1 1 1 0
Y2 L 1 1 1 0 1
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Decoders: The 74x138 3-to-8 Decoder Section 5.4
Decoders
321
DO NOT COPY DO NOT COPY DO NOT NOT COPY COPY DO DO NOT COPY DO NOT COPY DO NOT NOT COPY COPY DO (a)
(15)
Y0_L
(b)
74x138
6
(14)
G1
G2A_L G2B_L
(6)
(13)
(12)
(5)
(11) (15)
(10) (14)
(1)
(9) (13)
(6)
G1 (2) B
G2A_L
Y1_L
5
Y3_L
(7) (12)
(3)
Y4 Y5 Y6 Y7
(b)
74x138
Y5_L Y1_L
Y6_L Y2_L
Y7_L Y3_L
Y3
2
Decoders
Y4_L Y0_L
Y0 Y1 Y2
1
Section 5.4
(4)
C (5) G2B_L
G1 G2A G2B
A B 3 C
Y2_L
(4)
(a)
A
4
15 14 13
12 11 10 9
7
321
15 Figure 5-37 Y0 6 G1 14 The 74x138 3-to-8 Y1 4 G2A decoder: (a)Y2logic13 5 G2B including 12 pin diagram, Y3 11 numbers for a Y4 1 A 10 standard 16-pin Y5 dual 2 B package; 9 in-line Y6 3 C 7 (b) traditional logic Y7 symbol.
Figure 4: The 74x138 3-to-8 decoder: (a) logic diagram, including pin numbers (11) Y4_L 74x138 for a standard 16-pin dual in-line package; (b) traditional logic symbol. +5V Moslem Amiri, V´ aclav Pˇrenosil
R of Digital Systems II 15 Design Y0 6
DEC0_L
Figure5-37 5-38 Figure
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Decoders: The 74x138 3-to-8 Decoder Table 3: Truth table for a 74x138 3-to-8 decoder. Inputs G1 0 x x 1 1 1 1 1 1 1 1
G2A L x 1 x 0 0 0 0 0 0 0 0
G2B L x x 1 0 0 0 0 0 0 0 0
Moslem Amiri, V´ aclav Pˇrenosil
Outputs C x x x 0 0 0 0 1 1 1 1
B x x x 0 0 1 1 0 0 1 1
A x x x 0 1 0 1 0 1 0 1
Y7 L 1 1 1 1 1 1 1 1 1 1 0
Y6 L 1 1 1 1 1 1 1 1 1 0 1
Y5 L 1 1 1 1 1 1 1 1 0 1 1
Design of Digital Systems II
Y4 L 1 1 1 1 1 1 1 0 1 1 1
Y3 L 1 1 1 1 1 1 0 1 1 1 1
Y2 L 1 1 1 1 1 0 1 1 1 1 1
Y1 L 1 1 1 1 0 1 1 1 1 1 1
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY B
Y6_L
(2)
Decoders: Cascading Binary Decoders C
(7)
(3)
Y7_L
standard 16-pin dual in-line package; (b) traditional logic symbol.
Multiple binary decoders can be used to decode larger code words 74x138
+5V
R
6
4 5
1
N0 N1 N2 N3
2 3
G1 G2A G2B
Y0 Y1 Y2 Y3
A B
Y4 Y5 Y6
C
Y7
EN_L
15 14 13 12 11 10 9 7
DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L
Figure 5-38 Design of a 4-to-16 decoder using 74x138s.
U1
74x138
6
4 5
1
G1 G2A G2B
A B 3 C 2
Y0 Y1 Y2 Y3
Y4 Y5 Y6 Y7
15 14 13 12 11 10 9 7
DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L
U2
Figure Design Copyright © 1999 by John5:F. Wakerly Moslem Amiri, V´ aclav Pˇrenosil
of a 4-to-16 decoder 74x138s. Copyingusing Prohibited Design of Digital Systems II
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Decoders: Cascading Binary Decoders To handle larger code words, binary decoders can be cascaded hierarchically
Moslem Amiri, V´ aclav Pˇrenosil
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Decoders: Cascading Binary Decoders 322
Chapter 5
Combinational Logic Design Practices
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY 74x138
6
4 5
G2B
1
N0 N1 N2
G1 G2A
2 3
Y0 Y1 Y2 Y3
Y4
A B C
Y5 Y6 Y7
15 14 13
12 11 10 9
7
DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L
U2 74x138
6
4 5
G2B
1
2
1/2 74x139
EN3_L N3 N4
1
2 3
1G
1Y0 1Y1
1A 1B
1Y2 1Y3
4
5 6 7
3
EN0X7_L EN8X15_L
G1 G2A
U1
Y2 Y3
Y4
A
Y5 Y6 Y7
B C
EN16X23_L EN24X31_L
Y0 Y1
15 14 13 12 11 10 9 7
DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L
U3 74x138
6
4 5
G2B
1
2
EN1 EN2_L
G1 G2A
3
Y0 Y1 Y2 Y3
Y4
A B
Y5 Y6 Y7
C
15 14 13 12 11 10 9 7
DEC16_L DEC17_L DEC18_L DEC19_L DEC20_L DEC21_L DEC22_L DEC23_L
U4 74x138
6
4 5
G1 G2A G2B
1
A 2 B 3 C
Y0 Y1 Y2 Y3
Y4 Y5 Y6 Y7
15 14 13 12 11 10 9 7
DEC24_L DEC25_L DEC26_L DEC27_L DEC28_L DEC29_L DEC30_L DEC31_L
U5
Figure 5-39 Design of a 5-to-32 decoder using 74x138s and a 74x139.
Figure 6: Design of a 5-to-32 decoder using 74x138s and a 74x139. Moslem Amiri, V´ aclav Pˇrenosil
Copyright © 1999Design by John F.of Wakerly Digital
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
5.4.1 Binary Decoders Decoders in Verilog The most common decoder circuit is an n-to-2 decoder or binary decoder. Such binary decoder n
Table 4:
enable input decode
a decoder has an n-bit binary input code and a 1-out-of-2n output code. A binary decoder is used when you need to activate exactly of 2ndecoder outputs based an Structural-style Verilog module foronethe inonFig. n-bit input value. For example, Figure 5-32(a) shows the inputs and outputs and Table 5-4 is the truth table of a 2-to-4 decoder. The input code word 1,I0 represents an integer in the range 0–3. The output code word Y3,Y2,Y1,Y0 has Yi equal to 1 if and only if the input code word is the binary representation of i and the enable input EN is 1. If EN is 0, then all of the outputs are 0. A gate-level circuit for the 2-to-4 decoder is shown in Figure 5-32(b). Each AND gate decodes one combination of the input code word I1,I0. The binary decoder’s truth table introduces a “don’t-care” notation for input combinations. If one or more input values do not affect the output values for some combination of the remaining inputs, they are marked with an “x” for that input combination. This convention can greatly reduce the number of rows in the truth table, as well as make the functions of the inputs more clear. The input code of an n-bit binary decoder need not represent the integers from 0 through 2n−1. For example, Table 5-5 shows the 3-bit Gray-code output
2.
I0′ I0 I1′ I1 EN
I0
Figure 5-32 A 2-to-4 decoder: (a) inputs and outputs; (b) logic diagram.
Y0
2-to-4 decoder
I0 I1
Y1
I1
Y0 Y1 Y2 Y3
EN
Y2
Y3
EN
(a)
Moslem Amiri, V´ aclav Pˇrenosil
(b)
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Decoders in Verilog Table 5: Functional-style Verilog module for a 74x138-like 3-to-8 binary decoder.
Section 5.4
Decoders
321
DO NOT COPY DO NOT COPY DO NOT COPY (a)
(15)
74x138
Y0_L
6
(14)
G1
G2A_L G2B_L
(6)
(13)
(4)
(12)
(5)
(10)
(1)
Y1_L
5
1
Y2_L
2 3
(11)
Moslem Amiri, V´ aclav Pˇrenosil
4
Design of Digital Systems II
Y3_L
G1 G2A G2B A
B C
Y0 Y1 Y2 Y3
Y4 Y5 Y6 Y7
15 14 13
12 11 10 9
7
Y4_L
Figure 5-37 The 74x138 3-to-8 2012 (a) logic 15 / 69 decoder:
Y5_L November,
Decoders in Verilog In Tab. 5 Constants and inversions that handle the fact that two inputs and all outputs are active low are scattered throughout the code While its true that most Verilog programs are written almost entirely with active-high signals, if we are defining a device with active-low external pins, we should handle them in a more systematic and easily maintainable way
Tab. 6 Decoder function is defined in terms of only active-high signals The design can be easily modified in just a few well-defined places if changes are required in external active levels
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Decoders in Verilog Table 6: Verilog module with a maintainable approach to active-level handling.
Section 5.4
Decoders
321
DO NOT COPY DO NOT COPY (a)
(15)
74x138
Y0_L
6
(14)
G1
G2A_L G2B_L
Moslem Amiri, V´ aclav Pˇrenosil
(6)
(13)
(4)
(12)
(5)
Design of Digital Systems II
(11)
4
Y1_L
Y2_L
5
1
2
G1 G2A G2B A
B 3 C
Y3_L
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Y4 Y5 Y6 Y7
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12 11 10 9
7
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Decoders in Verilog Table 7: Hierarchical definition of 74x138-like decoder with active-level handling.
Moslem Amiri, V´ aclav Pˇrenosil
Table 8: Verilog functional definition of an active-high 3-to-8 decoder.
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Decoders in Verilog
Figure 7: Verilog module 74x138c: (a) top level; (b) internal structure using module Vr3to8deca.
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Decoders in Verilog Table 9: Behavioral Verilog definition for a 3-to-8 decoder.
Moslem Amiri, V´ aclav Pˇrenosil
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seven-segment decoder
A seven-segment decoder has 4-bit BCD as its input code and the “seven-
DO NOT COPY DO NOT COPY DO NOT COPY
segment code,” which isDecoders graphically depicted in Figure 5-43(b), as its output Decoders: Seven-Segment code. Figure 5-44 and Table 5-20 are the logic diagram truth table and for a 74x49 seven-segment decoder. Except for the strange (clever?) connection of the of the is a minimal product-of-sums “blanking input” BI_L seven-segment decoder has, each 4-bitoutput BCD as 74x49 its input code and
74x49
A ”seven-segment code” as its output code
Figure 5-43 Seven-segment display: (a) segment identification; (b) decimal digits.
a
f
g
e
b
c
d
(a)
(b)
Copyright ©display: 1999 by John F. Wakerly identification; (b) Copying Figure 8: Seven-segment (a) segment decimalProhibited digits.
Moslem Amiri, V´ aclav Pˇrenosil
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Decoders: Seven-Segment Decoders Section 5.4
Decoders
333
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Figure 9: The 74x49 seven-segment decoder: (a) logic diagram, including pin (a)
(11)
(10)
(b)
a
b
74x49
3
11
BI
5
1 2 4
a 10 b 9
A
c
B C
d 6 e
D
f
8
g
(9)
13
(8)
BI_L
C
(1)
f
(2)
(12)
D
e
(5)
(13)
B
d
(3)
(6)
A
c
12
g
(4)
Figure 5-44 The 74x49 seven-segment decoder: (a) logic diagram, including pin numbers; (b) traditional logic symbol.
Copyright © 1999 by John F. Wakerly
numbers; (b) traditional logic symbol. Moslem Amiri, V´ aclav Pˇrenosil
Copying Prohibited
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Decoders: Seven-Segment Decoders Table 10: Truth table for a 74x49 seven-segment decoder. Inputs BI L 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Moslem Amiri, V´ aclav Pˇrenosil
D x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
C x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Outputs B x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
a 0 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0
b 0 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0
c 0 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0
Design of Digital Systems II
d 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0
e 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0
f 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0
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Decoders: Seven-Segment Decoders Each output of 74x49 is a minimal POS realization for corresponding segment, assuming don’t-cares for non-decimal input combinations INVERT-OR-AND structure used for each output is equivalent to an AND-OR-INVERT gate, which is a fast and compact structure to build in CMOS or TTL Modern seven-segment display elements have decoders built into them A 4-bit BCD word can be applied directly to device
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Decoders: Seven-Segment Decoders Table 11: Verilog program for a seven-segment decoder.
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Y1 = I2 + I3 + I6 + I7
Encoders
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Y2 = I4 + I5 + I6 + I7
n
The corresponding logic circuit is shown (b). Ininput general, a 2 -to-n can If a device’s output code has fewer bitsinthan code, it is encoder called an be built from n 2 n−1-input OR gates. Bit i of the input code is connected to OR encoder gate j if bit j in the binary representation of i is 1. Simplest encoder to build is a 2n -to-n or binary encoder
Its input code is 1-out-of-2n code and its output code is n-bit binary Binary encoder
Y0
I0
2n inputs
I1
Y0 Y1
I0 I1 I2
I2 I3
n outputs
I4
Yn–1
n–1
I2
(a)
Y1
(b)
I5 I6 I7
Y2
Figure 10: Binary encoder: (a) general structure; (b) 8-to-3 encoder.
5.5.1 Priority Encoders Y outputs 0 = I 1 of +an I 3n-bit + I 5binary + I 7 decoder are generally used to The 1-out-of-2 n coded control a set of 2 n devices, Y 1 =where I 2 +atI 3most + I one 6 +device I 7 is supposed to be active at n any time. Conversely,Yconsider a system with 2 2 = I 4 + I 5 + I 6 + I 7inputs, each of which indicates a request for service, as in Design Figure 5-46.Systems This IIstructure is often found in microMoslem Amiri, V´ aclav Pˇrenosil of Digital November, 2012 26 / 69
Encoders: Priority Encoders Consider a system with 2n inputs, each of which indicates a request for service
This structure is often found in microprocessor input/output subsystems where inputs might be interrupt requests Binary encoder works properly only if inputs are guaranteed to be asserted at most one at a time If multiple requests can be made simultaneously, the encoder gives5.5 Encod Section undesirable results
DO NOT COP DO NOT COP DO NOT COP Request encoder
Requests for service
REQ1 REQ2 REQ3
REQN
Requestor's number
Figure 5-46 A system with 2n requestors, and encoder” that ind which request si asserted at any
Figure 11: A system with 2n requestors, and a ”request encoder” that indicates simultaneously, the encoder gives undesirable results. For example, suppose that which signal is asserted at any time. I2 and I4 of the 8-to-3 encoder are both 1; then the output is 110, the inputsrequest Moslem Amiri, V´ aclav Pˇrenosil
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T COPY T COPY T COPY T COPY T COPY
stor. Such a device is called a
Encoders: Priority Encoders priority encoder
oder is shown in Figure 5-47. 0 contain number of the We the assign priority to input lines, so that when multiple requests are output asserted, is assertedencoder if no inputs produces the number of the highest-priority
requestor
ity encoder’s outputs, we first Such a device is called priority encoder hat Hi is 1 if and only if Ii is the Priority encoder
I7
I6
I5 I4 I3 I2
5′ ⋅ I6′ ⋅ I7′
outputs are similar to the ones
H7
H7
A2 A1 A0
IDLE
I1 I0
Figure 12: Logic symbol for a generic Figure 5-47 8-input priority encoder.
H7 Moslem Amiri, V´ aclav Pˇrenosil
Logic symbol for a generic 8-input Design ofencoder. Digital Systems II priority
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Encoders: Priority Encoders Logic equations for priority encoder’s outputs (Fig. 12) Input I 7 has the highest priority Outputs A2–A0 contain number of the highest-priority asserted input IDLE is asserted if no inputs are asserted First we define eight intermediate variables H0–H7 Using H0–H7, equations for A2–A0 are similar to ones for a binary encoder H7 = I 7 H6 = I 6 · I 70 H5 = I 5 · I 60 · I 70 .. . H0 = I 0 · I 10 · I 20 · I 30 · I 40 · I 50 · I 60 · I 70 A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7 IDLE = I 00 · I 10 · I 20 · I 30 · I 40 · I 50 · I 60 · I 70 Moslem Amiri, V´ aclav Pˇrenosil
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DO NOT DO NOT DO NOT DO NOT DO NOT
74x148
The 74x148 is a commercially
Encoders: The 74x148 Priority Encoder symbol is shown in Figure 5-4
main difference between th Figure 5-47 is that its inputs a 74x148 is an MSI 8-input priority encoder input, EI_L, that must be ass 74x148 complete truth table is given i 5 EI Instead of an IDLE outpu 4 I7 the device is enabled and on 3 6 A2 I6 manufacturer calls this “Gro 2 7 I5 A1 EO_L signa Something.” The 1 9 I4 A0 EI_L input of another ’1 the 13 I3 12 14 EI_L asserted if is asserted but I2 GS 11 15 ’148 may be enabled. I1 EO 10 Figure 5-50 shows how I0 accept 32 request inputs and Figure 5-48 highest-priority requestor. Sin Figure 13: Logic symbol forsymbol the 74x148 priority encoder. Logic for 8-input enabled at any time, the outpu the 74x148 8-input RA2–RA0. Likewise, the indiv priority encoder. encoder to produce RA4 and R is asserted.
Ta b l e 5 - 2 2 Truth table
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Encoders: The 74x148 Priority Encoder Section 5.5
Encoders
339
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DOfor theNOT COPY Figure 14: Logic diagram 74x148 8-input priority encoder, including pin I0_L
(10)
(15)
I1_L
I2_L
(14)
I4_L
I5_L
I6_L
I7_L
EI_L
GS_L
(12)
(9)
I3_L
EO_L
(11)
A0_L
(13)
(1)
(7)
(2)
A1_L
(3)
(4)
(6)
A2_L
(5)
Figure 5-49 Logic diagram for the 74x148 8-input priority encoder, including pin numbers for a standard 16-pin dual in-line package.
numbers for a standard 16-pin dual in-line package. Copyright © 1999 by John F. Wakerly
Moslem Amiri, V´ aclav Pˇrenosil
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Encoders: The 74x148 Priority Encoder Table 12: Truth table for a 74x148 8-input priority encoder. Inputs EI L 1 0 0 0 0 0 0 0 0 0
I0 L x x x x x x x x 0 1
I1 L x x x x x x x 0 1 1
I2 L x x x x x x 0 1 1 1
Moslem Amiri, V´ aclav Pˇrenosil
I3 L x x x x x 0 1 1 1 1
Outputs I4 L x x x x 0 1 1 1 1 1
I5 L x x x 0 1 1 1 1 1 1
I6 L x x 0 1 1 1 1 1 1 1
I7 L x 0 1 1 1 1 1 1 1 1
Design of Digital Systems II
A2 L 1 0 0 0 0 1 1 1 1 1
A1 L 1 0 0 1 1 0 0 1 1 1
A0 L 1 0 1 0 1 0 1 0 1 1
GS L 1 0 0 0 0 0 0 0 0 1
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Encoders: The 74x148 Priority Encoder Instead of an IDLE output, ’148 has a GS L (Group Select) output It is asserted when device is enabled and one or more of request inputs are asserted
EO L signal is an enable output used for cascading It is designed to be connected to EI L input of another ’148 that handles lower-priority requests EO L is asserted if EI L is asserted but no request input is asserted; thus, a low-priority ’148 may be enabled
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Encoders: The 74x148 Priority Encoder 340
Chapter 5
Combinational Logic Design Practices
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY 74x148
5
REQ31_L REQ30_L REQ29_L REQ28_L REQ27_L REQ26_L REQ25_L REQ24_L
4 3 2 1
13 12 11 10
EI I7
I6
A2 A1
I5 I4
A0
I3 I2
GS EO
I1
6
G3A2_L
7 9
G3A1_L G3A0_L
14
G3GS_L
15
I0
U1
G3EO_L
74x148
5
REQ23_L REQ22_L REQ21_L REQ20_L REQ19_L REQ18_L REQ17_L REQ16_L
4 3 2 1
13 12 11 10
EI I7
I6
A2
I5 I4 I3
A1 A0
I2 I1 I0
GS EO
7
G2A2_L G2A1_L
9
G2A0_L
14
G2GS_L
6
1
4
REQ15_L REQ14_L REQ13_L REQ12_L REQ11_L REQ10_L REQ9_L REQ8_L
4 3 2 1
13 12 11 10
I6
A2 A1 A0
I5 I4 I3 I2 I1
GS EO
6 7 9
14
G1A2_L G1A1_L G1A0_L
G1GS_L
15
4 3 2 1
13 12 11 10
RA3
I5 I4 I3 I2 I1 I0
74x20
2
6
4 5
9
74x20
8
13
1
GS EO
9
G0A2_L G0A1_L G0A0_L
14
G0GS_L
6 7
15
74x20
6
4 5
9
10 12 13
RA1
U6
2
A2 A1 A0
RA2
U6
12
U3
EI I7
I6
1
10
I0
74x148
5
6
U5
EI I7
G1EO_L
REQ7_L REQ6_L REQ5_L REQ4_L REQ3_L REQ2_L REQ1_L REQ0_L
RA4
74x00
5
74x148
5
3
U5
U2
G2EO_L
74x00
2
15
RA0
U7
74x20
8
RGS
U7
U4
Figure 5-50 Four 74x148s cascaded to handle 32 requests.
Figure 15: Four 74x148s cascaded to handle 32 requests. Copyright © 1999 by John F. Wakerly
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Encoders: The 74x148 Priority Encoder In Fig. 15 There are 32 request inputs and a 5-bit output, RA4–RA0, indicating the highest-priority requestor Since A2–A0 outputs of at most one ’148 will be enabled at any time, outputs of individual ’148s can be ORed to produce RA2–RA0 Individual GS L outputs can be combined in a 4-to-2 encoder to produce RA4 and RA3 RGS output is asserted if any GS output is asserted
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Encoders in Verilog Table 13: Behavioral Verilog module for a 74x148-like 8-input priority encoder.
338
Chapter 5
Combinat
DO N DO N DO N DO N
5.5. The sym mai Figu inpu com
74x148
74x148
5 4 3 2 1 13 12 11 10
Moslem Amiri, V´ aclav Pˇrenosil
Design of Digital Systems II
EI I7
I6 I5 I4 I3 I2 I1 I0
A2 A1 A0
GS
EO
6 7 9
14 15
the man Som the asse ’148
acce Figure 5-48 high Logic symbol for enab the 74x148 8-input RA2 priority November, 2012encoder. 36 / 69 enco
value on SDATA is undefined in this case.
Three-State Devices: Three-State Buffers
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
Figure 5-52 Various three-state buffers: (a) noninverting, active-high enable; non-inverting, active-low enable; (c) inverting, active-high The most(b)basic three-state device is a three-state buffer, often enable; (d) inverting, active-low enable. three-state driver
(a)
(b)
(c)
called a
(d)
Figure 16: Various three-state buffers: (a) non-inverting, active-high enable; (b) non-inverting, active-low enable; (c) inverting, active-high enable; (d) The enable. actual voltage level of a floating signal depends on circuit details, s DEFINING inverting, active-low “UNDEFINED”
resistive and capacitive load, and may vary over time. Also, the interpretation level by other circuits depends on the input characteristics of those circuits, When enable input behaves like an anything ordinaryother buffer best is notasserted, to count ondevice a floating signal as being than “unde or inverter Sometimes a pull-up resistor is used on three-state party lines to ensure that a f valueisis negated, pulled to a HIGH voltage and interpreted When enable input device output floats as logic 1. This is especially tant on party lines that drive CMOS devices, which may consume excessive It goes to a when high-impedance (Hi-Z), disconnected state0 and their input voltage is halfway between logic and 1.functionally
behaves as if it were not even there
Three-state devices allow multiple sources to share a single ”party Copying Prohibited line,” as long as only one device talks on the line at a time
Copyright © 1999 by John F. Wakerly Moslem Amiri, V´ aclav Pˇrenosil
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Three-State Devices: Three-State Buffers
6
Chapter 5
Combinational Logic Design Practices
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
1-bit party line
P
Q
74x138
EN1 5 /EN2 4 /EN3
SSRC0 SSRC1 SSRC2
6
1
2 3
G1 G2A G2B
Y0 Y1 Y2 Y3
A B C
Y4 Y5 Y6 Y7
15 14 13 12 11 10 9 7
/SELP /SELQ /SELR /SELS /SELT /SELU /SELV /SELW
R
SDATA
S
T
U
V
W
Figure 17: three-state Eight sources sharing a so three-state party line.state Typical devices are designed that they go into the Hi-Z faster than Moslem Amiri, V´ aclav Pˇrenosil
they come out Design of the of Hi-Z state. (In terms of the specifications a Digital Systems II November,in2012
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Three-State Devices: Three-State Buffers Three-state devices are designed so that they go into Hi-Z state faster than they come out of Hi-Z state tpLZ and tpHZ are both less than tpZL and tpZH If outputs of two three-state devices are connected to same party line, and we simultaneously disable one and enable other, the first device will get off party line before the second one gets on If both devices were to drive party line at same time, and if both were trying to maintain opposite output values (0 and 1), then excessive current would flow and create noise in system (fighting)
Delays and timing skews in control circuits make it difficult to ensure that enable inputs of different three-state devices change simultaneously Even when this is possible, a problem arises if three-state devices from different-speed logic families are connected to same party line tpZL or tpZH of a fast device may be shorter than tpLZ or tpHZ of a slow one
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Three-State Devices: Three-State Buffers The only safe way to use three-state devices is to design control logic that guarantees a dead time on party line during which no one is driving it
Dead time must be long enough to account for worst-case differences between turn-off and turn-on times of devices and for skews in Section 5.6 Three-State Devic three-state control signals
DO NOT COPY DO NOT COPY DO NOT COPY SSRC[20]
7
0
1
2
3
EN1
/EN2, /EN3 SDATA
W
P
Q
R
S
min(tpZLmin, tpZHmin)
max(tpLZmax, tpHZmax)
dead time
Figure 5-5 Timing diagra three-state p
Figure 18: Timing diagram for the three-state party line of Fig. 17.
The dead time must be long enough to account for the worst-case differences between turn-off turn-on times of Design the devices forIIskews in the three-state Moslem Amiri, V´ aclavand Pˇrenosil of Digitaland Systems November, 2012
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DO NOT COP DO NOT COP DO NOT COP
time. Independent enable inputs, as in the ’125 and ’126, are not necessary. Three-State Devices: SSI and MSI Three-State Buffers Thus, to reduce the package size in wide-bus applications, most commonly
used MSI parts contain multiple three-state buffers with common enable inputs.
For example, Figure showscontains the logic four diagram and symbolnon-inverting for a 74x541 Each of 74x125 and5-56 74x126 independent octal noninverting buffer. Octal means that the part contains eight three-state buffersthree-state in a 14-pin package (1) (2)
(13)
(3)
(12)
(1) (2)
(11)
74x125
(13)
(3)
(12)
(11)
74x126
(4) (5)
(10)
(6)
(9)
(4)
(8)
(5)
74x54
(10)
(6)
(9)
Figu Pinou and 7 state
(8)
Figure©19: Pinouts 74x125 and 74x126 three-state buffers. Copyright 1999 by JohnofF.the Wakerly Copying Prohibited
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Three-State Devices: SSI and MSI Three-State Buffers Most party-line applications use a bus with more than one bit of data E.g., in an 8-bit microprocessor system, data bus is eight bits wide, and peripheral devices place data on bus eight bits at a time A peripheral device enables eight three-state drivers to drive bus, all at the same time
To reduce package size in wide-bus applications, MSI parts contain multiple three-state buffers with common enable inputs
Moslem Amiri, V´ aclav Pˇrenosil
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Three-State Devices: SSI and MSI Three-State Buffers Chapter 5 Combinational Logic Design Practices
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY 74x541
1
G1_L
G1 G2
19
2
3
A1 A2
4
A3 5 A4 6
A5 7 A6 8 A7 9
A8
G2_L
18
Y1 17 Y2 16 Y3
Y4
A1
15
A2
(1)
(19)
(2)
(18)
(3)
(17)
(4)
(16)
(5)
(15)
(6)
(14)
(7)
(13)
(8)
(12)
(9)
(11)
Y1
Y2
14
Y5 13 Y6 12 Y7 Y8
A3
Y3
11
(b)
A4
A5
A6
A7
Y4
Y5
Y6
Y7
(a)
A8
Y8
Figure 20: The 74x541 Microprocessor octal three-state buffer: (a) logic diagram, including pin 74x541 20-pinREAD dual in-line package; (b) traditional Input Port 1 logic symbol. 1 G1
gurenumbers 5-57 for a standard ng a 74x541 as a Moslem Amiri, V´ aclav Pˇrenosil
Design of Digital Systems19II INSEL1
G2
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ymbol.
(a)
Three-State Devices: SSI and MSI Three-State Buffers A8
(9)
(11)
Y8
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Microprocessor
igure 5-57 sing a 74x541 as a icroprocessor input ort.
74x541
1
READ
19
INSEL1
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
D0 D1
INSEL2 INSEL3
G2
2
A1
Y1
A2
Y2
A3 5 A4
Y3
3 4
D2 D3 D4
User Inputs
6
A5 7 A6
D5
8
D6 D7
Input Port 1
G1
9
Y4
18
DB0
17
DB1
16
DB2
15
DB3
14
DB4
Y5 13 Y6
A7
Y7
A8
Y8
DB5
12
DB6
11
DB7
74x541
1
19
G2
2
A1
3
User Inputs
Input Port 2
G1
A2 4 A3 5 A4 6 A5 7 8
A6
A7 9 A8
18
Y1 17 Y2 Y3
DB1
16
DB2
15
DB3
Y4 14 Y5 Y6
DB0
DB4
13
DB5
12
DB6
Y7 11 Y8
DB7
DB[0:7]
Figure 21: Using as a microprocessor input port.Prohibited Copyright © 1999 a by 74x541 John F. Wakerly Copying Moslem Amiri, V´ aclav Pˇrenosil
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Three-State Devices: SSI and MSI Three-State Buffers In Fig. 21, microprocessor selects Input Port 1 (top 74x541) by asserting INSEL1 and requests a read operation by asserting READ Selected 74x541 responds by driving microprocessor data bus with user-supplied input data Other input ports may be selected when a different INSEL line is asserted along with READ
A bus transceiver contains pairs of three-state buffers connected in opposite directions between each pair of pins, so that data can be transferred in either direction A bus transceiver is typically used between two bidirectional buses
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Three-State Devices: SSI and MSI Three-State Buffers Section 5.6
Three-State Devices
349
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
G_L DIR
A1
(19) (1)
(2)
(18)
B1
74x245
19
G DIR
1
A2
(3)
(17)
B2
2
3
A1 A2
4
A3
(4)
(16)
A3 5 A4
B3
6
A5 A6 8 A7 9 A8 7
A4
(5)
(15)
B4
18
B1 17 B2 16 B3
B4
15 14
B5 13 B6 12 B7 11 B8
(b)
A5
A6
A7
A8
(6)
(14)
(7)
(13)
(8)
(12)
(9)
(11)
B5
B6
B7
B8
(a)
individual buffers. Both enable inputs, G1_L and G2_L, must be asserted to
Figure 22: The 74x245 octal three-state transceiver: diagram; (b) enable the device’s three-state outputs. The little rectangular symbols(a) inside logic the buffer symbols indicate hysteresis, an electrical characteristic of the inputs that traditional logic symbol. improves noise immunity, as we explained in Section 3.7.2. The 74x541 inputs Moslem Amiri, V´ aclav Pˇrenosil Design of Digital Systems II typically have 0.4 volts of hysteresis.
November, 2012
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Three-State Devices: SSI and MSI Three-State Buffers 350
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Combinational Logic Design Practices
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Bus A
74x245
ENTFR_L ATOB
Control Circuits
19
1
2
3 4
5 6 7 8 9
G DIR A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
18 17 16 15 14 13
12 11
Bus B
Figure 5-59 Bidirectional buses and transceiver operation.
74x540
Many other varieties of octal three-state buffers are commercially availFigure 23:able.Bidirectional buses and transceiver operation. For example, the 74x540 is identical to the 74x541 except that it contains
Moslem Amiri, V´ aclav Pˇrenosil
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Three-State Devices: SSI and MSI Three-State Buffers Table 14: Modes of operation for a pair of bidirectional buses. ENTFR L 0 0 1
ATOB 0 1 x
Moslem Amiri, V´ aclav Pˇrenosil
Operation Transfer data from a source on bus B to a destination on bus A Transfer data from a source on bus A to a destination on bus B Transfer data on buses A and B independently
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Three-State Devices: Three-State Outputs in Verilog Table 15: Verilog module for a 74x541-like 8-bit three-state driver.
348
Chapter 5
Combinational Logic Design Practices
DO NOT COP DO NOT COP DO NOT COP 74x541
1
G1_L
G1 G2
19
2
3 4
5
A1 A2 A3 A4
6
A5 7 A6 8 A7 9
A8
G2_L
18
Y1 17 Y2 16 Y3
Y4
15
A2
(2)
(18)
(3)
(17)
(4)
(16)
(5)
(15)
Y1
Y2
14
Y5 13 Y6 12 Y7 Y8
A3
Y3
11
(b)
Moslem Amiri, V´ aclav Pˇrenosil
A1
(1)
(19)
A4
Design of Digital Systems II
(6)
November, 2012
(14) 49 /
Y4
69
Three-State Devices: Three-State Outputs in Verilog Table 16: Verilog module for a 74x245-like 8-bit transceiver. Section 5.6
Three-State Devices
349
O NOT COPY O NOT COPY O NOT COPY O NOT COPY (18)
B1
74x245
19
G DIR
1
(17)
B2
2
3 4
(16)
5
B3
A1 A2 A3 A4
6
A5 7 A6 8 A7
(15)
9
B4
A8
18
B1 17 B2 16 B3
B4
15 14
B5 13 B6 12 B7 B8
11
(b)
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Three-State Devices: Three-State Outputs in Verilog Table 17: Verilog module for a four-way, 8-bit bus transceiver.
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Three-State Devices: Three-State Outputs in Verilog Tab. 17 Transceiver handles four 8-bit bidirectional buses, A[1:8], B[1:8], C[1:8], and D[1:8] Each bus has its own output enable input, AOE L–DOE L, and a master enable input MOE L must also be asserted for any bus to be driven The same source of data is driven to all buses, as selected by S[2:0] If S2 = 0, buses are driven with a constant value When selected source is a bus, the selected source bus cannot be driven, even if it is output-enabled
Table 18: Bus-selection codes for a four-way bus transceiver.
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
equals the corresponding bit of the selected input, iDj. Multiplexers Multiplexers are obviously useful devices in any application in which data must be switched from multiple sources to a destination. A common application between the processor’s registers and its arithmetic logic unit (ALU). For example, a 16-bit processor in which It connects data from one of n sourcesconsider to its output
in computers is the multiplexer A multiplexer is a digital switch
(b)
1D0 1D1
1Y
1Dn1
2D0
multiplexer
(a)
2D1
EN
enable
2Y
s
SEL
select
2Dn1
b
D0
b
b
D1
n data sources
Y
b
Dn1
data output
bD0 bD1
bY
bDn1
SEL
EN
Figure 24: Copyright Multiplexer structure: inputs and outputs; (b)Copying functional © 1999 by John F.(a) Wakerly Prohibited equivalent. Moslem Amiri, V´ aclav Pˇrenosil
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Multiplexers Fig. 24(a) shows inputs and outputs of an n-input, b-bit multiplexer There are s inputs that select among n sources, so s = dlog2 ne When EN = 0, all of outputs are 0
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Design of Digital Systems II
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
16-pin packages. At one extreme is the 74x151, shown in Figure 5-62, which selects among eight 1-bit inputs. The select inputs are named C, B, and A, where C is most significant numerically. The enable input EN_L is active low; both active-high (Y) and active-low (Y_L) versions of the output are provided.
74x151
Multiplexers: Standard MSI Multiplexers EN_L
D0
D1
D2
D3
(7)
(4)
A′ A B′ B C′ C
(3)
(2)
(1)
(5)
Y
(6)
D4
D5
(14)
74x151
7
D6
(13)
11
10 9
D7
(12)
4 3 2
A
Y_L
(15)
EN A B C D0 D1 D2
Y Y
5
6
1
D3 D4 D5 D6 12 D7
(11)
15 14
B
C
13
(10)
(9)
(a)
Copyright © 1999 by John F. Wakerly
(b)
Copying Prohibited
Figure 25: The 74x151 8-input, 1-bit multiplexer: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol. Moslem Amiri, V´ aclav Pˇrenosil
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Multiplexers: Standard MSI Multiplexers Table 19: Truth table for a 74x151 8-input, 1-bit multiplexer.
Inputs EN L 1 0 0 0 0 0 0 0 0
Moslem Amiri, V´ aclav Pˇrenosil
C x 0 0 0 0 1 1 1 1
Outputs B x 0 0 1 1 0 0 1 1
A x 0 1 0 1 0 1 0 1
Y 0 D0 D1 D2 D3 D4 D5 D6 D7
Design of Digital Systems II
YL 1 D0’ D1’ D2’ D3’ D4’ D5’ D6’ D7’
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
Multiplexers: Standard MSI Multiplexers 74x157 2-input, 4-bit multiplexer: (a) logic diagram, Figure 5-63 The including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.
(a)
G_L S
(15)
(b)
(1)
74x157
15
G
1
2 3 5
1A
(2)
6
S 1A 1B 2A 2B
1Y 2Y
11
(4)
1B
2A
(3)
3A
4A 13 4B
4A
(6)
9
12
2Y
(11)
(10)
3Y
(14)
(12)
4B
4Y
7
(5)
(9)
3B
3Y
14
(7)
2B
1Y
3A 10 3B
4
(13)
4Y
Copyright © 1999 by John F. Wakerly Copying Prohibited Figure 26: The 74x157 2-input, 4-bit multiplexer: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.
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Multiplexers: Standard MSI Multiplexers Table 20: Truth table for a 74x157 2-input, 4-bit multiplexer.
Inputs GL 1 0 0
Moslem Amiri, V´ aclav Pˇrenosil
S x 0 1
Outputs 1Y 0 1A 1B
2Y 0 2A 2B
3Y 0 3A 3B
Design of Digital Systems II
4Y 0 4A 4B
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Figure 5-64 Ta bMSI l e 5 - 3 Multiplexers 5 Multiplexers: Standard Inputs Outputs Traditional logic Truth table for a
symbol for the B A 1Y 2Y 74x153 4-input, 2-bit 74x153. multiplexer. 1C0 2C0 0 0 0 1C1 2C1 0 0 1 74x153 0 121: 0Truth1C2 14 Table table2C2 for a 74x153 A 2 1C3 2C3 0 1 1 B 4-input, 2-bit multiplexer. 1 1C0 1 0 0 0 1G 6 1C1 1C0 1 0 1 0 5 Inputs Outputs 1C1 7 1C2 1 1 0 0 1Y 4 1C2 1 11G L 1 2G L 1C3 0 B A 1Y 2Y 3 1C3 15 0 0 0 0 0 00 02C0 1C0 2C0 2G 10 0 0 0 1 0 00 12C1 1C1 2C1 2C0 11 2C1 0 1 0 0 0 01 02C2 1C2 2C2 9 2Y 12 2C2 0 1 0 1 0 01 12C3 1C3 2C3 13 2C3 1C0 0 1 x 0 x 1 00 0 0 0 1 0 1 1C1 0 1 1 0 1C2 0 0 Figure 27: Traditional logic 1999 by John F. Wakerly Copying Prohibited 0 1 1 1 1C3 0 for the 74x153. 1 0 0 0 0 2C0 1 0 0 1 0 2C1 1 0 1 0 0 2C2 1 0 1 1 0 2C3 1 1 x x 0 0
L
2G_L
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Multiplexers: Standard MSI Multiplexers Some multiplexers have three-state outputs Enable input, instead of forcing outputs to zero, forces them to Hi-Z state Three-state outputs are useful when n-input muxes are combined to form larger muxes
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Multiplexers: Expanding Multiplexers Size of an MSI multiplexer seldom matches characteristics of problem at hand E.g., an 8-input, 32-bit multiplexer might be used in design of a processor We use 32 74x151 8-input, 1-bit multiplexers, each handling one bit of all inputs and output Processor’s 3-bit register-select field is connected to A, B, and C inputs of all 32 muxes, so they all select same register source at any given time
Another dimension in which multiplexers can be expanded is number of data sources E.g., a 32-input, 1-bit multiplexer
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Multiplexers: Expanding Multiplexers Section 5.7
Multiplexers
363
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY 74x151
7
XA0
EN
11
XA1
A
10
B C D0 3 D1
XA2
9 4
X0 X1 X2
2 1
X3
15
X4
14
X5
13
X6 X7
12
Y
1
1G
1Y0 1Y1
XA3 XA4
2
1A 3 1B
1Y2 1Y3
4 5
EN0_L EN1_L
EN2_L 7 EN3_L 6
6
XO0_L
D3 D4 D5 D6 D7
U2
1/2 74x139
XEN_L
5
Y
D2
74x151
7
EN
11
10
9
U1
4
X8
3
X9
2
X10 X11
1
A B
C D0 D1
Y Y
5
6
XO1_L
D2 D3
15
D4 D5 13 D6 12 D7
X12 X13 X14 X15
14
1
U3
2 4
74x151
7
11
10
9 4
X16 X17 X18 X19 X20
3 2 1
EN A B C D0 D1 D2 D3
5
Y Y
1/2 74x20
6
XOUT
U6
5
6
XO2_L
15
D4 14 D5 13 D6 12 D7
X21 X22 X23
U4
74x151
7
11
10
9 4
X24 X25 X26
3 2
EN A B C D0 D1 D2
Y Y
5
6
XO3_L
Figure 5-65 Combining 74x151s to make a 32-to-1 multiplexer.
1
X27 X28 X29 X30 X31
D3 D4 14 D5 13 D6 12 D7 15
Copyright © 1999 by John F. Wakerly
U5
Copying Prohibited
Figure 28: Combining 74x151s to make a 32-to-1 multiplexer. Moslem Amiri, V´ aclav Pˇrenosil
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Multiplexers: Expanding Multiplexers 74x251 is identical to ’151 in its pinout and its internal logic design, except that Y and Y L are three-state outputs 32-to-1 multiplexer can also be built using 74x251s The circuit is identical to Fig. 28, except that output NAND gate is eliminated Instead, Y outputs of four ’251s are simply tied together
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
The 32-to-1 multiplexer can also be built using 74x251s. The circuit is Multiplexers, and identicalDemultiplexers, to Figure 5-65, except that the outputBuses NAND gate is eliminated. Instead, the Y (and, if desired, Y_L) outputs of the four ’251s are simply tied together. The ’139 decoder ensures that at most one of the ’251s has its threeA multiplexer canenabled be used select oneis of n sources data state outputs at anyto time. If the ’139 disabled (XEN_L isof negated), of the ’251s are disabled, and the XOUT and XOUT_L outputs are transmit then on all a bus undefined. However, if desired, resistors may be connected from each of these At far endtoof demultiplexer cancase. be used to route bus signals +5 bus, volts toapull the output HIGH in this
to data to
one of m destinations
igure 5-66 multiplexer driving a bus nd a demultiplexer ceiving the bus: ) switch equivalent; ) block diagram symbols.
(a)
multiplexer
demultiplexer
SRCA
DSTA
SRCB
DSTB
BUS
SRCC
DSTC
SRCZ
DSTZ
SRCSEL
(b)
DSTSEL
SRCA
SRCB SRCC
DSTA
MUX
BUS
DMUX
SRCZ
DSTB DSTC DSTZ
SRCSEL
DSTSEL
© 1999 by John F. Wakerly ACopyright multiplexer driving a bus
Copyingreceiving Prohibited the bus: Figure 29: and a demultiplexer (a) switch equivalent; (b) block-diagram symbols. Moslem Amiri, V´ aclav Pˇrenosil
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DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY
one are 0; the selected output equals the data input. This definition may be
Multiplexers, generalized for a b-bit,Demultiplexers, n-output demultiplexer; suchand a deviceBuses has b data inputs,
and its s select inputs choose one of n = 2s sets of b data outputs. A binary decoder with an enable input can be used as a demultiplexer, as Function a The demultiplexer inverse of a to multiplexer’s shown in Figure of 5-67. decoder’s enableisinput is connected the data line, and its select inputs determine of its output lines the data A b-bit, n-outputwhich demultiplexer has isb driven data with inputs and s bit. The remaining output lines are negated. Thus, the 74x139 can be used as a s one of n = 2 sets of b data outputs 2-bit, 4-output demultiplexer with active-low data inputs and outputs, and the 74x138 can be used as a 1-bit, 8-output demultiplexer. In fact, A binary decoder with an enable input canthebemanufacturused as a er’s catalog typically lists these ICs as “decoders/demultiplexers.” (a)
2-to-4 decoder
SRCDATA
G
DSTSEL0 DSTSEL1
A B
Y0 Y1 Y2 Y3
demultiplexer
1/2 74x139
(b)
DST0DATA DST1DATA DST2DATA DST3DATA
inputs to select
SRCDATA_L
G
DSTSEL0 DSTSEL1
A B
Using aa2-to-4 binary decoder as a 1-bit, demultiplexer: Figure Figure 5-67 30: Using 2-to-4 binary decoder as4-output a 1-bit, 4-output (a) generic decoder; (b) 74x139.
Y0 Y1 Y2 Y3
DST0DATA_L DST1DATA_L DST2DATA_L DST3DATA_L
demultiplexer: (a)
generic decoder; (b) 74x139.
5.7.4 Multiplexers in ABEL and PLDs Multiplexers are very easy to design using ABEL and combinational PLDs. For example, the function of a 74x153 4-input, 2-bit multiplexer can be duplicated enable input5-68 is connected datacharacteristics line, and its select in aDecoder’s PAL16L8 as shown in Figure and Table 5-36.to Several of the PLD-based design are worth noting: determine whichandofprogram its output lines is driven with data bit • Signal names in the ABEL program are changed slightly from the signal names shown for a 74x153 in Figure 5-64 on page 361, since ABEL does notAmiri, allow number first character of a signal name. Moslem V´ aa clav Pˇrenosilto be used as theDesign of Digital Systems II
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Multiplexers in Verilog Table 22: Dataflow Verilog program for a 4-input, 8-bit multiplexer.
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Multiplexers in Verilog Table 23: Behavioral Verilog module for a 4-input, 8-bit multiplexer.
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Multiplexers in Verilog Table 24: Behavioral Verilog program for a specialized 4-input, 18-bit multiplexer.
Moslem Amiri, V´ aclav Pˇrenosil
Table 25: Function table for a specialized 4-input, 18-bit multiplexer.
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References John F. Wakerly, Digital Design: Principles and Practices (4th Edition), Prentice Hall, 2005.
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