Infineon
DDR2 – The Next DRAM Generation
New York Joachim W. Binder 2004-05-18 slide -1 -
May 18th, 2004 – New York Please note that while you are reviewing this information, this presentation was created as of the date listed, and reflected management views as of that date. This presentation contains certain forward-looking statements that are subject to known and unknown risks and uncertainties that could cause actual results to differ materially from those expressed or implied by such statements. Such risks and uncertainties include, but are not limited to the Risk Factors noted in the Company's Earnings Releases and the Company's filings with the Securities and Exchange Commission.
Joachim W. Binder Director Investor Relations
Copyright © Infineon Technologies 2004. All rights reserved.
The Performance Gap Performance Performance Gap
L1 Pentium IV
L2
Pentium III
Pentium II
L3
L1 Pentium
D ual C ha
L2
10ns 7.5ns
New York Joachim W. Binder 2004-05-18 slide -2 -
533MHz 333MHz 400MHz L1 266MHz 200MHz 133MHz 200MHz DDR SDRAM 66MHz 100MHz 3.3ns SDR SDRAM 6ns 5ns
nnal
800MHz 667MHz
DDR2 SDRAM
EDO DRAM
1990 1992 1994
1996
1998
2000
2002
2004
2006
Year
Copyright © Infineon Technologies 2004. All rights reserved.
Why DDR2?
New York Joachim W. Binder 2004-05-18 slide -3 -
! !
To increase clock frequency up to 400 MHz (i.e. 800Mbit/s per pin bandwidth)
! !
To decrease power consumption
! !
To extend the physical limits by another 3 to 4 years (volume DRAM solution for 2005-2008)
! !
To improve bus utilization
! !
To keep cost, cost, and cost as low as possible Copyright © Infineon Technologies 2004. All rights reserved.
DDR Memory Module versus DDR2 Memory Module TSOP package (thin small outline package)
FBGA (fine-pitch ball grid array) New York Joachim W. Binder 2004-05-18 slide -4 -
Copyright © Infineon Technologies 2004. All rights reserved.
Memory Modules: Registered (RDIMM) and Unbuffered Modules (DIMM) Register
DDR II SDRAM
New York Joachim W. Binder 2004-05-18 slide -5 -
Parity / ECC
Clock Driver
serial EEPROM
Copyright © Infineon Technologies 2004. All rights reserved.
Notebook Memory Modules: Small Outline DIMM (SO-DIMM)
New York Joachim W. Binder 2004-05-18 slide -6 -
Copyright © Infineon Technologies 2004. All rights reserved.
Different Target Markets !
Server – registered modules (RDIMM); x4, x8 devices – focusing on 400MHz devices this year – up to 32 modules (8 channels by 4 modules each) per machine; typ. 8 modules
!
Workstations – registered modules; x4, x8, x16 devices – focusing on 533MHz devices this year – 2 to 4 modules per machine
!
PCs – registered or unbuffered modules; x8, x16 devices – focusing on 533MHz devices this year – up to 3 modules per machine (Dual Channel: 2 modules per channel)
!
New York Joachim W. Binder 2004-05-18 slide -7 -
Notebooks – x16 devices; x8 for high-density module only – focusing on 400MHz and 533MHz devices late 2004 – up to 2 modules per machine Copyright © Infineon Technologies 2004. All rights reserved.
Block Diagram of PC System CPU CPU
L1 L1 Cache Cache
L2 L2 Cache Cache
FSB
Graphics Graphics Subsystem Subsystem
ATA ATA Ports Ports
AGP (PCI-Express 16)
PCI (PCI-Express 1)
LAN LAN New York Joachim W. Binder 2004-05-18 slide -8 -
Mouse/Keyb. Mouse/Keyb.
Memory Memory Controller Controller Hub Hub (North (North Bridge) Bridge)
Memory Bus Memory Bus
DDR DDR SDRAM SDRAM
DDR DDR SDRAM SDRAM
Audio Audio (South (South Bridge) Bridge)
USB USB BIOS BIOS Support Support Copyright © Infineon Technologies 2004. All rights reserved.
PC Motherboards (ATX Format) Serial Port
Parallel Port
USB
Mouse / Keyboard Power Supply Plugin
PCI Slot AGP Slot
North Bridge
CPU Socket
South Bridge
New York Joachim W. Binder 2004-05-18 slide -9 -
CMOS Battery
IDE Controller
Memory Slot Copyright © Infineon Technologies 2004. All rights reserved.
Processor / Memory Interconnection (von Neumann Architecture)
address bus command bus CPU data bus
addresses commands New York Joachim W. Binder 2004-05-18 slide -10 -
Memory
data
John von Neumann (1903 – 1957) Copyright © Infineon Technologies 2004. All rights reserved.
Block Diagram of a DRAM
add [0..9]
row [0..9]
cell array 1K x 1K [0]
col [0..9]
New York Joachim W. Binder 2004-05-18 slide -11 -
CLK CKE \RAS \CAS \WE \CS
[1] [2]
[5] [3] [4]
[7] [6]
sense sense amplifier amplifier
control logic data [0..7] Copyright © Infineon Technologies 2004. All rights reserved.
The Introduction of Banks Independent Memory Sections Within the Chip BS [0..1]
[7] [6] [5] [4] [3] [2] [1] [0]
New York Joachim W. Binder 2004-05-18 slide -12 -
Copyright © Infineon Technologies 2004. All rights reserved.
Example: 256 Mbit (32M x 8) = 4 x 4K x (2K) x 8 4 Banks, 4096 Rows, 2K Page, x8 Organization 2K page length [7] [6] [5] [4] [3] [2]
x8 organization
[1]
New York Joachim W. Binder 2004-05-18 slide -13 -
[0]
Copyright © Infineon Technologies 2004. All rights reserved.
512M DDR2 SDRAM Die Photo
New York Joachim W. Binder 2004-05-18 slide -14 -
Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 a) Densities DDR
DDR2
DDR2 Advantage
128M, 256M, 512M, 1G 256M, 512M, 1G, 2G (4G) larger memory subsystems possible
256M 256M 2G 2G
512M 512M
4G 4G
1G 1G
110nm New York Joachim W. Binder 2004-05-18 slide -15 -
90nm
70nm or later Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 b) Package DDR
DDR2
DDR2 Advantage
TSOP (66 pins), some in FBGA
FBGA only
better electrical characteristics; reduced parasitics;
(TSOP = thin small outline package)
(FBGA = fine-pitch ball grid array)
smaller footprint; stacked/dual die (two dies in a package)
500
µm
350
New York Joachim W. Binder 2004-05-18 slide -16 -
µm
Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 c) Operating Voltage DDR
DDR2
DDR2 Advantage
2.5V for core 2.5V for I/O
1.8V for core 1.8V for I/O
reduced power consumption
Voltage [V]
5.0V 3.3V 2.5V 1.8V 1.2V New York Joachim W. Binder 2004-05-18 slide -17 -
1970
1996
2001
2004
2007 Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR 2 d) Clock Frequencies DDR
DDR2
DDR2 Advantage
200MHz (100MHz) [100MHz], 266MHz (133MHz) [133MHz], 333MHz (166MHz) [166MHz], 400MHz (200MHz) [200MHz]
400MHz (200MHz) [100MHz], 533MHz (266MHz) [133MHz], 667MHz (333MHz) [166MHz], 800MHz (400MHz) [200MHz]
migration to higherspeed I/Os; more relaxed internal timing requirements
internal clock chip clock clock for data transfer
New York Joachim W. Binder 2004-05-18 slide -18 -
Copyright © Infineon Technologies 2004. All rights reserved.
Impact on Front End Manufacturing (1) !
Manufacturing challenges: none
!
Overall die size increase: about 5-10% – ~ 2-3% increase due to wider internal data busses because of 4-bit-data-prefetch – ~ 3-7% increase due to architectural changes
!
4-bit-data-prefetch: – more relaxed internal timing, therefore better yields
New York Joachim W. Binder 2004-05-18 slide -19 -
!
On-die-termination (ODT): none
!
I/O callibration (OCD): none
Copyright © Infineon Technologies 2004. All rights reserved.
Impact on Front End Manufacturing (2) !
Reduced power consumption for comparable densities – will go down due to lower internal clock frequencies – will go down (activation currents) due to shortened page length – will go down due to some I/O power savings – will go up due to higher densities – will go up due to higher clock frequencies
New York Joachim W. Binder 2004-05-18 slide -20 -
Copyright © Infineon Technologies 2004. All rights reserved.
Impact on Backend Manufacturing !
Testing time: none
!
New testing tools required? – No, basically not for 400MHz. – Perhaps, could be required for 533MHz. (depending on the state-of-the-art of the existing tools) – Yes, definitely for 667MHz and 800 MHz.
!
Packaging tools required? – New packaging tools definitely required as FPGA is used only.
! Packaging costs? – Will go up as FBGA is more expensive as TSOP. New York Joachim W. Binder 2004-05-18 slide -21 -
Copyright © Infineon Technologies 2004. All rights reserved.
Conclusion " Step from DDR I to DDR II has small impact on cost; major contribution comes from FBGA package. " Step from DDR I to DDR II not significantly different than transition from SDR to DDR I with respect to volume ramp-up and price transition. " There will be an initial price premium due to capacity limitation. With a DDR II share of more than 50% (expected for 2H05) premium will be close to parity.
New York Joachim W. Binder 2004-05-18 slide -22 -
Copyright © Infineon Technologies 2004. All rights reserved.
Roadmap for DDR III !
Voltage: 1.8V # 1.2V
!
Density: 8G and onward
1333MHz 1067MHz 800MHz 667MHz 533MHz 400MHz
2004
SDR New York Joachim W. Binder 2004-05-18 slide -23 -
DDR
2007
DDR-II
DDR-III Copyright © Infineon Technologies 2004. All rights reserved.
Source: www.intel.com/technology/memory/ddr/valid/ddr2_dram_results.htm
Validated DDR2 400MHz SDRAM Components
New York Joachim W. Binder 2004-05-18 slide -24 -
Copyright © Infineon Technologies 2004. All rights reserved.
Bibliography !
DDR II memory boards validated by Intel: www.intel.com/technology/memory/ddr/valid/ddr2_dram_results.htm
!
"Denali Memory Report": www.denali.com
!
Technical notes about DDR II by Micron: www.micron.com/products/dram/ddr2sdram/technote.html
New York Joachim W. Binder 2004-05-18 slide -25 -
Copyright © Infineon Technologies 2004. All rights reserved.
To create Semiconductor Solutions, enabling the Technology Lifestyle of the Individual in the 21st Century.
− Appendix − New York Joachim W. Binder 2004-05-18 slide -26 -
Copyright © Infineon Technologies 2004. All rights reserved.
DDR2 Package Ballout for a x8 Device 1
2
3
7
8
9
A
VDD
\RDQS
VSS
VSSQ
\DQS
VDDQ
B
DQ6
VSSQ
DM
DQS
VSSQ
DQ7
+
C
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
+
D
DQ4
VSSQ
DQ3
DQ2
VSSQ
DQ5
E
VDDL
VREF
VSS
VSSDL
CK
VDD
CKE
\WE
\RAS
\CK
ODT
BA0
BA1
\CAS
\CS
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
A12
A14
A15
A13
1 2 3456 7 8 9 A B C D E F G H J K L
+ + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+
$ populated ball + ball not populated
F G
BA2
H J
VSS
K L New York Joachim W. Binder 2004-05-18 slide -27 -
VDD
VDD VSS
Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 e) Page Size Reduction
New York Joachim W. Binder 2004-05-18 slide -28 -
DDR
DDR2
DDR2 Advantage
256M: 1KB
256M: 1KB
512M, 1G: 2KB
512M, 1G, 2G: 1KB (x4, x8) 2KB (x16)
reduced activation power due to shortened page size
cell array
cell array
1K x 2K
1K x 1K
sense sense amplifier amplifier
sense sense amplifier amplifier
Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 f) Prefetch DDR
DDR2
DDR2 Advantage
2 bit
4 bit
memory core internally operates only with half the frequency; reduced core speed dependency for better yields; reduced power consumption; internal data bus has to be doubled; slightly increase of the die size; additional space [0]
New York Joachim W. Binder 2004-05-18 slide -29 -
[0]
additional space Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 g) Internal Banks
New York Joachim W. Binder 2004-05-18 slide -30 -
DDR
DDR2
DDR2 Advantage
256M, 512M, 1G: 4 banks
256M, 512M: 4 banks 8 banks give better performance 1G, 2G: 8 banks than 4 banks
[3] [2] [1] [0]
[3] [2] [1] [0]
[3] [2] [1] [0]
[3] [2] [1] [0]
[3] [2] [1] [0]
[3] [2] [1] [0]
[3] [2] [1] [0]
[3] [2] [1] [0]
Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 h) Read and Write Latencies DDR
DDR2
DDR2 Advantage
Read_Latency: 2; 2.5; 3 CLK
Read_Latency: CL + AL CL = (3; 4; 5)
eliminating half-clock cycles helps speed internal DRAM logic, improves yields, and reduces test cost
AL not implemented
AL = (0; 1; 2; 3; 4) (AL = additive latency)
additive latency mainly used in server applications to improve command bus efficiency
Write_Latency: 1 CLK
Write_Latency = Read_Latency - 1
improves command bus efficiency
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK adr
row
col
cmd
act
write
data New York Joachim W. Binder 2004-05-18 slide -31 -
Write_Latency
Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 i) On-Die Termination DDR
DDR2
DDR2 Advantage
on-motherboard termination
on-die termination (ODT)
ODT for both memory and controller improves signalling and reduces system cost
Switch 1 or 2 is enabled VDDQ by the ODT pin. Selection between switch 1 or 2 is determined by two bits in the Extended Mode Registe Set switch 1 (EMRS).
to and from the SSA
On-die termination offers the option to teminate the signals in the DRAM itself rather than on the motherboard. A handful of resistor packs and capacitors on the motherboard are not necessary anymore which reduces some cost and makes memory subsystem layout more efficient.
VDDQ
switch 2
DRAM input buffer
DQ Pin
switch 1
switch 2
control New York Joachim W. Binder 2004-05-18 slide -32 -
VSSQ
This feature requires an additional pin named "ODT".
VSSQ
ODT Pin Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 j) Data Strobes DDR
DDR2
DDR2 Advantage
single-ended
differential or single-ended
improves system timing margin by reduced strobe crosstalk; increases pin count for the memory controller
single-ended data strobe
Vref
DQS
differential data strobe
\DQS trigger points
New York Joachim W. Binder 2004-05-18 slide -33 -
DQS Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 k) I/O Callibration (Off-Chip Driver Impedance Adjustment) DDR
DDR2
DDR2 Advantage
no
off-chip driver (OCD) impedance adjustment; memory controller configured
enables system to align pull-up / pull-down drive strengths to nominal conditions; feature not expected to be widely used
Explanation In DDR the output drivers have to confirm the minimum and maximum V/I curves defined by JEDEC commitee. Furthermore, due to process variations the Ron resistance can also vary from device to device. In DDR II the output driver Ron resistance can be adjusted and optimized for the system application. This new feature is called "OCD". Programming the OCD can be done via three bits in the Extended Mode Register.
New York Joachim W. Binder 2004-05-18 slide -34 -
Since the Ron characteristic is a function of temperature and voltage, the Ron value can be re-adjusted any time it is needed during operation. Copyright © Infineon Technologies 2004. All rights reserved.
Changes from DDR to DDR2 l) Modules
New York Joachim W. Binder 2004-05-18 slide -35 -
DDR
DDR2
DDR2 Advantage
184-pin unbufered 184-pin registered
240-pin unbuffeered 240-pin registered
modules are same length, with added pins;
200-pin SO-DIMM
200-pin SO-DIMM
172-pin MicroDIMM
214-pin MicroDIMM
DDR2 SO-DIMM is same connector;
244-pin MiniDIMM
different pinout as DDR
Copyright © Infineon Technologies 2004. All rights reserved.
From SDR to DDR: The Introduction of "Prefetch 2"
1
0
0 1
primary sense amplifier
0 1
secondary sense amplifier
~3% die size increase additional space
I/O Interface
1 New York Joachim W. Binder 2004-05-18 slide -36 -
0
additional space Copyright © Infineon Technologies 2004. All rights reserved.
Latencies: tRDC, tCL 133MHz; Burst Length = 8; Page Hit; Same Bank 1
2
3
4
5
6
7
8
9
10
11
12
13
CLK adr
row
col X
act
read
col Y
tCK = 7.5ns
\RAS \CAS cmd data tRCD = 2
tCL = 2
tCL = 2 1st burst
New York Joachim W. Binder 2004-05-18 slide -37 -
2nd burst Copyright © Infineon Technologies 2004. All rights reserved.
Latencies: tRDC, tCL 133MHz; Burst Length = 8; Page Hit; Different Banks 1
2
3
4
5
6
7
8
9
10
11
12
13
CLK bank 0
adr
row
bank 1
col
row
col
tCK = 7.5ns
\RAS \CAS cmd
act
read
Preparation of read operation in bank 1 while data transfer in bank 0.
act
data tRCD = 2
tCL = 2
tRCD = 2
tCL = 2
1st burst in bank 0 New York Joachim W. Binder 2004-05-18 slide -38 -
2nd burst in bank 1 Copyright © Infineon Technologies 2004. All rights reserved.
Latencies: tRDC, tCL, tRP, tRC 133MHz; Burst Length = 8; Page Miss 1
2
3
4
5
6
7
8
9
10
11
12
13
CLK adr
row X
col
act
read
row Y
col
act
read
\RAS \CAS cmd
prech
data tRCD = 2
tCL = 2
tRP = 2
tRCD = 2
tCL = 2
tRAS = 6 tRC = 8 New York Joachim W. Binder 2004-05-18 slide -39 -
1st
burst
start of 2nd burst Copyright © Infineon Technologies 2004. All rights reserved.
