CZECH TECHNICAL UNIVERSITY IN PRAGUE Faculty of Electrical Engineering

MASTER THESIS

Bc. Michal Eli´aˇs Digital Measurement System for the HIE-Isolde Superconducting Accelerating Cavities

Department of Cybernetics Thesis supervisor: Ing. Daniel Val´ uch, PhD

Acknowledgements I would like to thank my supervisor Ing. Daniel Val´ uch, PhD, for his advices and support, to Gregoire Hagmann for providing us with a module that made the development much faster, to rest of my colleagues at CERN for doing a great job and answering all my questions. And most importantly to my family, always being there for me.

Abstrakt Supravodiv´e rezonanˇcn´ı dutiny pro urychlovaˇc HIE-Isolde jsou v souˇcasnou chv´ıli st´ale ve v´ yvoji. Znaˇcn´e mnoˇzstv´ı energie i zdroj˚ u Evropsk´e organizace pro jadern´ y v´ yzkum (CERN) je investov´ano do v´ yzkumu veden´ı vysokofrekvenˇcn´ıho pole uvnitˇr supravodiˇc˚ u, v´ yvoji rezonanˇcn´ıch dutin a napraˇsov´an´ı a nan´aˇsen´ı supravodiv´ ych materi´al˚ u. Pro usnadnˇen´ı v´ yvoje je d˚ uleˇzit´e m´ıt k dispozici syst´em, s jehoˇz pomoc´ı se daj´ı rychle a pˇresnˇe mˇeˇrit vysokofrekvenˇcn´ı vlastnosti novˇe vyvinut´ ych dutin. Souˇcasn´ y syst´em zaloˇzen´ y na analogov´em mˇeˇren´ı f´aze a sledovac´ıch VF gener´atorech nen´ı pro testy optim´aln´ı. Pokud nejsou pˇredem zn´amy pˇresn´e parametry dutiny, tradiˇcn´ı zpˇetnovazebn´ı syst´em nebude schopn´ y nal´ezt rezonanci, popˇr´ıpadˇe jej´ı nalezen´ı potrv´a pˇr´ıliˇs dlouho. Toto je zp˚ usobeno velk´ ym ˇcinitelem jakosti Q, kter´eho tyto dutiny dosahuj´ı (p´asmo rezonance je ˇsirok´e jen zlomek Hz na frekvenci 100 MHz). Pokud je dutina rozladˇena jen o nˇekolik ˇs´ıˇrek p´asma, intenzita pole uvnitˇr dutiny pˇri ladˇen´ı frekvence bude t´emˇeˇr nemˇeˇriteln´a. Nav´ıc m´a vysokofrekvenˇcn´ı pole uvnitˇr dutiny znaˇcnou setrvaˇcnost, rychlost ladˇen´ı je tud´ıˇz velmi omezen´a. Proto je nutn´e navrhnout nov´ y, plnˇe digit´aln´ı, syst´em zaloˇzen´ y na st´avaj´ıc´ım hardware vyvinut´em pro LHC a SPS urychlovaˇce. D´ale uv´aˇzit nov´e zp˚ usoby pro rychlejˇs´ı nalezen´ı a sledov´an´ı rezonance, kter´e budou fungovat i v prostˇred´ı s vibracemi a v´ ykyvy tlaku h´elia.

Abstract At the time of writing, the superconducting cavities for the HIE Isolde accelerator are still under development. Extensive R&D efforts are being invested at CERN into the fundamental science of the RF superconductivity, cavity design, niobium sputtering, coating and RF properties of superconducting cavities. Fast and precise characterisation and measurements of RF parameters of the newly produced cavities is essential for advances with the cavity production. The currently deployed analogue measurement system based on an analogue phase discriminators and tracking RF generators is not optimal for efficient work at the SM18 superconducting cavity test stand. If exact properties of the cavity under test are not known a traditional feedback loop will not be able to find resonant frequency in a reasonable time or even at all. This is mainly due to a very high Q factor. The resonance peak is very narrow (fraction of a Hz at 100 MHz). If the resonant frequency is off by several bandwidths, small changes of the cavity field during the tuning will not be measureable. Also cavity field will react only very slowly to any change of the drive signal. A new techniques to find and track the cavity resonance faster, as well as to keep the cavity field constant under strong microphonics and helium pressure variations must be found to meet the deadlines for the HIE Isolde machine. Therefore a new fully digital measurement and conditioning system based on the available existing hardware from the LHC and SPS must be designed and built.

CONTENTS

Digital Measurement System

Contents 1 Introduction

1

2 HIE Isolde

3

3 RF Systems

4

3.1

Quarter wave resonator for the HIE-Isolde machine . . . . . . . . . . . . .

7

3.2

LLRF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

3.2.1

Self excited loop

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

3.2.2

Generator driven mode of operation . . . . . . . . . . . . . . . . . .

9

3.2.3

State of The Art . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

4 Warm cavity test setup

12

5 Measurement card

14

5.1

Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

5.2

VME modular system . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

5.2.1

Direct RF sampling and direct digital quadrature demodulation . .

17

5.2.2

ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17

5.2.3

DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

5.2.4

Onboard clock distribution . . . . . . . . . . . . . . . . . . . . . . .

20

FPGA and the firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

5.3.1

Decimator and demodulator VHDL block . . . . . . . . . . . . . . .

22

5.3.2

Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

5.3.3

Module configuration . . . . . . . . . . . . . . . . . . . . . . . . . .

27

5.3.4

Configuration scripts . . . . . . . . . . . . . . . . . . . . . . . . . .

28

Measurement card prototype . . . . . . . . . . . . . . . . . . . . . . . . . .

29

5.3

5.4

6 Clock Generator

31

6.1

Sampling clock generator prototype board . . . . . . . . . . . . . . . . . .

32

6.2

PCB version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33

6.3

810 MHz band pass filter design . . . . . . . . . . . . . . . . . . . . . . . .

34

7 RF amplifier

36 i

CONTENTS

Digital Measurement System

8 Cavity tuning system

38

9 Project status and the next steps

40

10 Measured results

40

10.1 Sampling clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

10.2 Direct RF sampling and digital quadrature demodulation . . . . . . . . . .

41

10.3 Cavity tuning transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41

10.4 Other interesting results . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41

11 Conclusion

46

ii

LIST OF FIGURES

Digital Measurement System

List of Figures 1

CERN accelerator complex (taken from [1]) . . . . . . . . . . . . . . . . .

2

2

Isolde hall after upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

3

Model of a ferrite resonator [2] . . . . . . . . . . . . . . . . . . . . . . . . .

5

4

Booster RF ferrite cavity [2] . . . . . . . . . . . . . . . . . . . . . . . . . .

5

5

SPS 200 MHz travelling wave structure [2] . . . . . . . . . . . . . . . . . .

5

6

200 MHz TWC in the SPS tunnel (circa 1975) [2] . . . . . . . . . . . . . .

5

7

LHC 400 MHz superconducting cavity (production in the clean room) [2] .

5

8

LHC superconducting cavities (in the machine tunnel) [2] . . . . . . . . . .

5

9

LEP 352 MHz normal conducting cavities [2] . . . . . . . . . . . . . . . . .

6

10

PSI 50 MHz normal conducting cavity [2] . . . . . . . . . . . . . . . . . . .

6

11

SPS RF amplifier [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

12

300 kW klystron for LHC . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

13

Coaxial quarter wave resonator . . . . . . . . . . . . . . . . . . . . . . . .

7

14

Cavity model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

15

Self excited loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

16

Generator driven system . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

17

LHC cavity controller diagram [4] . . . . . . . . . . . . . . . . . . . . . . .

11

18

LHC beam phase module. An example of a mixed RF and digital VME board [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

19

Schematic diagram of the warm cavity test setup . . . . . . . . . . . . . .

12

20

Warm cavity test setup in the building 864 . . . . . . . . . . . . . . . . . .

13

21

Measure card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .

15

22

HIE-Isolde machine LLRF diagram . . . . . . . . . . . . . . . . . . . . . .

16

23

LHC RF Low Level chassis . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

24

ADC sampling scheme, k = 0, locked frequencies . . . . . . . . . . . . . . .

18

25

ADC sampling scheme, k = 1, variations in the RF signal . . . . . . . . . .

19

26

Functional block diagram of the ADC AD9255 . . . . . . . . . . . . . . . .

20

27

Functional block diagram of the DAC AD9122 . . . . . . . . . . . . . . . .

20

28

LVDS receiver and DDR decoder as a chip specific primitives defined on the ChipTop level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22

VME memory map in the Cheburashka software . . . . . . . . . . . . . . .

23

29

iii

LIST OF FIGURES

30

Digital Measurement System

Firmware development design flow. Blue blocks show the hardware development, green blocks the software development . . . . . . . . . . . . . . . . .

24

31

Decimation and CoRDIC blocks in the Visual Elite environment . . . . . .

24

32

SRAM Read/Write cycle timing [5] . . . . . . . . . . . . . . . . . . . . . .

27

33

Lowest level of the memory controller in the Visual Elite environment . . .

28

34

Modified SPS TWC800 Cavity Loops module . . . . . . . . . . . . . . . .

30

35

Effective number of bits as a function of the input signal frequency and the sampling clock jitter [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

36

Clock generation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32

37

Prototype of the clock generator . . . . . . . . . . . . . . . . . . . . . . . .

33

38

With bandpass filter connected . . . . . . . . . . . . . . . . . . . . . . . .

33

39

PCB version of the Clock generator . . . . . . . . . . . . . . . . . . . . . .

34

40

Glitch in the ECL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

41

Glitch detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

42

Filter prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

43

Tuning the resonant frequency . . . . . . . . . . . . . . . . . . . . . . . . .

35

44

Stripline hairpin band pass filter . . . . . . . . . . . . . . . . . . . . . . . .

35

45

Assembled filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

46

Block diagram of the 30 W RF amplifier . . . . . . . . . . . . . . . . . . .

36

47

30 W RF amplifier prototype. The analogue gauges are used for forward and reflected power indication. Full scale 30 W . . . . . . . . . . . . . . . . . .

37

48

Cavity tuning system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

49

Tuning control user interface . . . . . . . . . . . . . . . . . . . . . . . . . .

39

50

Sampling clock generator jitter measurement . . . . . . . . . . . . . . . . .

42

51

ADC noise floor for different values of the input signal frequency. Red trace fRF = 2 MHz, green trace fRF = 20 MHz, blue trace fRF = 100 MHz. fsample = 10.949 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42

Sampled data, channel Reference (CH1) and Cavity Forward (CH2). Red bars are the raw undecimated data, blue bars after decimation by factor 8 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43

52

53

Sampled data, channel Cavity Reflected (CH3) and Antenna (CH4). Red bars are the raw undecimated data, blue bars after decimation by factor 8 192 43

54

Residual noise on the magnitude measurement. fsample = 10.949 MHz, decimation by 8 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

44

LIST OF FIGURES

55

Digital Measurement System

Residual noise on the magnitude measurement. fsample = 10.949 MHz, decimation by 8 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

44

Cavity resonant frequency during the tuning transient as captured by the Measurement system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

44

57

FFT of the tuning transient showing the mechanical modes of the cavity .

45

58

Frequency response of the warm HIE-Isolde cavity, measured by the developed Cavity measurement system . . . . . . . . . . . . . . . . . . . . . . .

45

59

VME crate with all modules discussed and developed for this thesis . . . .

47

60

Warm cavity test stand the night before submitting this thesis . . . . . . .

47

56

v

LIST OF TABLES

Digital Measurement System

List of Tables 1

CD Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

50

1. INTRODUCTION

1

Digital Measurement System

Introduction

Particle accelerator is a device that uses electromagnetic fields to propel charged particles to high speeds and to contain them in a form of spatially well-defined beams [7]. A very simple particle accelerators based on a DC acceleration were used by scientists already in the 19th century. The final energy obtainable by the DC acceleration technique is however limited so a new generation of radio frequency powered accelerators was developed in the 1920s. Two principal classes exist - the linear accelerators (linac) and the circular accelerators. In case of linacs the particles are accelerated and pass through the whole machine exactly once. The linac is typically constructed in one straight line, but machines with bends also exist. The beam is either extracted to the next machine, shot to a fixed target or collided with beam from another accelerator. In contrary the circular accelerators feature a closed beam trajectory. The beam is injected and circulates in the machine for many turns. Depends on type, the beam trajectory is either fixed (synchrotrons) or it is function of a beam energy (cyclotrons). The beam could be either accelerated and extracted to the next user, or could be simply stored for a long periods of time. Both accelerator types have characteristic properties determining their function. The linear accelerators are typically very well suited for acceleration of a low energy beams when the speed of particles still significantly increases (β "LVDS_25" DIFF_TERM => TRUE B_MHz100_GBuf B_MHz100_IBuf FPGA_MHZ100_P MHz100x clk G FPGA_MHZ100_N IOSTANDARD => "LVDS_25" DIFF_TERM => TRUE B_MHz50_GBuf FPGA_MHZ50_P B_MHz50_IBuf MHz50x clk G FPGA_MHZ50_N

QZ_SCLK QZ_SDO MHz100

MHz50

LVDS3_N

SF

S

MHz50

S MHz10

IOSTANDARD => "LVDS_25" DIFF_TERM => TRUE

QZ_SDIO

G

S SFP1_RXDA

MHz10 POR

B_MHz10_GBuf

B_MHz10_IBuf MHz10x clk

QZ_CS_N

SFP0_RXDAT

5. MEASUREMENT CARD LVDS3_P

QZ_CS_N

MHz100

QZ_SCLK QZ_SDO

IODelayRdy

POR

Backplane signals (LVDS) Digital Measurement System

QZ_SDIO

LVDS4_P

IODelayRdy

LVDS4_N

IOSTANDARD => "LVDS_25" DIFF_TERM => TRUE

C24

LVDS2_P LVDS2_N

D

ADC_DATA1_P (8:0)

ADC_Data1 (14:0)

R Frev

Bit 14 : OR

ADC_SCLK

ADCIntfce

ADC_SDIO ADC_CS_n

B_ADCIntfce2 ADC_Data2

ADC_DATA2_P (8:0)

IOSTANDARD => "LVDS_25" DIFF_TERM => TRUE

ADC_Data1

ADC_SYNC

B

C22 D

B_ADCIntfce1

ADC_DATA1_N (8:0)

S

Fc

IOSTANDARD => "LVDS_25" DIFF_TERM => TRUE

ADC Interface LVDS receiver and DDR decoder

S

R

F

F

ADC_SCLK ADC_SDIO ADC_CS_n (4:1)

P

ADC_SYNC (4:1)

P

ADC_Data2 (14:0)

ADC_DATA2_N (8:0)

IQ demod ADC's Bit 14 : OR ADCIntfce ADC_Data3

F

B_ADCIntfce3 ADC_DATA3_P (8:0)

ADC_Data3 (14:0)

ADC_DATA3_N (8:0)

F Bit 14 : OR

ADC_Data4

ADCIntfce B_ADCIntfce4 ADC_DATA4_P (8:0) ADC_Data4 (14:0) ADC_DATA4_N (8:0) Bit 14 : OR ADCIntfce B_IDelayCtrl MHz200 POR

REFCLK RST

RDY

IODelayRdy

IO_IDelayCtrl

Figure 28: LVDS receiver and DDR decoder as a chip specific primitives defined on the ChipTop level 1 IDelayctrl per clock regions where the IOdelay are used.

also all necessary XML files for automatic driver generation, skeleton for the FESA classes and integrates the design in the control system. The tool significantly shortens the design time and reduces chances of errors. Cheburashka user interface is shown in Figure 29. Output of the Visual Elite is a single generic VHDL file. It is then loaded into the Synplify tool, which does all the optimizations and translations from the generic VHDL code into a device specific EDIF format (Electronic Data Interchange Format). It contains the design netlist with pre-mapped blocks in an industry standard form. This optimized netlist file is then loaded into the Xilinx ISE tool which does the place and route and timing analysis. The bitstream is than either directly loaded into the FPGA, or converted into a PROM file and flashed into the onboard PROM memory using the Xilinx iMPACT tool. A complete firmware design flow used in the BE/RF/FB section is sketched in Figure 30. 5.3.1

Decimator and demodulator VHDL block

Relatively low required feedback loop bandwidth (hundreds of Hz) and a need of high sampling frequency due to the ADC limitations (> 10 MHz) allows us to heavily decimate the input data (by a factor of 210 ) lowering the noise while still fulfilling the Nyquist criterion. A decimator with simple rectangular window is suitable for our application. The

Design: HIE_measCard:ChipTop

Date: T

22

5. MEASUREMENT CARD

Digital Measurement System

Figure 29: VME memory map in the Cheburashka software transfer function of this decimator is described by (2) and (3). IOU T =

QOU T =

1

DF −1 n=2X

2DF +1

n=0

[y(4n) − y(4n + 2)]

(2)

[y(4n + 1) − y(4n + 3)]

(3)

1

DF −1 n=2X

2DF +1

n=0

where y(n) is the input data stream from the ADC, DF the decimation factor and IOU T , QOU T the output data streams at a reduced data rate of 2DF1 +2 . This decimation algorithm was implemented in the VHDL language and synthesized into the Virtex 5 FPGA. Basic operational principle is the following - the data are sampled with ADC clock rising edge, modified to a proper bus format/size and enter decimation block. There, depending on the decimation factor, are sorted into I and Q samples, rescaled and stored into the accumulators. When defined number of I and Q samples is collected, value of those temporary registers is divided by a number of accumulated data samples, copied to the output port, and DecimMarker (Data valid) strobe is asserted. This strobe is synchronous with the ADC clock, common for all ADCs and always lasts exactly one clock period. The strobe is used as a signal to inform the memory block that processed data 23

5. MEASUREMENT CARD

Digital Measurement System

C driver generator

Cheburashka

FESA class

C++ compiler

VME embedded computer

VHDL VHDL

EDIF

Visual Elite

bitstream

Synplify

USB

Xilinx ISE

Xilinx iMPACT

Xilinx Platform Cable

JTAG

FPGA, PROM

VHDL HDL Simulator

Figure 30: Firmware development design flow. Blue blocks show the hardware development, green blocks the software development should be stored into the external SRAM memory using memory controller or a calculation on those data should be performed. The decimated and demodulated I and Q data are converted from the cartesian to a polar format using VHDL implementation of a CoRDIC algorithm [20] (in our case pipelined core). The phase and magnitude of each channel is normalized using the reference channel. In the measurement card this is so far end of the signal processing, as we need only to observe the signals. In the future feedback controller these will be the error signals in a feedback loop to generate the accelerating voltage in the cavity. All those post processed signals can also be stored into the external (circular) memory buffers, and frozen at any time to readout any part of the buffers using VME bus. C663

adc1Gain (15:0)

C696

Rst

D

ADCLK

C697

S1405

Q

D

Q

ADCmux (15:0)

S1408

D

ADCLK

CLK

C680

adc2Gain (15:0)

C698

Q

C681 DecFactor (3:0)

adc1Gain(3:0)

RstFalling

Q

ADCLK

CLK

CLK

C684 ADCLK one C687

RstFalling

Sync

Ch1Q (15:0)

Q_out

CH1decQ (15:0)

DecimMarker

Data_valid

zero C699

ADC_data

DecFactor (3:0)

Dec_factor Demodulator & Decimator

ADCLK

Clk

Rst

ADC_Data1(13:0)

Rst

zero ADC1raw (15:0)

ADC_Data1(14)

zero

Rst

ADC_data1ex (15:0)

ADC_Data1 (14:0)

Ch1I (15:0)

I_out

Clk_en

DecimatorSync

'0'

CH1decI (15:0)

Clk

C560

'0'

RstO

LimXin LimX

zero

LimYin LimY

O

Ch1Val

MarkerIn MarkerOut

C523

S1602 (15:0)

Loc_adc1OR

C703

X"0000" CorMode

C704

Vector

C705

Circular

CorSubm

X0

Xn

Y0

Yn

Z0

Zn

Ch1Mag (15:0) Ch1MagObs (15:0)

Ch1PhObs (15:0) Ch1Phase (15:0)

CorMode CorSubm CoRDICPipe

Figure 31: Decimation and CoRDIC blocks in the Visual Elite environment C686

ADCLK one DecimatorSync RstFalling ADC_data2ex (15:0) DecFactor (3:0)

Clk Clk_en Sync

CH2decI (15:0)

I_out Q_out Data_valid

Ch2Q (15:0) CH2decQ (15:0)

S1576 zero

Rst C707

ADC_data Dec_factor Demodulator & Decimator

ADCLK Rst zero zero

ADC_Data2 (14:0) ADC_Data2(13:0)

C561

Clk Rst

RstO

LimXin LimX LimYin LimY MarkerIn MarkerOut

ADC2raw (15:0) ADC_Data2(14)

zero

Ch2I (15:0)

'0'

S1123 C524

S1620 (15:0) C706

Loc_adc2OR

X"0000" CorMode CorSubm

C688

X0

Xn

Y0

Yn

Z0

Zn

24

Ch2Val Ch2Mag (15:0)

Ch2MagObs (15:0)

Ch2PhObs (15:0) Ch2Phase (15:0)

CorMode CorSubm CoRDICPipe

CH3decI (15:0)

5. MEASUREMENT CARD

Digital Measurement System





architecture V1 of DemodDecimator is constant DecimInit : natural := 2**15-1; constant Zero : signed(28 downto 0) := (others => ’0’); signal Iacc, Qacc : signed(28 downto 0); signal IQstate : natural range 0 to 3; signal DecimCounter : natural range 0 to DecimInit; begin process(Clk, Rst) begin if rising_edge(Clk) then if Rst = ’1’ or Sync = ’1’ then IQstate