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3D Flash/CT memories Daniele Ielmini DEI - Politecnico di Milano, Milano, Italy
[email protected]
Flash scaling overview 1. Flash scaling:
T. Kamaigaichi, et al., IEDM Tech. Dig. 2008
www.micron.com Feb. 26, 2010
2. Evolutionary scenario:
H. Tanaka et al., VLSI Symp. 2007
3. Paradigm shift
M. Lee, et al., IEDM Tech. Dig. 2007 D. Ielmini, "Non volatile memories" – 3
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3D memories • 2D memory stacking: – NAND stacking (Samsung, 2006) – TFT NAND (Macronix, 2006)
• 3D charge trapping memories – Bit cost scalable (BICS) memory (Toshiba, 2007) – Terabit Cell array transistor (TCAT) memory (Samsung, 2009)
• Resistive-based crossbar arrays Feb. 26, 2010
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Multichip package • This is a ‘fake’ 3D technology: the cost is not reduced (cost is proportional to manufactured area, not package area), only the package area/thickness is affected (attractive for handsets, MP3 players, etc.) • e.g. the Samsung 64GB moviNAND measures 1.4 mm in height, consists of 16 30nm-class 32Gb MLC NAND chips and a controller. The 17-die stack was achieved by using 30-micron thick chips (0.03*17 = 0.51mm) and advanced package technology Feb. 26, 2010
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3D NAND • Stacking of NAND layers (not chips) in a single chip • Motivation: further cost reduction
EUV
• In fact, cost scaling slows down because of lithography limitations (immersion litho, double/triple/quadruple patterning, or EUV with huge investments and reduced throughput) • 3D allows less aggressive F scaling better reliability • Stacking (and 3D) has better costs by avoiding advanced litho tools and adopting relaxed F Feb. 26, 2010
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3D NAND
• 2nd layers is SOI with epitaxial Si on ILD • 63 nm TANOS technology, erase by source (thin body does not allow erase by body bias) S. M. Jung, et al., IEDM Tech. Dig. 2006 Feb. 26, 2010
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3D NAND layout
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Reliability impact
• No degradation seen in 2nd layer • P/E characteristics not degraded either Feb. 26, 2010
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TFT 3D NAND
60 nm
90 nm
E. K. Lai, et al., IEDM Tech. Dig. 2006
• Alternative: poly-Si finFET BE-SONOS (Macronix, 2006) • polySi TFT: a-Si LPCVD + 600°C annealing • tSi = 60 nm, W G = 90 nm, LG = 200 nm Feb. 26, 2010
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Reliability
• Reasonable reliability, no significant degradation in the top layer Feb. 26, 2010
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Impact of grain boundary (GB)
T.-H. Hsu, et al., IEDM Tech. Dig. 629, 2009
• tSi = 50 nm, WG = LG = 30 nm • Annealing of 600°C for 30 hours results in 200 nm average grain size 30 x 30 nm2 channels can be marginally affected Feb. 26, 2010
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TFT vs. bulk devices • Large TFT devices are worse than bulk (GB effect) • Small TFT devices are similar to bulk, because of nearly zero GB • Bad P/E distributions due to GB statistics GB distance
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3D (stacked) NAND limits • One decoder for each layers area overhead • Critical (and costly) litho steps to make minimum feature size are necessary for each layer • Epy-Si layer is a high temperature process number of stacked layers is limited by thermal budget A simpler, cheaper 3D architecture is needed
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2D NAND architecture BL1
string1
DSL WL1 WL2 WL3 SSL
string2
• NAND is inherently 3D: DSL – BL coordinate x WL1 WL2 – String coordinate y WL3 SSL – WL coordinate z • In planar NAND, BL and string along the same direction • 3D NAND is straightforward Feb. 26, 2010
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Bit-cost scalable (BiCS)
• BL (x) and upper SG (y) select a vertical string • Planar WL (z) select a single cell along the string • String area = 6F2, cell area = 6F2/N Feb. 26, 2010
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Process sequence • String in three steps (lower SG plug + memory plug + upper SG plug) • Slit to reduce disturbs • Only one critical litho step = memory plug • CG formation:
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String
• Punch + plug polysilicon for best hole filling • Undoped or n- doped depletion mode vertical FETs to avoid separate n+/p+ doping Feb. 26, 2010
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From 6F2 To 4F2
• BL have 2F pitch, USG have 3F pitch since they must surround the plug (2x0.5F) and be isolated (F) • 2-layer USG can achieve 2F pitch 4F2 string area Feb. 26, 2010
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Program/erase • Program: – select strings by USG+BL – High CG for e- injection from poly-channel • Erase: – High BL/SL, CG = 0 – BBT holes by GIDL at n+SL/LSG – Holes populate poly channel and raise body potential – Holes injection into charge traps Feb. 26, 2010
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Program/erase characteristics
• P/E window improves for decreasing diameter, as a result of the larger E-field in the inner oxide for small diameter Feb. 26, 2010
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Macaroni channel
• Better control of body potential better STS • Higher density of grain boundaries better VT distribution Feb. 26, 2010
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Reliability issues
• Retention to be improved (SONS dielectric stack, ONO oxide would be damaged by HF diluted etch used to improve poly-poly contact in the plug) • Limited scaling of macaroni FET • Charge migration in the trapping layer mitigated by channel length in the z direction no limits Feb. 26, 2010
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Advantages over 3D NAND 3d nand layers =
bc =
BiCS layers =
bc =
1 2 1 4 22 nm 2 2 2 1 3 1,333333 0,666667 4 1 0,5 1 1 6 2 3 3 2 4 1,5 5 1,2 6 1 7 0,857143 8 0,75 9 0,666667 10 0,6 11 0,545455 12 45nm 0,5 13 0,461538 14 0,428571 15 0,4 16 0,375
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2 3 1,5 1 0,75 0,6 0,5 0,428571 0,375 0,333333 0,3 0,272727 0,25 0,230769 0,214286 0,2 0,1875
3 4 1,333333 1 0,666667 0,5 0,444444 0,333333 0,333333 0,25 3 2 1 0,666667 0,5 0,4 0,333333 0,285714 0,25 0,222222 0,2 0,181818 0,166667 0,153846 0,142857 0,133333 0,125
4 1,5 0,75 0,5 0,375 0,3 0,25 0,214286 0,1875 0,166667 0,15 0,136364 0,125 0,115385 0,107143 0,1 0,09375
• 3D NAND = 4F2 while BiCS = 6F2 3D NAND better for 1 layer only • 12 layer-BiCS is equal to 2 layers – 4bc 3D NAND • 12 layer-BiCS is equal to 1 layer – 2bc at half F (e.g. 22 nm instead of 45 nm) when planar Flash will be no more scalable (e.g. 10 nm), BiCS will show up in a previous technology node (e.g. 50 nm)
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Cost comparison
• Cf is relatively large for BiCS (USG, BSG, punch and plug) • Cv is relatively large for 3DNAND (each layer must replicate DSL and SSL, drivers, etc.) • Yield degradation for 3DNAND (epi-Si deposition with high thermal budget) Feb. 26, 2010
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Pipe-shaped BiCS •
Some problems to be addressed: 1. Bad reliability because of SONS 2. Series resistance due to diffused source line 3. Uncontrollable LSG due to thermal budget • Pipe-shaped BiCS solves these issues
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Reliability improvement
• Reliability improvement thanks to SONOS instead of SONS structure (poly is plugged all at once, no need for HF etch) Feb. 26, 2010
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Other issues and solutions • Other issues include: – Gate material is p+ polysilicon, no metal gate (e.g. W or TaN as in TANOS) can be integrated because of etching limitations – Erase: GIDL at VG < 0 needed circuit overhead
• Those issues are solved by Terabit Cell Array Transistor (TCAT), the Samsung answer to BiCS
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Terabit Cell Array Transistor (TCAT)
• Very similar to BiCS but: – Gate-last process where sacrificial nitride is replaced by metal gate (W) Feb. 26, 2010
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Gate-last process
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Program/erase characteristics
• P-doped channel connected to the substrate allows for bulk erase similar to NAND (not in BiCS with n-channel tied to n+ source) • Erase saturation at VT = -1 V to be improved by diameter scaling Feb. 26, 2010
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