Course AE0B38APH - FPGA Application Introduction into VHDL, VHDL design units

Lecture topic 2

AE0B38APH ‐ FPGA Applications

1

What is a VHDL ?

Standard for …

 VHDL – VHSIC (VHSIC – very-high-speed integrated circuit) Hardware Description Language  Originally developed for US Department of Defense (1981)  Main idea: development of language that will be portable between all producers of VHSICs, ASICs, FPGAs …etc.  Can be used for documentation, simulation and verification  1987 - first standardization: IEEE Standard 1076-1987  1994 - next improvement: IEEE Standard 1076-1993 – brings 9valued of logic for signals (U,X,0,1,Z,W,H,L,-)  1999 – add extensions for analog and mixed-signal mixed signal  Text oriented language g g with reserved Keywords y AE0B38APH ‐ FPGA Applications

2

Reserved Keywords in VHDL Reserved words in VHDL abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant

disconnect downto else elsif end entityy exit file for function generate generic group guarded if impure in inertial inout

AE0B38APH ‐ FPGA Applications

is label library linkage literal loop p map mod nand new next nor not null of on open or others

out package port postponed procedure process p pure range record register reject return rol ror select severity signal shared sla

sli sra srl subtype then to transport type unaffected units until use variable wait when while with xnor xor

3

VHDL standard IEEE 1076    

VHDL is non-case sensitive !!! Symbol semicolon(;) ends command Symbols double dash (--) - comments VHDL does not support automatic data type conversion – there are a lot of conversion functions (e.g. (e g CONV_STD_LOGIC_VEC CONV STD LOGIC VEC)

 Standard defines:    

data types variables or signals logic, arithmetic and relation operations of course Possibility to work in sequence or parallel domain

 Bas Basic c language construct constructions: ons

 While and For loops  If then, if then else, elseif end commands  Case when end case command

AE0B38APH ‐ FPGA Applications

4

Design entity – basic unit of VHDL  Design entity – primary hardware abstraction in VHDL it represents a portion of hardware design that VHDL, well-defined inputs and outputs and performs a welldefined f function f  It may represent an entire system, a subsystem, a board, a chip or macro-cell  Whole design may be composed from many entities, only one must be tagged as top-entity

AE0B38APH ‐ FPGA Applications

5

Entity declarations Entity identifier is entity_header tit h d entity_declarative_part [ begin b i entity_statement_part ] end d [entity] [ ] [entity_simple_name l ];

AE0B38APH ‐ FPGA Applications

6

Entity header Generic ( generic_list ) ; P t ( port_list Port t li t ) ; Type Generic: T G i used d for f constants t t Type Port : in – data are only read from inputs The most  often  out – data d is written to output used inout – communication in both directions other possibilities: buffer, linkage

AE0B38APH ‐ FPGA Applications

7

Entity declarative part entity_declarative_item : subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | signal_declaration g |shared_variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | disconnection_specification _ p | use_clause | group_template_declaration |g group_declaration p_

AE0B38APH ‐ FPGA Applications

8

Example: An entity declaration with entity declarative items items: Entity ROM is Port (Addr: in Word; D t outt Word; Data: W d Sel: in Bit); Type Instruction is array (1 to 5) of Natural; type Program is array (Natural range ) of Instruction; use Work.OpCodes.all, Work.RegisterNames.all; constant ROM_Code: _ Program g := (

); end ROM;;

(STM, R14, R12, 12, R13) , (LD R7, (LD, R7 32, 32 0, 0 R1 ) , (BAL, R14, 0, 0, R7 ) , • • -- etc. etc •

AE0B38APH ‐ FPGA Applications

9

Entity statement part concurrent_assertion_statement | passive_concurrent_procedure_call | passive_process_statement i t t t

AE0B38APH ‐ FPGA Applications

10

Example: Entity declaration part with statements entity Latch is port ( D Din: n in n Word; Wor ; Dout: out Word; Load: in Bit; Clk: in Bit ); constant Setup: p Time := 12 ns; constant PulseWidth: Time := 50 ns; use Work.TimingMonitors.all; begin assert Clk='1' or Clk'Delayed'Stable (PulseWidth); CheckTiming (Setup, Din, Load, Clk); end ;

AE0B38APH ‐ FPGA Applications

11

Architecture – body of entities Architecture – defines entity behaving I more complex In l cases - can be b entry t more architectures hit t for one entity

architecture identifier of entity_name entity name is architecture_declarative_part b i begin architecture_statement_part end d [ architecture hit t ] [ architecture_simple_name hit t i l ] ;

AE0B38APH ‐ FPGA Applications

12

Architecture declarative part block_declarative_item subprogram_declaration | subprogram_body | type_declaration | subtype_declaration bt d l ti | constant_declaration | signal_declaration | shared_variable_declaration shared variable declaration | file_declaration | alias_declaration | component_declaration p _ | attribute_declaration | attribute_specification | configuration_specification | disconnection_specification di i ifi i | use_clause | group_template_declaration | group_declaration group declaration

AE0B38APH ‐ FPGA Applications

13

VHDL example code: AND gate

Library  declaration

Input and  output  d l declaration

Block defines  behaving entity  ANDGATE

AE0B38APH ‐ FPGA Applications

14

VHDL example code : Counter Library  declaration Input and  output  declaration

Block defines  behaving entity  ANDGATE

AE0B38APH ‐ FPGA Applications

15

STD_logic_1164 Package  For using that libraty project must include the following lines: Library ieee; use ieee.std_logic_1164.all;

 Defines basic types: std_logic, std_logic_vector, std_ulogic, std_ulogic_vector  And 9 9-level level of logic values values:         

'U' - uninitialized 'X' - strong drive, unknown logic value '0' 0 - strong drive, drive logic zero '1' - strong drive, logic one 'Z' - high impedance 'W' W - weak drive, drive unknown logic value 'L' - weak drive (pull-up, pull-down resistors), logic zero 'H' - weak drive (pull-up, pull-down resistors), logic one '-' - don don'tt care

AE0B38APH ‐ FPGA Applications

16

Any questions

AE0B38APH ‐ FPGA Applications

17