Correlated electron Random Access Memory: Physical Design, Realization, and Characterization by Christopher R. McWilliams B.S. Electrical Engineering, University of Colorado Colorado Springs, 2008
A thesis submitted to the Faculty of the Graduate School of the University of Colorado in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical and Computer Engineering 2013
c
Copyright by Christopher R. McWilliams 2013 All Rights Reserved
This thesis entitled: Correlated electron Random Access Memory: Physical Design, Realization, and Characterization written by Christopher R. McWilliams has been approved for the Department of Electrical and Computer Engineering
Carlos A. Paz de Araujo
Thottam S. Kalkur
Zbigniew Celinski
Date
The final copy of this thesis has been examined by the signatories, and we find that both the content and the form meet acceptable presentation standards of scholarly work in the above mentioned discipline.
iv McWilliams, Christopher R. (M.S., Electrical Engineering) Correlated electron Random Access Memory: Physical Design, Realization, and Characterization Thesis directed by Prof. Carlos A. Paz de Araujo
The device fabrication process, switching properties and characterization of Correlated Electron Random Access Memories (CeRAMs) are described herein. Film synthesis techniques, test pattern process flows, High temperature retention, Cycle dispersion and optimization, Cycle Fatigue, and switching parameter optimization have been investigated. CeRAM’s display initially conductive or “Born-ON” behavior without the need for the high electroforming voltages usually required for other TMO based resistive memories. Nonvolatile data retention at elevated temperatures up to 300◦ C in addition to a wide operating range from -269◦ C to 150◦ C for CeRAM has been confirmed. CeRAMs also show exceptional read endurance with no evidence of fatigue out to 1012 cycles. Desirable scaling characteristics for high density memory application have also been shown for CeRAMs due to a widening of the read window and consistent write window as devices are scaled down. Characterization of these device parameters and device modeling, using the fundamental physics of Mott and charge transfer insulators, is the central point of this thesis.
Dedication
I dedicate this work to my loving family.
vi
Acknowledgements
This research would not have been possible without the involvement and support of many people. First and foremost, I am deeply indebted to my academic adviser and mentor Dr. Carlos A. Paz de Araujo. I give you my heartfelt thanks for your guidance in this work and countless hours of discussion on the topics included within this thesis and crucial to the understanding of my research both academically and professionally. I would like to express my sincerest gratitude to Ms. Jolanta Celinska. Without your contributions in materials synthesis and our mutual research interests, this thesis would have been impossible. I have greatly enjoyed the opportunity of working with you over the past several years and look forward to a long and rewarding friendship. I would like to thank Dr. Orlando Auciello and his teams of scientists both currently at the University of Texas at Dallas, and formerly at Argonne National Laboratories. Throughout this research you have graciously provided valuable resources and expertise necessary for the understanding and improvement of materials and devices studied for the research included in this thesis.
Contents
Chapter 1 Introduction 1.1
1.2
1
Non-volatile Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.1.1
Floating Gate and Charge Trap Memories . . . . . . . . . . . . . . . . .
3
1.1.2
Ferroelectric Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
1.1.3
Resistive Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Scope of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
2 Review of The Current Status of Resistive Memory Technology 2.1
10
Material Properties and Device Performance . . . . . . . . . . . . . . . . . . . .
11
2.1.1
Chalcogenides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2.1.2
Binary Metal Oxides . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.1.3
Perovskites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.1.4
Solid-State Electrolytes . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.1.5
Organic and Molecular Systems . . . . . . . . . . . . . . . . . . . . . . .
13
2.2
Mechanism for Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.3
Challenges of RRAM Development . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.3.1
Materials Issues of Resistive Memories . . . . . . . . . . . . . . . . . . .
16
2.3.2
Reliability Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
viii 3 Electronic Phase Transitions in Correlated Systems
20
3.1
Non-Interacting Electrons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
3.2
Mott Insulators and the Mott Transition . . . . . . . . . . . . . . . . . . . . . .
23
3.3
The Hubbard Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
3.4
Green’s Functions
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Transport in Nanoscale Oxide Devices 4.1
4.2
33
The MIM Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
4.1.1
Potential energy and Image force . . . . . . . . . . . . . . . . . . . . . .
33
4.1.2
MIM current equations . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Transport During the Phase Transition . . . . . . . . . . . . . . . . . . . . . . .
37
5 CeRAM
41
5.1
The CeRAM Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
5.2
Device Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
5.3
Characterization and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
5.3.1
Physical and Chemical Characterization . . . . . . . . . . . . . . . . . .
48
5.3.2
Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
5.3.3
Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
Modeling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
5.4.1
Circuit simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
5.4.2
device modeling
81
5.4
6 Summary and Outlook
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
ix Bibliography
94
Appendix A Code for simulations
101
B Derivations
107
B.1 MIM Diode current simplification . . . . . . . . . . . . . . . . . . . . . . . . . . 107 B.2 Tunneling Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 B.3 LRS Current equatinon derivation . . . . . . . . . . . . . . . . . . . . . . . . . 108
x
Tables
Table 2.1
RRAM Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
5.1
SR Latch Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
xi
Figures
Figure 1.1
Crystal structure unit cell of a cubic perovskite (ABO3 ) Ferroelectric material.
6
1.2
Typical ferroelectric Polarization vs. voltage hysteresis loop. . . . . . . . . . . .
7
2.1
Table with highlighted materials used for RRAM devices in the literature . . .
18
3.1
band diagram for NiO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
3.2
Mott-Hubbard metal-insulator transition. . . . . . . . . . . . . . . . . . . . . .
27
3.3
Mott-Hubbard vs. charge transfer insulator energy band structure. . . . . . . .
28
4.1
Total Potential Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.2
MIM diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
4.3
Schematic of the system described within the Landauer approach . . . . . . . .
38
4.4
Diode current vs. applied bias for a symmetric diode with charge near the Fermi level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Total MIM current with Diode current, Thermionic, and Tunneling current contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
40
40
3-D Crystallographic representation of the (a)NiO octahedral and (b)Ni(CO)4 structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
5.2
The CeRAM MIM-cap test structure. . . . . . . . . . . . . . . . . . . . . . . .
44
5.3
Illustration of process flow for CeRAM test structure. . . . . . . . . . . . . . .
45
xii 5.4
CeRAM test structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
5.5
XPS Spectra for Ni 2p energy spectrum in carbonyl ligand doped NiO CeRAM
49
5.6
XPS Spectra for O 1s energy spectrum in carbonyl ligand doped NiO CeRAM
50
5.7
SEM image at 20,000x magnification of defect and surface morphology Nickle Oxide based CeRAM CSD film.
5.8
. . . . . . . . . . . . . . . . . . . . . . . . . .
51
AFM topography scans for NiO films deposited using different precursor molarities (scan size: 2µm)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
HRTEM image of CeRAM cross-section . . . . . . . . . . . . . . . . . . . . . .
52
5.10 STEM image of CeRAM cross-section . . . . . . . . . . . . . . . . . . . . . . .
53
5.11 Electron energy loss spectrum scans for CeRAM sample . . . . . . . . . . . . .
54
5.12 EELS line scan of CeRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
5.13 LabVIEW GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
5.14 Pulse switching GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
5.15 CeRAM testing equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . .
59
5.16 Load resistor compliance circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
5.17 1T1R MOSFET compliance circuit . . . . . . . . . . . . . . . . . . . . . . . . .
62
5.18 Cascode current mirror compliance circuit . . . . . . . . . . . . . . . . . . . . .
64
5.9
5.19 Typical I-V characteristics for (a)bipolar and (b)unipolar switching by voltage sweep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
5.20 Reset current vs. Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
5.21 On resistance vs. compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
5.22 I-V curves for CeRAM cell programmed using a 50µA compliance limit showing a max IReset of approximately 70µA. . . . . . . . . . . . . . . . . . . . . . . . .
69
5.23 200 ms Reset pulse, 50 cycles Switching Reliability: 98% . . . . . . . . . . . . .
70
5.24 MOSFET transistor curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
5.25 Average read voltage across a 50Ω sense resistor for reset pulse widths of (a) 200 ms, (b) 100 ms, and (c) 50 ms. . . . . . . . . . . . . . . . . . . . . . . . . .
72
xiii 5.26 ROn and ROf f resistance of 100 consecutive cycles at room temperature and the corresponding read margin. . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
5.27 Read endurance for high(ROf f ) and low(ROn ) resistance states of a (10×10)µm2 cell at room temperature with 0.2V read voltage. . . . . . . . . . . . . . . . . .
74
5.28 Nonvolatile data retention of high and low resistance states at elevated temperatures up to 300◦ C for 1 hour. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
5.29 Full I-V hysteresis measurement showing bi-stable behavior at operating temperatures (a) -269 ◦ C (b) 25 ◦ C and (c) 150 ◦ C. . . . . . . . . . . . . . . . . . .
76
5.30 Circuit schematic representation for CeRAM SPICE model . . . . . . . . . . .
77
5.31 Pulse simulation of CeRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
5.32 Circuit schematic representation of CeRAM memory array in standard and common source 1T1R configurations . . . . . . . . . . . . . . . . . . . . . . . . . .
80
5.33 simulation input stimulus for simulation 4x4 array in 1T1R circuit configuration 80 5.34 Simulation output for 4x4 array in 1T1R circuit configuration . . . . . . . . . .
81
5.35 Schematic representation of the CeRAM I-V device model.
82
. . . . . . . . . . .
5.36 Thermionic emission, Poole-Frenkel, and square root dependent plots of experimental data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
5.37 Conductive state current of a CeRAM element vs. applied bias. . . . . . . . . .
88
5.38 CeRAM Device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
5.39 Modeled and Experimental J-V characteristics for CeRAM . . . . . . . . . . .
89
Chapter 1
Introduction
Over the past 10 years, significant advancements have been made in the development and research of devices based on resistance change in an effort to meet the requirements of high density standalone memory for future technologies. Due to the potential benefits of these devices from their simple operation, promising scaling potential, CMOS compatibility and ultra high density arrays through the use of 3D architectures[1],[2] these devices have received notable consideration from the research community. Although more recent research has come a long way toward it’s application, the observation of thin films of metal-oxide materials undergoing a transition from an insulator to a conductive state dates back more than 50 years. The first reports of this resistive switching behavior were published in the 1960s and 70s [3, 4, 5, 6]. The phenomenon dates back even further when considering the bulk material metal-insulator transition observations by Mott 1949 [7]. Resistance switching properties have been observed in a variety of materials [8, 9, 10, 11, 12, 13, 14, 15] for the last decade. The focus of this research was centered around NiO primarily for it’s ease of integration due to the industry trend of using nickel silicide contacts in 65nm and below technology nodes. For the realization of resistive memories often referred to as Resistive Random Access Memories (RRAMs), two issues continue to delay their commercialization. Firstly, high current in the conductive state and secondly, the high electroforming voltages that produce random filaments across nanoscale thin films of these materials.
2 The starting point to force the charge transfer transition to be the dominant device physics is to control the NiO stoichiometry with Ni(CO)4 (i.e., Nickel Carbonyl doping). Carbonyl complexes stabilize the oxygen vacancies resulting in a pure Mott (CT) transition system. Thus, as the Metal-Insulator Transition (MIT) is exploited from the strong electron-electron correlation formed in Mott insulators; the physics of CeRAM departs considerably from that of RRAMs. Furthermore, RRAMs have thus far fallen into a device paradigm that depends on the formation of “filaments,” i.e., metallic pathways that can be connected/disconnected via an electrochemical process near the anode. In this work, a novel approach which uses the Mott-like charge transfer (CT) properties of NiO is pursued. As described above, CeRAMs are resistive random access memories that are based on a Mott-like charge transfer metal-insulator transition in NiO, a well known TMO. Due to the large area/thickness ratio, a large number of defects plague the stoichiometric balance. To compensate for these defects, the Ni(CO)4 was developed. It is well known that strong electron correlations exist in the bulk phase of such materials as described by Mott and Hubbard [7], [16]. In the case of ultra thin films, compensation of charge effects in the large surface to volume ratio is needed to achieve an electroforming free device. In our case a large change in the device resistance between “On” and “Off” states occurs. An appropriately configured device exhibits hysteresis and non-volatile characteristics, for which stable memory switching can be controlled. Such stable systems based only on dorbital electron correlation and not charge trapping are central to the CeRAM concept, i.e. absent of electroforming and defect compensation to isolate the Mott quantum phase transition. Earlier work in this area is shown in refs. [17] and [18] respectively.
1.1
Non-volatile Memories Non-volatile memory defines a class of computer memories that is able to maintain stored
data in the interruption or continued absence of a supplied power. Non-volatile memory, like all traditional semiconductor memories, falls into one of four memory classifications or a
3 combination of two or more of them. These types of memories are described below: I Random Access Memory (RAM) which can be accessed very quickly and at any random memory location and contain subclasses of memories such as Dynamic RAM (DRAM), Static RAM (SRAM), and certain types of read only memory (ROM). II Sequential Access Memory (SAM) in which memory cells are addressed and accessed in chronological order and the access times are highly dependent on the address of the accessed memory cell. Modern technology examples of SAM devices include magnetic memory such as hard disks and tape drives and optical memories like CD-ROM’s. III Content Addressable Memory (CAM) in which memory cells are addressed and accessed by searching for specific data and return the address(es) of that data. Access times are very fast, but the applications of such a memory are limited and are typically used in microprocessors for cache memory applications. IV Read Only Memory (ROM) which can either not be modified once initially written or can be modified slowly and with some level of difficulty. Although most forms of ROM are considered randomly accessible and therefore fall under the RAM classification, it is important to note that that ROM memories are alternatively grouped by their ability or inability to be written and re-written as opposed to their accessibility.
1.1.1
Floating Gate and Charge Trap Memories
Memories based on floating gate technology (FG) with charge trapping such as FLASH are currently the leading edge for mass storage application. At present, NAND FLASH is the state of the art in the Electrically Erasable Programmable Read-Only Memory (EEPROM)
4 class of memories due to its memory cell being smaller than conventional EEPROMs; this is accomplished by eliminating the pasgate transistor of the conventional EEPROM cell. The downside of this scheme is that even though they are state of the art at current 5V and even 3.3V silicon logic levels, as the nodes shrink and the standard levels inevitably decrease to 1.1V and even 0.5V over the next several years FLASH memories, which are based on Fowler-Nordheim tunneling, will no longer function reliably. One fundamental cause for this loss in reliability is simply due to the fact that as the technology node and thus the physical dimensions of the FG decrease, the total number of electrons stored in that FG gets smaller and smaller. Retention requirements must account for the loss of a few electrons each year decreasing total data storage retention time and further, it is important that sufficient trapped charge in the FG to ensure that small defects or even a single defect will not cause all charge in the gate to be lost. The best known FG technology is NAND FLASH in the form of a USB flash drive, SD memory cards, and solid state drives. NAND flash presented huge advancements over the existing technologies used for portable storage devices (think floppy disks and zip drives) which is why it was such a disruptive technology. When compared to the alternatives, NAND flash has faster erase and write times and a smaller cell area on chip allowing for more densely packed arrays and thus larger data storage per unit area. However, FLASH memories have several inadequacies that would make it a poor candidate for the future desire of a so called universal memory. • Slow erase and write times: NAND FLASH has programming speed on the order of a couple milliseconds per 128KB block which is exceptionally slow when compared to, lets say, SRAM which has programming speeds on the order of nanoseconds. • Low programming endurance: The typical NAND flash can be written/re-written on the order of 106 times which is insufficient for applications such as cache memory and computer main memory which can be written and re-written many times per second
5 and also have fewer writing cycles and smaller storage density than state of the art hard disk drives (HDD’s). Even more drastically, gigabyte class FLASH would have much less endurance and the number of electrons in the gate is smaller. • High voltage requirements: NAND FLASH requires higher voltage than the standard chip supply voltage to erase the cell. To achieve the high voltages it is necessary to provide multiple supply voltages which is typically not necessary, or include charge pump circuits in the chip design which are big and use up valuable real-estate on the silicon.
1.1.2
Ferroelectric Memories
Ferroelectric memories are based on the two stable electronic polarization states of ferroelectric material to store non-volatile data.[19] The ferroelectric memory element closely resembles that of a conventional Metal-Insulator-Metal (MIM) capacitor where the insulator portion that would typically be comprised of some sort of dielectric material which is replaced with a ferroelectric material which is typically configured in a perovskite (ABO3 ) lattice structure. The memory architecture of a Ferroelectric Random Access Memory (FeRAM) is very similar to that of a 2 transistor Dynamic Random Access Memory (DRAM) except that it is truly random access and non-volatile as opposed to modern DRAM chips which are volatile and data is read in bursts. The operating principle of an FeRAM is that the B cation in the ABO3 perovskite structure can occupy two stable positions in the lattice (Fig: 1.1). These lattice configurations are referred to as polarization states, and when the B cation moves up in the lattice it is considered to be in positive polarization or data “1”, alternatively when the B cation moves down in the lattice it is considered negative polarization or data “0”[20]. The polarization states of the Ferroelectric memory can be easily controlled by applying an external field across the storage element. The macroscopic electrical behavior of the ferroelectric memory cell is
6
(a)
(b)
Figure 1.1: Crystal structure unit cell of a cubic perovskite (ABO3 ) Ferroelectric material in (a) positive polarization state or Data “1” (b) negative polarization state or Data “0”.
represented in figure 1.2 as a polarization vs. voltage hysteresis loop. Remnant polarization represents the level of stored charge in the cell when no external bias is present. For all intents and purposes, a cell with a stored confrontational charge in the Pr position would correspond to a logical “1” and similarly, stored charge in the Pr− position would correspond to a logical “0”. Coercive field (VC /thickness) corresponds to the threshold level of field that must be overcome in order for the ferroelectric memory cell to change polarization states. Polarization states are direction dependent and the storing mechanism depends on the B-O dipole configuration and not trapped charge. Thus, in most cases, FeRAMS are destructively read as the opposing polarization is needed to de-polarize (reverse) the dipole configuration. Though the operating principle is the same for cubic perovskite based FeRAM’s such as Pb[ZrTi]O3 , it was not until the discovery of layered perovskites, such as SrBi2 Ta2 O9 (SBT), that significant advancements in ferroelectric memories were made. Ferroelectric memories based on SBT exhibit excellent retention characteristics, low leakage currents, and show nearly fatigue free behavior beyond 1012 cycles [21]. However, Pb[ZrTi]O3 based memories have also
7
Figure 1.2: Typical ferroelectric Polarization vs. voltage hysteresis loop. Pr is remnant polarization and Vc is coercive voltage.
improved due to IrOx electrodes. FeRAM technology has seen a long and fruitful existence with commercial applications in smartcards and electronic metering to name a few. The primary advantage of FeRAM is its low power consumption and stable nonvolatility. However, FeRAM has had significant difficulties breaking into large scale commercialization due to difficult process integration caused by the high temperature requirements of crystallizing the ferroelectric materials. Additionally, FeRAM has not been proven capable of accommodating high density applications in the shrinking CMOS technology nodes.
1.1.3
Resistive Memories
Resistive memories are a class of memory that store a bit based on the resistance state of the storage material. Resistive memories, as I have described them, are a broad classification
8 and therefor contain several emerging memory technologies such as Phase Change Memory (PCM) which undergoes a structural phase change between the amorphous and crystalline phase typically due to Joule heating. Magnetoresistive Random-Access Memories (MRAMs) are devices in which the magnetic state in one of two ferromagnetic plates separated by an insulating material can be switched. In its current embodiment, the spin-torque transfer across the insulating barrier controls the resistance. And, as described before, RRAMs for which the actual switching mechanism is still not well understood, have an immense body of research in industrial laboratories and academia. Many materials have demonstrated resistive switching behavior resulting from electric field including binary transition metal oxides, complex transition metal oxides, such as perovskites, paraelectric and magnetic perovskites, high-k dielectric materials, phase change chalcogenides, and various organic and molecular compounds. The primary appeal of RRAMs is their simplicity, scalability, ultra fast switching times, and ease of integration into current and next generation semiconductor technology scaling nodes. The memory cell can ideally be as simple as an MIM device sandwiched between perpendicular metal lines essentially creating a cross-point array, or in a conventional 1T1R type configuration in which the MIM capacitor structure serves as the storage element and the Metal-Oxide-Semiconductor (MOS) transistor provides isolation from other elements in the memory array as well as taking on a integral roll in the programing of the memory element by limiting the current flow across such element. Thus, resistive memories represent the most promising candidates thus far to fulfill the requirements for a universal memory that would combine the cost benefits of DRAM and the speed of an SRAM with the non-volatility of a FLASH memory.
9
1.2
Scope of Thesis This thesis describes fundamental fabrication and characterization of a novel resistive
random access memory in which the Mott insulator transition common in TMOs is solely the metal/insulator switching mechanism. Though CeRAM falls under the blanket category of resistive RAMs, the underlying physics that control the memory function give CeRAM distinction from other resistive RAM’s, and it is the understanding of these underlying physical mechanisms that have given this research a potential advantage in the pursuit of commercializing this technology. Chapter 2 contains a literature review of current resistive based memory technologies including materials properties and a comprehensive comparison of the device performance metrics which have been reported in the literature as of the date of this work. The conventional filamentary mechanisms believed to be responsible for memory behavior in these materials and devices is also covered in this chapter as well as the challenges already experienced and facing RRAM development. Integration issues related to the materials as well as electrical and reliability issues are all addressed in this section. In chapter 3 a comprehensive review of the physical science necessary to the understanding of CeRAM device performance is presented. Once the background has been established the CeRAM technology can be thoroughly presented in chapters 4 and 5 . Here, the concept behind the CeRAM development program is established. In chapter 4 the fabrication process for proof of concept structures is presented and the characterization and analysis techniques along with a review of compelling results supporting CeRAM are discussed. In chapter 5 the device model of the CeRAM storage cell is summarized, and a review of its capabilities to describe the CeRAM “diode” is included. Finally, in chapter 6, conclusions and recommendations for future work are presented. Appendices A and B show derivations of model equations and MATLAB codes for simulation.
Chapter 2
Review of The Current Status of Resistive Memory Technology
Resistive switching based memories can be can be distinguished by their physical mechanism which drives the resistive switching behavior. Throughout most of the literature, the resistive switching is driven by Thermal, electronic, magnetic, and ionic effects.[22] These switching mechanisms account for the vast majority of memory technologies structured around resistive switching. Phase Change Memories (PCM) undergo a resistive change based on a physical phase change from crystalline to amorphous and vice versa. This is induced by thermally pulsing a phase change material with a resistive heating element. The resistive switching of Conductive Bridge Memories (CBM) is based on ionic migration through a specific medium such as metallic ions migrating through a solid-state electrolyte material to form a conductive bridge through which current can flow easily. Resistive switching mechanisms categorized as magnetic effects are the basis for spin-torque or Spin Transfer Torque (STT) where spin polarized current is used to flip the magnetic polarization of a magnetic material. Though generally outside the scope of this thesis, an excellent primer on STT materials and technologies can be found in Ralph and Stiles [23]. Resistive switching memories based on electronic effects such as those seen in binary metal oxides comprise the largest material set investigated in the literature and this chapter. Resistive random access memory, typically referred to in the literature as RRAM or ReRAM such as those reviewed in these articles[24, 25, 26] as described in chapter 1, fall into the “filamentary memory” paradigm. Thus, in order to become a resistive switch, the material
11 in the MIM sandwich has to be electroformed - that is, a process to create metal rich filaments probably along the grain boundaries. The focus of this chapter is to summarize the latest developments of resistive memory devices based solely in the filament paradigm. We start, however with a broader review of other RRAMs and the materials used to derive them.
2.1
Material Properties and Device Performance Many materials have been considered for use in resistive memories both organic and
inorganic. These materials have shown thermal and ionic resistive switching throughout the literature and typically fall under several categories such as chalcogenides for PCM’s, binary metal oxides, perovskites, solid-state electrolytes, and various organic and molecular systems. Table 2.1 lists a representative sampling of devices and materials from the literature with several of the more meaningful performance metrics. The data highlighted in RED represents the best reported performance as of the time of this literature review.
2.1.1
Chalcogenides
Chalcogenide glasses, such as GeSbTeSe and AgInSbSeTe, have been investigated for use in phase change memories. In these materials, the chalcogenide material can be switched from the crystalline phase to the amorphous phase by heating the chalcogenide with a resistive heater at one electrode. There are several challenges plaguing the commercial integration of PCM’s. First, the large current densities necessary to produce the necessary internal temperature of the storage mechanism for a given technology node exceeds the capabilities of the standard processes. This means that either the active switching region needs to be smaller than the transistor gate length which can potentially be smaller than the typical resolution of the lithography. Second, and most fundamentally to the switching mechanism itself, is the fact that a phase-change, that is essentially thermally induced physical change in the crystalline structure of the switching element, has the potential to cause the resistance of the material to drift over time as defects
12 are created and thus the threshold voltage used to sense the state of the active element must also drift. An excellent review of the status of phase change memory can be found in Wong et al. [27].
2.1.2
Binary Metal Oxides
Binary metal oxides represents the most promising and appropriately the most widely studied group of resistive switching materials.[8, 13, 28, 29, 30, 31, 32] The vast majority of these materials are based on oxides of transition metals due to their ability to undergo Mott metal-insulator and charge transfer transition as a result their incomplete d-shells. The Binary metal oxides are favored in many of these studies because of the advantage of integrating well with current CMOS technology and the fact that scaling properties appear to fall within the range of future CMOS scaling power capabilities. Because of their favor, a vast amount of data has been collected for resistive memories based on Binary metal oxides, and the data is quite promising for different material systems for different reasons. For instance, of the data reported in table 2.1, these materials systems account for the majority of the best reported data in the literature. Most of these materials demonstrate a unipolar or non-polar switching behavior meaning they can be programmed using only positive biases or by using positive and negative biases if the desired architecture should require making them a more versatile choice than some other materials. Much more on the transition mechanism’s of these materials will be covered in subsequent chapters of this thesis.
2.1.3
Perovskites
Perovskite materials, like SrTiO3 (STO), SrZrO3 as well as more complex structures like the colossal magnetoresistive manganites Pr1-x Cax MnO3 (PCMO), La0.7 Sr0.3 MnO3 (LSMO), and cuprate superconductors YBCO, and BSCCO [33], have been observed to exhibit bipolar resistive switching behavior. PCMO films were first reported by researchers at Sharp Laboratories [34] to undergo a resistance change induced by electronic pulse and actually represents
13 the first reported RRAM device, although the phenomenon was observed much earlier than this reporting. These materials have not been a focus of this research for the same reason that ferroelectric memories are not likely candidates for sub-nm technologies because they are more difficult to integrate into existing CMOS processes and dont have the supporting scaling evidence to show they will meet the small size and low power requirements of future CMOS devices.
2.1.4
Solid-State Electrolytes
Materials such as AgGeS and AgGeSe [35] have been studied for Conductive Bridge Random Access Memories (CBRAM) in which the solid electrolyte is sandwiched between an inert cathode and an anion rich anode. For the example of Ag-Ge-Se solid electrolyte, when the stack structure is biased positively the Ag anions from the anode migrate through the electrolyte creating a metallic bridge between the anode and cathode where current can flow more freely. Reversing the bias the anions migrate back into the metal anode and the conductive pathway is broken.
2.1.5
Organic and Molecular Systems
Organic materials have received much attention for their mechanical flexibility, light weight, and low cost properties. These organic RRAMs use a polymer material as the active or switching material sandwiched between two metal electrodes. Recently, it has been shown that extremely low reset currents of ∼ 20nA can be achieved while maintaining excellent data retention using a parylene-C based device[36]. Molecular systems are not necessarily mutually exclusive of other materials systems used for RRAM devices; however, RRAM devices are a specific subset in which storage capacitors are created using some structure containing monolayers of molecular materials as the storage element typically sandwiched between metals and semiconductor grade materials.[37, 38]. These materials, though they could potentially meet all of the scaling requirements of next
14 generation MOS technology, still have a long way to go to prove that they exhibit the necessary robustness to meet the stability, endurance, and performance metrics necessary to be a disruptive force in the memory market.
2.2
Mechanism for Switching The Mechanism responsible for the resistive switching behavior of RRAM devices, though
still largely debated and not fully understood, typically falls under two general classifications: Filamentary conduction and interface type switching. The models used to represent these classifications, however are not as few and contain such concepts as oxidation-reduction reaction [29], random circuit breaker model [51], an electric faucet model [52], thermal dissolution [53], and Mott transitions. The one thing that most of these switching mechanisms seem to have in common is that the change in conductivity is highly localized in so called “filaments” that create conduction paths between the two electrodes and that these filaments are not native to the virgin state of the material but are created during an electroforming step in which a higher power density than is required for switching is applied to the active element. Once the filaments have been created, they can be dislocated from the electrodes and repaired and so on by applying specific biases across the material which is dependent on the materials system. In a bi-polar device, the material is positively biased in order to repair the filament conductors and a negative bias is used to dislocate those filaments. In a unipolar or non-polar system, the switching mechanism is more charge density driven and a higher bias is used to connect the filaments between the electrodes but with the same bias polarity at a lower amplitude the conductive filaments can be broken moving the switching element back in the insulating state. Additionally, with the silver bridge CBRAM we have the ion migration mechanism in which positively charged anions move through an electrolyte to form conductive pathways between the anode and cathode of the active device.
15
Table 2.1: A representative list of material systems used in RRAM devices and their characteristics arranged by year of publication. NS represents values that are “not specified” in the literature Switching Material
BE Material
TE Material
Cell Area (µm2 )
Current
Voltage
Speed
HRS/LRS Ratio
Sr(Zr)TiO3 Ti/Pt
Ti/Pt
0.01
1.4mA
≤ 1 V
1 mS
>2.5
PCMO
Pt
Pt
7854
200µA
≤ 5 V
20 ns
NiO
Noble Metal
Noble Metal
0.2
2mA
10
106
300h @ 150 ◦ C
2004
[8]
NS
2005
[35]
Cux O
Cu
Ti/ TiN
0.03
45µA
10
600
30h @ 90◦ C
2005
[28]
Ti:NiO
Pt
Pt
0.25
100µA
90
100
1000h @ 150 ◦ C
2007
[40]
FeOx
Pt
Pt
.18-18
5mA
10
3x104
1000h @ 85 ◦ C
2007
[13]
NiO
SrRuO3
Pt
90
20mA
5
200
3000s @ 25 ◦ C
2007
[41]
TaOx
Pt
Pt
0.49
170µA
10
109
3000h @ 150 ◦ C
2008
[29]
Ti/ HfOx
TiN
TiN
0.1
25µA
10
106
10h @ 200 ◦ C
2008
[42]
MgO
CoFeB
CoFeB
.1x.2
5mA
10
400
88h @ 85◦ C
2008
[30]
NiO
Pt
Pt
0.49
20µA
1000
100
1000h @ 150 ◦ C
2008
[43]
ZnO
ITO
ITO
196350
20mA
100
100
105 s @ 25 ◦ C
2008
[31]
Ti/ HfOx
TiN
TiN
0.0009
200µA
100
1010
28h @ 150 ◦ C
2009
[44]
MnO2
Pt
Ti
11310
30mA
≤ 1 V
10 ms
>10
105
104 s @ 80◦ C
2009
[45]
ZnO
ITO/ Ag/ITO
ITO
NS
3mA
10
200
104 s @ 85◦ C
2009
[46]
WOx
W
TiN
0.0036
1mA
10
106
2000h @ 150 ◦ C
2010
[32]
ZrOx / HfOx
TiN
Pt
0.0025
50µA
10
106
28h @ 125 ◦ C
2010
[47]
N:AlOx
Al
Al
1
50nA
100
105
28h @ 125 ◦ C
2011
[48]
TaOx / Ta2 O5
Pt
Pt
9000
30µA
100
1012
3h @ 200◦ C
2011
[49]
Hf/ HfOx
TiN
TiN
0.0001
50µA
10
5x107
30h @ 250 ◦ C
2011
[50]
>1000
Endurance
3.2x1010
16
2.3
Challenges of RRAM Development There are several challenges in the development of RRAM devices that need to be over-
come in order for the main market drivers to put these materials into production. I would say first and foremost that cell performance metrics need to significantly exceed those of current high density flash memory technologies. It is known and accepted that flash memories will fail to perform as technology nodes scale, but right now they are a safe technology. But, going deeper than the competitiveness of the technology, there are materials and reliability concerns that need to be addressed before the technology can really take off.
2.3.1
Materials Issues of Resistive Memories
One of the first and most fundamental concerns with any new technology development is the compatibility of the process materials necessary for that new development with materials used in any underlying manufacturing process that would be needed to realize the new technology. For RRAM development to be realized, any material used in the storage element must be compatible with materials and processes of current and next generation semiconductor fabrication technology. The development of resistive memories, especially in the academic world, has examined a large range of materials as was evidenced in table 2.1, some of which can be risky when introduced in a semiconductor fabrication facility. An example of these materials can be seen in in the color coded periodic table of elements Figure 2.1, the elements highlighted in green in particular are materials that have been studied for resistive memory development but are not widely present if at all in current CMOS processes. Only those resistive memory elements comprised of materials highlighted in magenta present the simplest integration with CMOS because they are already compatible with most fab processes. In order to utilize many of these materials they would need to be strictly isolated from front end of line processes (e.g. Au,Pt,Cu) because of their known detrimental effects to CMOS flows, while with others, their potential effects are simply too unknown to risk contamination of process flows used in other
17 established product lines. There are also some back end of line (post CMOS) contamination concerns due to the fact that in many fabrication facilities there is processing equipment that is not strictly limited to front end of line such as lithography steppers and certain etchers. Any resistive memory that would be added integrated into an existing technology flow should be consisting of those materials which are not foreign to the fabrication facility.
2.3.2
Reliability Issues
The primary failure mechanism for RRAM devices, including CeRAM devices, which are the focus of this thesis, is that during write/re-write cycling the memory cell becomes irreversibly stuck in the LRS. However, as it will be described later, whilst this failure mechanism is certainly defect driven in CeRAMs, doping control can be used to optimize the device. In the case of filamentary RRAMs, doping control of the conductive filaments is unfortunately not a viable solution. Scalability is also a critical factor when considering a device for future technology where memory cells must be able to reliably switch at nanometer device dimensions in order to meet with the form factor requirements of future technologies. Scalability becomes an issue with RRAM devices partially due to the mechanism which is attributed to the switching behavior of the bulk of the devices presented in the literature. If the switching mechanism is considered to be a random matrix of conductive filaments, which is largely agreed upon, the performance of these resistive switching structures will very likely be quite different when the entire device geometry shrinks down to a size smaller than that of a single conductive filament. Since it has been shown that the maximum on state current of RRAM devices which occurs at the onset of a RESET is dependent on the compliance current, i.e. the current allowed to flow through the active region during a SET, and not the device dimensions themselves. There is some concern that at a certain point in the dimensional scaling process the currents will cease to decrease with area and create current requirements higher than the technology will allow. Additionally, it is possible with this mechanism for the dimensions of the active cell to simply
1 IA 1
18 VIIIA
1.0079
2
H
1
Periodic Table of Chemical Elements 2 IIA
Hydrogen 3
4.0025
He
6.941
4
13 IIIA
9.0122
5
10.811
14 IVA 6
12.011
15 VA 7
14.007
16 VIA 8
15.999
17 VIIA 9
18.998
Helium 10
20.180
Li
Be
B
C
N
O
F
Ne
Lithium
Beryllium
Boron
Carbon
Nitrogen
Oxygen
Flourine
Neon
2
11
22.990
12
24.305
Na
Mg
Sodium
Magnesium
3
19
39.098
20
40.078
13
3 IIIA 21
44.956
4 IVB 22
47.867
5 VB 23
50.942
6 VIB 24
51.996
7 VIIB 25
54.938
8 VIIIB 26
55.845
9 VIIIB 27
58.933
10 VIIIB 28
58.693
11 IB 29
63.546
12 IIB 30
65.39
26.982
14
28.086
15
30.974
16
32.065
17
35.453
18
39.948
Al
Si
P
S
Cl
Ar
Aluminium
Silicon
Phosphorus
Sulphur
Chlorine
Argon
31
69.723
32
72.64
33
74.922
34
78.96
35
79.904
36
83.8
K
Ca
Sc
Ti
V
Cr
Mn
Fe
Co
Ni
Cu
Zn
Ga
Ge
As
Se
Br
Kr
Potassium
Calcium
Scandium
Titanium
Vanadium
Chromium
Manganese
Iron
Cobalt
Nickel
Copper
Zinc
Gallium
Germanium
Arsenic
Selenium
Bromine
Krypton
4
37
85.468
38
87.62
39
88.906
40
91.224
41
92.906
Rb
Sr
Y
Zr
Nb
Rubidium
Strontium
Yttrium
Zirconium
Niobium
5
55
132.91
56
137.33
57-71
72
178.49
73
180.95
42
95.94
43
96
44
101.07
45
102.91
46
106.42
47
107.87
Mo
Tc
Ru
Rh
Pd
Ag
Molybdenum
Technetium
Ruthenium
Rhodium
Palladium
Silver
74
183.84
75
186.21
76
190.23
77
192.22
78
195.08
79
196.97
48
112.41
Iodine
Xenon
Hg
Caesium
Barium
Lanthanide
Halfnium
Tantalum
Tungsten
Rhenium
Osmium
Iridium
Platinum
Gold
Mercury
Fr
Ra
Ac-Lr
Francium
Radium
Actinide
7
Rutherfordium
57
138.91
Dubnium
58
140.12
266
107
Seaborgium
59
140.91
264
108
Bohrium
60
144.24
277
Hassium
61
145
109
268
Meitnerium
62
150.36
110
281
Darmstadtium
63
151.96
111
280
Roentgenium
64
157.25
112
81
204.38
82
207.2
Tl
285
Ununbium
65
131.29
Tellurium
Au
106
54
Antimony
Pt
262
126.9
Tin
Ir
105
53
Indium
200.59
Os
261
127.6
Cadmium 80
Re
104
52
Xe
W
89-103
121.76
I
Ta
226
51
Te
Hf
88
118.71
Sb
La-Lu
223
50
Sn
Ba
87
114.82
In
Cs
6
49
Cd
158.93
Thallium 113
284
Ununtrium
66
83
208.98
Pb
162.50
Lead 114
209
164.93
115
288
Ununpentium
68
85
210
Po
Bismuth 289
Ununquadium
67
84
Bi
167.26
Polonium 116
293
Ununhexium
69
86
222
At
168.93
Rn
Astatine 117
292
Ununseptium
70
173.04
Radon 118
294
Ununoctium
71
174.97
La
Ce
Pr
Nd
Pm
Sm
Eu
Gd
Tb
Dy
Ho
Er
Tm
Yb
Lu
Lanthanum
Cerium
Praseodymium
Neodymium
Promethium
Samarium
Europium
Gadolinium
Terbium
Dysprosium
Holmium
Erbium
Thulium
Ytterbium
Lutetium
Materials reported in RRAM literature RRAM Materials in current fab processes Z
mass
89
227
90
232.04
91
231.04
92
238.03
Symbol
Ac
Th
Pa
U
Name
Actinium
Thorium
Protactinium
Uranium
93
237
Neptunium
94
244
Plutonium
95
243
Americium
96
247
Curium
97
247
Berkelium
98
251
Californium
99
252
Einsteinium
100
257
Fermium
101
258
Mendelevium
102
259
Nobelium
103
262
Lawrencium
Figure 2.1: Table with highlighted materials used for RRAM devices in the literature 18
19 be smaller than would be necessary for a filament to form and the memory action of those devices would no longer exist. Fortunately for CeRAM devices, though the RESET current does scale with compliance, we have been able to demonstrate that the processing techniques used for precisely controlling the material properties allow for the scaling of off state diode current which drives the compliance requirements thereby allowing us to tune the compliance requirements as a function of area. More on this later. Electroforming requirements of the filament driven devices will also create issues due to the high voltage and current requirements in the initial conditioning phase of the memory element. Essentially what is happening here is that in order to create conductive filaments in the material capable of being switched between the resistive and conductive states, a larger voltage must first be applied to the anode (top electrode) of the device causing many conductive filaments (often agreed upon to be oxygen vacancies in the grain boundaries of the semiamorphous material) to be created at the cathode (bottom electrode) eventually building a complete path all the way to the top electrode. Once the filaments have been created the switching mechanism is concentrated near the anode where the filament density is the smallest, and the filaments can be destroyer by thermal breakdown in the case of unipolar switching and potentially thermally assisted electron migration in bipolar switching devices.
Chapter 3
Electronic Phase Transitions in Correlated Systems
The goal of this chapter is to provide the necessary background information to build an understanding of the underlying mechanisms of metal-insulator transitions (MITs). As it is well known (Imada et al. [54]) electron density variations are responsible for the MIT and its reversal. It is central to the CeRAM storage cell that electron tunneling and electron-hole recombination induce these density variations and are responsible for the switching between metal and insulator behavior observed in CeRAMs. It is thus implicit in the basic physics of Mott-like MITs, that the Wigner-Seitz density parameter, Rs and the ensuing electron screening length are first order parameters in controlling the electron-electron interaction. Starting with a review of Hubbard-Mott theory, this chapter covers the physics of the infinitely narrow Hubbard Hamiltonian and it’s application to quantum transport in CeRAMs.
3.1
Non-Interacting Electrons Let us consider a simple system in which the Schr¨odinger equation represents the transfer
function. The most general form of the transfer function takes the form: ˆ = i~ ∂Ψ HΨ ∂t
(3.1)
ˆ is a Hamiltonian operator which represents the total where Ψ is the wave function and H energy of the system for a given wave function. For a single particle non-interacting system
21 the Schr¨odinger equation becomes: −
∂Ψ∗ ~2 d 2 Ψ + V (x)Ψ = EΨ = i~ . 2m dx2 ∂t
(3.2)
Multiplying both sides by the complex conjugate of the wave function yields d2 Ψ ∗ Ψ + Ψ∗ V (x)Ψ = EΨ∗ Ψ. dx2
(3.3)
By combining 3.2 and 3.3 the single particle current in an open boundary (device) is given by
∇·J =−
∂ρ . ∂t
(3.4)
To illustrate the non-interactive electron current we start with a fundimental continuity equation dJ ∂ρ =− dx ∂t
(3.5)
ρ = Ψ∗ Ψ
(3.6)
where,
and re-write Schr¨odinger’s equations as ~2 d 2 ρ ∂ρ + Ψ∗ V (x)Ψ = i~ 2 2m dx ∂t ∂ρ ~2 d 2 ρ + ΨV (x)Ψ∗ = i~ − 2m dx2 ∂t
−
(3.7a) (3.7b)
combining these two equations together yields 2 d Ψ ∂ρ 2 2 + (Ψ∗ V (x)Ψ − ΨV ∗ (x)Ψ∗ ) = 2i~ . dx ∂t
(3.8)
2 ∂ρ d2 ∗ ∗ d Ψ Ψ − Ψ 2 Ψ + V (x) (Ψ∗ Ψ − ΨΨ∗ ) = 2i~ 2 dx dx ∂t
(3.9)
~2 − 2m If V (x) = V ∗ (x) then ~2 − 2m
and since we know that Ψ∗ Ψ = ΨΨ∗ ~ − i4m
2 d2 ∗ ∂ρ ∗ d Ψ − Ψ 2Ψ = Ψ 2 dx dx ∂t
(3.10)
22 which can be re-written as: ~ − i4m
d dΨ∗ d dΨ Ψ −Ψ dx dx dx dx ∗
=
∂ρ ∂t
(3.11)
giving the equation for current by using the continuity equation from before as: J =−
~ (Ψ∗ ∇Ψ − Ψ∇Ψ∗ ) . i4m
(3.12)
At the mesoscopic scale, where the device dimensions (thickness) are of the order of the electron coherent wave length, single particle currents can be generalized in a many body problem fermion field. As this will be the key to show the MIT in current-voltage characteristics, the concept of a single non-interactive particle is readily seen in equation 3.12. For the Many Body description, fermion field operators are necessary and they immediately need second quantization. this is briefly described below starting with,
Ψ(x) = Ψ∗ (x) =
X
X
Ψ∗ Ψ =
ci φi (x) c†i φ∗i (x)
X
c†i ci
where ci and c†i are the annihilation and creation operators and φi (x), φ∗i (x) are the fermion field operators. As will be shown later, the current in mesoscopic devices is derived from: i~q
i h ˆ ∂N ˆ, H = N ∂t
(3.13)
where ˆ = N
X
c†k ck
(3.14)
k
which is the two particle operator and nk = band dispersion (E(k)).
c†k ck
is the electron density in the k-th state of the
23 As described above, the density parameter Rs , indicates how the density of free or nearly free electrons screen the ion and core electrons. It is well known (Kittel [55]) that the volume per free electron is 4 1 π(Rs aB )3 = 3 n
(3.15)
and that R = Rs ab which is nearly the lattice spacing, describes a metal like material (Rs = 1), which Mott used to describe the insulator to metal transition to be ∼ aB n1/3 = 0.26. c
(3.16)
Thus, at the critical electron concentration (nc ) a Mott insulator (or charge transfer Mott insulator) behaves like a metal with Rs as large as 6. An insulator is achieved when Rs is large enough to completely eliminate wave function overlap. A more sophisticated understanding of the Mott transitions is given below.
3.2
Mott Insulators and the Mott Transition The Mott transition, or even more fundamentally, Mott insulators are materials that, by
traditional band theory, should behave like metals but are instead insulators. This breakdown in band theory is due to the the fact that traditionally it is assumed that electrons do not interact with one another, i.e. that electrons and are essentially independent particles floating in an infinite and static potential. In the student Solid State Physics texts, such view of electrons has a long history. First, the very successful Drude model based on kinetic theory of gasses (Classical electron gas). Later, Sommerfeld introduced the quantum expansion of the drude model to include the wave properties of electrons. And finally, using Bloch electrons, Wilson developed band theory. By 1937, De Boer and Verwey [56] pointed out that NiO did not follow band theory because theoretically it should be a metal, and yet behaved as an insulator. Sir Nevile Mott, circa 1957 explained this anomaly as caused by a “disproportionation” reaction (d8 + d8 → d7 + d9 ) which yielded a coulomb repulsion in the 3d8 shell of NiO. By 1963, Hubbard and others explained
24 this now called “Mott transition” from first principles. In 1977 Mott and Hubbard received the Nobel Prize for their work.
3.3
The Hubbard Model The Hubbard model is based on the well known tight binding approximation as its
starting point. The general form of the Hamiltonian is of the form H = H0 + V
(3.17)
where V is the potential energy of the system and the tight binding Hamiltonian H0 in second quantization is, H0 = −t
X
c†i,σ cj,σ
(3.18)
hi,ji,σ
where t is the hopping integral representing the energy for electrons to hop from one atom to the next and c†i,σ cj,σ is the creation and annihilation operators representing the number of particles occupying each state. Hubbard considered the intrasite potential and the electron localization via a repulsive Coulombic force. Thus, Hubbard introduced the on-site repulsion term U which is a result of coulomb interaction between electrons on the same atomic orbital and is sometimes simply referred to as the Hubbard-U . Now 3.17 representing the total energy of the system with the kinetic Hamiltonian H0 and the local intrasite potential energy now becomes. H = −t
X
c†i,σ cj,σ
+U
hi,ji,σ
N X
ni↑ ni↓
(3.19)
i=1
where U = I − E.
(3.20)
I is the energy required to remove an electron from the lattice, and E represents the energy gained when free electrons are added to the lattice. For Ni I = E3d8 →3d7
(3.21)
E = E3d8 →3d9 .
(3.22)
25 If we consider transition metal oxide systems, and more specifically 3d transition metals such as in the NiO compound investigated here where the conduction mechanism is the disproportionation reaction dn + dn → dn+1 + dn−1
(3.23)
we can re-write equation 3.20 in the form U = E(dn+1 ) + E(dn−1 ) − 2E(dn ).
(3.24)
There is now some competition between the hopping integral t and the on-site coulomb repulsion U which is able to explain metal-insulator transitions in strongly correlated materials. The average value of coulomb potential between electrons in two different locations is V (i, j; k, l) = ij
and the Hubbard U is then
e2 kl 4πE0 |r1 − r2 |
2 e ii = V (ii, ii). U = ii 4πE0 r
(3.25)
(3.26)
Figure 3.1 shows the local crystal field configuration of NiO. It can be readily seen that the crystal field (made of local oxygen and nickel electric fields), splits the gas phase degenerate nickel orbitals into two degenerate sets of levels. The 2p oxygen orbitals interact with the upper Hubbard band to create the interaction between electrons that become the reason for the disproportionation and subsequently metal/insulator transition. According to Hund’s rule one would expect that each of the 5 sub-bands in the 3d shell would contain a single electron before any of them would be occupied by a second. If this were the case, the last two sub-bands would contain 1 electron each in the 3d7 and 3d9 positions meaning the Fermi level in the ground state would be located at the last filled, or lowest energy sub-band having room for an electron to doubly occupy that level and thus conduction occurs. However, since NiO does not adhere to non-interacting band theory for which Hund’s rule describes the band filling, this is not the case. As shown in 3.1, for the ground state
26
Hubbard subbands
dx 2-y 2, dz 2
Ni 3d
eg 6 Dq Ligand Field Splitting -4 Dq
dxy, dyz, dzx
t2g
Figure 3.1: band diagram for NiO. Reprinted with permission from Xue et al. [18]. Copyright 2011, AIP Publishing LLC
of a 3d transition metal, the 3dn state which should be empty contains an electron leaving the sub-band containing the 3dn+1 and 3dn+2 positions empty. This non-typical band filling creates an on-site coulomb repulsion causing these sub-bands to split into an empty upper Hubbard sub-band (UHB) [3dn+1 and 3dn+2 ] and a doubly occupied lower Hubbard sub-band (LHB) [3dn−1 and 3dn ]. The double occupancy at the 3dn level creates the repulsion that is responsible for the gap U . More on this mechanism will be discussed later. Nickel oxide however is in actuality a charge transfer type Mott insulator which is shown in figure 3.3b as opposed to the Mott-Hubbard model described in figures 3.2 and 3.3a. Though these two transition types are fundamentally different in the band representation, the transfer mechanism is largely the same and the Mott transition type mechanism satisfies both conditions. In the Mott-Hubbard type insulator, the metal to insulator transition occurs as a result of an electron being transferred from the lower Hubbard band 3dn to the upper Hubbard band
E
27
E
UHB EF
EF
LHB
Nickel 3d t2g
Nickel 3d t2g
Oxygen 2p band
Oxygen 2p band DOS(E)
(a) Insulating state
DOS(E) (b) Conducting state
Figure 3.2: Mott-Hubbard metal-insulator transition. (a) Normal band splitting into Full LHB and empty UHB representing a non conducting insulator. (b) Dotted line represents continuous band created when some electron states are excited into the UHB resulting in metallic conductive behavior.
3dn+1 overcoming the charge gap U created by the strong coulomb repulsion between intra-site electrons. Similarly, for the charge transfer Mott insulator, the lowest filled energy level is from the Oxygen 2p band instead of the transition metal 3d band and the charge transfer gap ∆ is between 3dn ↔ 3dn+1 L where L represents a hole in the oxygen valence band.[57] For charge transfer insulators, the transition is a result of an electron being transferred from the Oxygen 2p into the upper Hubbard band thus overcoming the charge gap (∆). Because the two MIT mechanisms are functionally the same, that is, the central point is the electron-electron interaction energy (U ), the Mott-Hubbard type is primarily used in this thesis. Linking of the discussion
28
E
E
UHB
UHB
EF
EF
LHB
Nickel 3d t2g Oxygen 2p band
Oxygen 2p band DOS(E) (a) Mott-Hubbard MIT
DOS(E) (b) Charge Transfer MIT
Figure 3.3: Two band representations of the insulating state of NiO representing the ground state of the metal insulator transition for (a)Mott-Hubbard metal insulator transition and (b) Charge transfer metal insulator transition are are shown.
pertaining to the density parameters, it should be pointed out that for H = KE + P E, Rs ∝
PE 1 ∝ KE n
(3.27)
thus, as the density varies, the MIT/IMT switching occurs.
3.4
Green’s Functions The purpose of using Green’s functions is that it provides a means for determining
the expectation values of correlated functions such as those we are presented with in our device problem. Much of this section follows the work of Nolting and Brewer [58] though not necessarily in the order in which it was presented. Let us begin this section by re-writing the
29 Many Body form of Schr¨odinger’s equation (3.1) using the Hubbard Hamiltonian from the previous section and Green’s functions.
∂ i~ − Hs G± (t) = 1δ(t) ∂t
(3.28)
where G+ and G− are the advanced and retarded Green’s functions respectively. G+ (E) =
1 E + iE − Hs
(3.29)
G− (E) =
1 E − iE − Hs
(3.30)
and, G± (E) =
[G± 0 (E)]
1 1 = E ± iE − H0 − Σ ± (E) − 1 − Σ ± (E)
(3.31)
where G0 =
1 1 or G0 = E − E(k) E − (E(k) − µ)
and Σ is the electron-electron interaction self-energy. Thus, the Green’s function for the “quasiparticle” (electrons plus interaction) is given by, G = G0 + GΣG0
(3.32)
Σασ ∼ = eV (ii, ii) ∼ eU
(3.33)
Σ = U hn−σ i f (U ).
(3.34)
E + µ − T0 E + µ = U (1 − hn−σ i) − T0
(3.35)
and the interaction term Σ is:
or as it will be later seen
Here, f (U ) =
and hn−σ i is the occupation number and is either “0” or “1” depending on if there is a second electron occupying the site or not; −σ means that the second electron obeys Pauli
30 principle - flipped spin. Multiplying through we get the self-energy in terms of the Green’s function as: −1 Σ = G−1 0 −G .
(3.36)
(1) DOS for Non-Interacting electrons Now lets introduce the Density of States (DOS) function for non-interacting fermions. The generalized density of states is given by: ρ0 (E) =
1 X δ(E − E(k)). N
(3.37)
k
If we consider only a single particle, the DOS would be ρ′0 (E) = δ(E − E(k)) where k is a fixed single state in the band diagram. Since we are in fact dealing with more than one state in the band and we assume the lattice potential is negligible, the energy dispersion is given as usual for a Bloch electron, E(k) =
~2 k 2 . 2m
(3.38)
From this, (see Appendix B) we can start with 3.37 and arrive at the well known derivation of DOS as, ρ0 (E) =
V 4π 2 N
2m ~2
3/2
√
E, E ≥ 0
(3.39)
where the work function µ = 0. (2) DOS for interacting (Correlated) electrons Starting with: HGαkσ = 1 (or δ(E))
(3.40)
such that the interactive Hamiltonian is given by, H = E − (H0 − µ + Σασ (k, E)) where
(3.41)
31 H0 =energy of a Free electron µ =chemical potential Σασ (k, E) =Interaction term= self-energy of the interaction
By using Dyson’s equation below, the Green’s function can be approximated. 1 (0) (0) Gkσ (E) = Gkσ (E) + Gkσ (E)Σσ (k, E)Gkσ (E) ~
(3.42)
We can find “G” including the interaction and model the material via the first order impact of the self-energy and not all higher order Green’s functions. This is important because we can use G in the density of states equation to find the DOS with electron-electron interaction, thus, with G from the Hubbard Hamiltonian for interacting narrow bands, −1 Im(G) π
ρσ =
(3.43)
and the density of states containing the electron-electron interaction is ρσ =
1 X δ[E − E(k) − Rσ (E − µ)] N
(3.44)
k
where the DOS without interactions is ρ0 =
−1 Im(G0 ) π
(3.45)
or ρ0 =
1 X δ(E − E(k)). N
(3.46)
k
So, if we compare the DOS equation for interacting quasi-particles with the standard Bloch density of states we see that: ρσ = ρ0 [E − Σσ (E − µ)].
(3.47)
This means that if Σ ∼ = U we have an insulator. As the = 0, we have a metal and for Σ ∼ DOS inters the conductivity and often “susceptibility”, the MIT/IMT can be seen as a transformation of the density of states as the function Σ is switched on and off.
32 (3) The Mott transition and the Density of States The general form of the self energy is given by: Σ = Rσ (k, E) + iIσ (k, E)
(3.48)
with the imaginary part Iσ set to zero, as commonly done for Mott insulators in which,
Σ(r, E) = Σ(E), i.e. Σ(k, E) = Σ(E).
(3.49)
This allows us to write the DOS equation in terms of only the real part of the self energy as(Dobrosavljevic et al. [59]): ρσ = ρ0 [E − Rσ (E − µ)]
(3.50)
where Rσ (Σ − µ) is the phase transition self-energy. In the next chapter, we will show that the essential characteristics of the CeRAM storage device, is such that a transition metal oxide (TMO) or perovskite, properly doped to reduce oxygen vacancies, takes advantage of the MIT/IMT via the free electron density parameter. Thus, in the “Set” mode, in which the MIM structure reaches a critical tunneling and thermionic current level, the injected electrons increase the electron concentration to the 1/3
level of the Mott criterion for IMT (i.e. aB nc
= 0.26). When this electron concentration
is annihilated by hole injection at the “Reset” voltage, the interaction U , switches on by the double occupancy on the 3d9,10 orbital. Thus the two memory states are accomplished.
Chapter 4
Transport in Nanoscale Oxide Devices
4.1
The MIM Diode A quantum mechanical representation of the MIM diode is the foundation for the model-
ing of the I-V characteristics of CeRAM devices. In this section I will describe the generalized model used for representing the barrier potentials in an MIM diode, as well as the generalized current equation used by Simmons [60] to show tunneling current through the barrier.
4.1.1
Potential energy and Image force
Let us first start with the simplest model for a rectangular potential barrier in two similar metal electrodes separated by an insulating film. The intrinsic electric field of this system is represented by Fi =
(Φ2 − Φ1 ) es
(4.1)
where Φ1 and Φ2 are the metal work functions of the electrodes, and s is the insulating film thickness. The barrier height of the metal insulator interfaces ϕi m is related to the metal work function Φm and the electron affinity of the insulator χi by ϕim = Φm − χi
(4.2)
and are related to one another as ϕ2 = ϕ1 + eFi s = ϕ1 − ∆Φ
(4.3)
34 where ∆Φ = Φ2 − Φ1 . It is fairly straight forward to represent the potential barrier height through the material as ϕ(x) = ϕ1 +
x∆Φ s
(4.4)
where x is the position in the insulating region between electrodes. When a bias is applied to one electrode and the film is no longer at the ground state, 4.4 can be re-written as: ϕ(x) = ϕ1 +
x(∆Φ − eV ) . s
(4.5)
The abrupt barrier edges represented by the rectangular model is in fact not a realistic representation of real interfaces which are much smoother due to an image force between the metal and the insulator. This image potential is found as [61]: ( ) ∞ X e2 1 ns 1 Vi = + − 8πKǫ0 2x (ns)2 − x2 ns
(4.6)
n=1
which is quite bulky and difficult to work with. Thankfully, the image potential can be accurately approximated as [60, 61]: Vi =
−2.88s eV Kx(s − x)
(4.7)
so the total potential energy in the insulator is now represented as: ϕtot (x) = ϕ(x) + Vi or more explicitly ϕtot (x) = ϕ1 +
x(∆Φ − eV ) −2.88s + eV. s Kx(s − x)
(4.8)
Figure 4.1 shows a rectangular potential barrier for an MIM diode with similar electrodes. As you can see, the image potential has a negative influence on the total potential of the barrier, lowering the total maximum of the potential barrier, and smoothing out the abrupt nature of the barrier edges. The total potential barrier equation 4.8 for a 1 V forward bias with ϕ1 = ϕ2 = 1eV , K = 1, T = 300K is simulated in MATLAB and can be compared to the rectangular potential barrier in figure 4.1 for different barrier thicknesses.
35 2
2 ϕ ϕim ϕtot
1
1
0
0
Potential (eV)
Potential (eV)
ϕ ϕim ϕtot
−1
−2
−1
−2
−3
−3
−4
−4
−5 −2
0
2
4
6
8
10
12
−5 −10
0
10
20
30
40
50
60
70
80
90
100
x (nm)
x (nm)
(b) total potential 90 nm barrier
(a) total potential 10 nm barrier
Figure 4.1: Image potential effect of total potential barrier given a rectangular potential barrier at 1 V forward bias for a symmetric MIM diode with (a) 10nm and (b)90nm barrier thickness. ϕ1 = ϕ2 = 1eV , K = 1, T = 300K. (Note: See Appendix A listing A.1 for MATLAB code.)
4.1.2
MIM current equations
The equation representing current flow between two similar electrodes can be found as [61]: ′
Jth = Ath T 2 e−ϕ /kT (1 − e−eV /kT ),
(4.9)
where Ath =
2 4πmekB , h3
(4.10)
and ϕ′ is the maximum barrier height. This equation represents the current due to thermionic emission and is limited by thermal effects. The generalized equation for tunneling current as presented by Simmons [60] is: n o Jtun = J0 ϕ¯ exp(−Atun ϕ¯1/2 ) − (ϕ¯ + eV ) exp(−Atun (ϕ¯ + eV )1/2 )
(4.11)
where J0 =
e , 2πh(β∆s)2
(4.12)
36 and the Atun factor is Atun
√ 4πβ∆s 2m = . h
(4.13)
The mean barrier height ϕ¯ is 1 ϕ¯ = ∆s
Z
s2
ϕ(x)dx,
(4.14)
s1
where s1 and s2 are the point where the potential barrier, including image charge, intersect the Fermi level and the tunneling distance ∆s = s2 − s1 . The correction factor β is 1 β =1− 2 8ϕ¯ ∆s
Z
s2 s1
(ϕ(x) − ϕ) ¯ 2 dx ≈ 1.
(4.15)
Figure 4.2a shows the thermionic and tunneling current densities for a MIM diode with an average barrier height of 1eV versus applied bias. For low bias, thermal emission dominates the current density through the barrier. As the applied bias increases to eVapplied ≈ ϕ, ¯ the tunneling current increases rapidly and begins to dominate. Figure 4.2b shows how both thermal and tunneling dominated currents contribute to the total current versus applied bias characteristic. 5
5
10
10
4
10
0
10
3
10 −5
10
2
10 −10
1
10 Jtotal (A/cm2)
−15
10
J
thermal
2
(A/cm )
10
0
10
−1
10
−20
10
−2
10 −25
10
−3
10 −30
10
J J −35
10
0
0.2
0.4
0.6 Applied Bias (V)
0.8
1
−4
10
thermal tunnel
−5
1.2
(a) Thermionic emission and tunneling current density
10
0
0.2
0.4
0.6 Applied Bias (V)
0.8
1
1.2
(b) Total current density
Figure 4.2: Thermionic emission, tunneling current, and total current density vs. applied bias for a symmetric MIM diode with ϕ¯ = 1 eV, s = 90 nm, and T = 300 K. (Note: See Appendix A listing A.2 for MATLAB code.)
37 For much of our purposes, in the regions of operation that are valid for CeRAM devices, the tunneling current equation 4.11 can be simplified to: (See Appendix B.1 for derivation) Jtun = −J0
4.2
eV exp A(eV /2)1/2 . 2
(4.16)
Transport During the Phase Transition Although the MIM structure is basic device architecture, Simmons model shows only an
independent electron approximation based on the semi-classical WKB approximation. From this alone, it is not possible to show the MIT/IMT transitions from such a model. However, Simmons model does show the electron density for free carriers that screen the ion cores and form the IMT. The system that best describes the devices in question, for the phase transition, is graphically represented in figure 4.3. For this system we have a finitely restricted nanojunction sandwiched between two ideal electrodes, or Leads, which are connected to two infinite potential reservoirs. The flow of electrons through the system is represented as a function of electrons moving into the junction from the left minus a function of electrons moving into the junction from the right. These equations are shown as follows: fL (E) =
1 , exp[(E − µL )/kB )] + 1
(4.17)
fR (E) =
1 . exp[(E − µR )/kB )] + 1
(4.18)
and
The total current of the system is the sum of all currents, and is thus the integral of the energy distribution, shown in 4.3, multiplied by the density of states which is best represented with the advanced and retarded greens functions: ie I = 2 2~
Z
dE Tr [ΓL (E) − ΓR (E)]G< (E) 2π
+ [fL (E)ΓL (E) − fR (E)ΓR (E)][G+ (E) − G− (E)] .
(4.19)
38
Figure 4.3: Schematic of the system described within the Landauer approach. The nanojunction is sandwiched between two ideal (scattering-free) leads. Particles are injected at the infinite far left and infinite far right with two different local equilibrium distributions. The infinite far regions may be conceptually thought of as two “reservoirs”, even though these do not interact dynamically with the system. The (macroscopic-averaged) local electrochemical c potential µ(x) varies along the whole structure. 2008 Massimiliano Di Ventra. Reprinted with the permission of Cambridge University Press.[62]
The total density of states can be reduced to a function A(E) which leads to: 2e I= ~
Z
dE[fL (E) − fR (E)]Tr{
ΓL (E)ΓR (E) A(E)} ΓL (E) + ΓR (E)
(4.20)
where, 2πA(E) = −2G+ (E)Im{Σ+ (E)}G+ (E).
(4.21)
By introducing the transmission coefficient, TLR (E) = −2Tr{ΓLR (E)G+ (E)Im{Σ+ (E)}G− (E)}
(4.22)
the total current of the system now becomes: e I= π~
Z
dE[fL (E) − fR (E)]TLR (E).
(4.23)
39 Converting to real current density will be more useful in the implementation of the transmission current into the CeRAM model, 2q J= h
Z
Γ0 (fL (E) − fR (E − eV ))ρσ dE.
(4.24)
It is here that it can be shown that the interaction, i.e. Σ ≈ φU , enters the current via ρσ , the DOS with interaction. An energy gap develops when ρσ 6= ρ0 . Simmons model is a specific situation when tunneling (and thermionic) current depends only on ρ0 . which can be simplified to:(See Appendix B.2 for derivation) Jφ =
X k
J0 eβ(E−E(kF ) 1 − eqV /kT .
(4.25)
If we are only concerned with the current at the Fermi level which is centered in the U gap, then E = E(kF ) and we can express this equation as Jφ (fermi) = J0 eqV /kT − 1 .
(4.26)
Notice the change in sign here which is due to the fact that we are interested in modeling electric current as opposed to electron flow which is opposite. The I-V characteristics of 4.26 are shown in figure 4.4 at room temperature. The reason this plot is represented as current vs. voltage instead of current density is because J0 , which would be dependent on device area, was chosen arbitrarily to be 1 × 10−12 and is within range of the baseline current of an average CeRAM device on the order of 10’s of micrometers. As shown in figures 4.4 (without thermionic current) and 4.5 (with thermionic current), the “set” current is nearly ballistic as Rs → 1 due to the electron interaction and the models exhibit the same result, i.e. JM IM (V = Vset ) ∼ = Jφ (V = Vset ). This will be used in the next chapter to show the CeRAM storage cell. In the insulating side of the Phase current equation, there is an experimentally derived J0 which is simply the extrapolated 0-bias current of the device. By adjusting this J0 value value in range with the thermionic emission current we are able to see the total effect of the current mechanisms for the phase transition plus thermal and tunneling effects.
40 −3
5
x 10
Idiode Compliance 4
Current (A)
3
2
1
0
−1 −2
−1.5
−1
−0.5
0 Applied Bias (V)
0.5
1
1.5
2
Figure 4.4: Diode current vs. applied bias for a symmetric diode with charge near the Fermi level.(Note: See Appendix A listing A.3 for MATLAB code.)
5
5
10
10
4
10 0
10
3
10
2
10
−5
10
1
10
0
−10
10
10
−1
10
J
−2
Jtotal (A/cm2)
thermal
(A/cm2)
−15
10
−20
10
−25
10
10
−3
10
−4
10
−5
10
−6
10 −30
−7
10
10
−8
10 −35
10
−9
10 J
−40
10
Jtunnel Jdiode
−45
10
thermal
0
0.2
0.4
0.6
0.8 1 Applied Bias (V)
1.2
1.4
1.6
(a) Diode, Thermionic, and tunneling current density
−10
10
−11
10
−12
10
0
0.2
0.4
0.6
0.8 1 Applied Bias (V)
1.2
1.4
1.6
(b) Total current density
Figure 4.5: Thermionic emission, tunneling current, phase transition Diode current, and total current density vs. applied bias for a symmetric MIM diode with ϕ¯ = 1.5 eV, s = 90 nm, and T = 300 K. (Note: See Appendix A listings A.2 and A.3 for MATLAB code.)
Chapter 5
CeRAM
Last chapter showed the physical model of the CeRAM storage cell I-V characteristics. In this chapter we will finally show the complete model, the actual device fabrication and SPICE modeling for circuit applications.
5.1
The CeRAM Concept The basic concept of CeRAM is that of a non-filamentary resistive RAM based on com-
pensation of disruptures in the co-ordination sphere of transition metals Mx caused by spacecharge and defects with (CO)x or Mz (CO)y ligands, where Mz represents a secondary transition metal. In other words, the switching properties of the transition metal oxide (TMO) compounds that could otherwise be negatively affected by non-stoichiometry and defects in the crystal structure are repaired through doping with natural ligands of carbonyl (CO)x and metal-carbonyl’s Mz (CO)y . Once the TMO structure has been properly compensated, the e– −e– interaction or repulsion can then be exploited for the switching and memory functions. This interaction is also known as electron correlation and is thus the namesake of the device i.e. Correlated electron RAM. The crystal structure of NiO takes the form of a 6-coordinate octahedral which is shown in figure 5.1a of a perfect crystal. Because, however, we know that the films deposited by CSD are in fact amorphous films, the crystal structure is anything but perfect. The carbonyl ligand in figure 5.1b is the Nickel Tetracarbonyl Ni(CO)4 that was chosen because of its preferential
42 triple bond between Carbon and Oxygen allowing carbon to easily substitute and repair any defects present in the molecular structure. The primary embodiment of this compensation is in the neutralization of excess Ni species by the following reaction: 4 CO + Ni ⇋ C4 NiO4
(5.1)
which is the result of π-backbonding in which electrons are donated from the d-orbitals of the transition metal to the anti-bonding orbitals of CO.
(a) Crystal structure of Nickel(II) Oxide
(b) Nickel-tetracarbonyl ligand structure
Figure 5.1: 3-D Crystallographic representation of the (a)NiO octahedral and (b)Ni(CO)4 structures.
The memory switching function of such a device is principally based on Metal to Insulator Transitions (MIT’s) for which TMO’s are commonly known to exhibit based on their incomplete 3d shells. Conduction in TMO devices is the result of a disproportionation reaction that changes the oxidation state of Ni. Disproportionation is known as a type of oxidation-reduction reaction in which both the reduced and oxidized species coexist. Thus, This reaction takes the form:
2 Ni2+ ⇋ Ni1+ + Ni3+
(5.2)
43 which means that the level 3d8 is split as d8 + d8 → d7 + d9 , and the defect free materials only contain this reaction such that U ∝ −kT ln
CN i3+ CN i1+ (CN i2+ )2
(5.3)
or, as represented in an oxide compound the reaction is shown as
(Ni2+ O2− )2 ⇋ Ni1+ O2− + Ni3+ O2− .
(5.4)
This reaction is called a disproportionation reaction when it occurs from left to right and a comproportionation reaction when it occurs from right to left. In essence, Ni1+ gains an electron, and Ni3+ loses an electron. Losing an electron is called ionization and has energy (I). Gaining an electron is called affinity and has energy (A). The difference between the ionization energy and the electron affinity energy creates an energy gap U which is the electrostatic energy that repulses two electrons. Within crystal sites, Ni atoms, which when in their most common 2+ oxidation state deep inside the 3d shell are stable, are considered localized and do not allow for electrical conduction. However, Mott demonstrated that these materials can be made to conduct when a definite amount of energy, equal to the energy gap U , is provided to the system (e.g. injected electrons, heat, pressure) thus creating the Ni1+ and Ni3+ states that are free to move about the lattice by electron transfer. The breakthrough of CeRAM comes with the defect compensation from metal-carbonyl complexes M(CO)x where M represents all transition metals and more specifically in our case, Ni(CO)4 . As previously described, the COx bond with Ni contributes an electron in a π-bond and compensates for any hole defects in the lattice. This allows the NiO lattice to be in its conductive Ni1+ + Ni3+ oxidation states as deposited thus eliminating the requirement for a high electroforming voltage before the device can transition from metal to insulator and back again. Thus, NiO becomes mostly a d8 ⇋ d9 + d7 material which can have a reversible quantum phase transition (∼ 10’s of femtoseconds) in the application of a voltage such that at high voltage (VSET ≈ 1.2V ) injects electrons from the electrode in quantity enough to
44 decrease the screening length around each Ni ion and allow electrons to overcome the charge gap U moving some electrons to the upper Hubbard sub-band and creating holes in the lower Hubbard sub-band. Thus, a metallic phase appears. In most cases, the VSET causes the transition from semiconducting behavior to metallic behavior to occur ballistically following Schottky or thermionic field emission leading up to the transition. Design of the interfaces to achieve optimum low set currents ( i.e. ICOM P LIAN CE ) which effectually reduces the on state current ION in the metallic phase of the device.
5.2
Device Fabrication
Pt Top Electrode NiO (Multi layer)
Pt Bottom Electrode SiO2/Si Substrate
Figure 5.2: The CeRAM MIM-cap test structure.
CeRAMs are constructed in a Metal-Insulator-Metal (MIM) capacitor configuration (shown in Figure 5.2) in which the insulator layer is replaced with a Transition Metal Oxide (TMO). For research device fabrication, CeRAM structures are processed on 4” silicon substrates with a thickness of 500µm and an 5000˚ Alayer of thermally grown silicon dioxide. The metal, in this case Platinum, is deposited using physical vapor deposition (PVD), or more specifically, RF sputtering, to a thickness of 2000˚ A. Thin films of NiO were deposited on these Pt/SiO2 /Si substrates using spin-on metal-organic-decomposition (MOD) of Octane based precursor solution prepared by Kojundo Chemical Laboratory Corporation, Japan. The
45 precursor can then be further diluted with Octane to control molarity and subsequently, the concentration of nickel-carbonyl complexes present in the films. The precursor is then applied using a spin coater and subsequently dried and pyrolyzed through open air baking at temperatures ranging from 150◦ C to 300◦ C . This process is then repeated several times to achieve the desired final thickness and to include any compositional variations on a per layer basis. With this spin on MOD process, it is also important to note that very fine control of film thickness and wafer uniformity can be controlled simply by adjusting the rotational speed of the wafer, or other substrate for that matter, during the initial coating phase of the process. The completed film stack is then annealed in a diffusion furnace with oxygen flow at a temperature of ≤ 450◦ C to crystallize the NiO layer. Final film thickness is then measured using ellipsometry, and the top electrode Pt layer is deposited by RF sputtering. The test structures are then defined using contact mask optical alignment with positive photo resist, and etched using an ion milling process. Finally, the remaining photo resist is stripped from the patterned devices using an oxygen plasma asher leaving the devices clean and ready for test. Figure 5.3 illustrates the CeRAM test structure process flow. Yes
Start SiO2/Si Substrate
Pt deposition (PVD) Bottom Electrode
Pt deposition (PVD) Top Electrode
Post Deposition Furnace Anneal
Dehydration bake
Pt electrode processed on different day ?
Pyrolized
No
Precursor dilution (Octane)
Drying
Spin Coating
Repeat to desired final thickness and per layer composition variations
Photolithography
Stack Etch Ion Milling
Photoresist Strip
End CeRAM Test Structures
Figure 5.3: Illustration of process flow for CeRAM test structure.
46
Figure 5.4: (a)Schematic diagram and (b)100× magnification top view image of CeRAM test structures. Encapsulated structures with varying dimensions and off resistor contact pads(upper) and direct probe (lower center) devices for I-V characterization of CeRAM.
For fabrication of these test structures for electrical characterization, a variety of photo-
47 mask sets were created and the most comprehensive of which is shown in 5.4. When processing the full mask set, which contains a total of 4 mask steps, arrays of ratioed capacitor structures are available that feature full dielectric encapsulation, off-device contact pads to eliminate probe damage to the actual device, large and small via contacts to identify any issues presented by contact resistance, and square vs. rectangular devices to analyze any performance variations due to device dimensions. This mask set was designed in such a way that different device structures can be processed simply by skipping over mask steps in the process sequence. For example, if only the first two masks are used and the final metallization step is skipped then longitudinal structures are made available (5.4 (a) lower left) to test the behavior of the material for in-plane devices with varying electrode spacing. Similarly, if the first two masks are used and the final metallization step is processed, structures for direct probing are made available and are shown in 5.4 (a) bottom center. Additionally, a single photo-mask was developed containing a variety of feature patterns and sizes to allow for analysis of size and edge effects on the electrical performance of the test devices which include square, rectangular, and circular structures with corresponding surface areas for each pattern to isolate edge effect variations in the electrical behavior of the devices.
5.3
Characterization and Analysis In order to properly understand the factors affecting device performance, a variety of
analysis techniques are used to determine the physical and chemical characteristics of the materials used in that device. Things like surface, bulk, and interface microstructure play a critical roll and can be analyzed through various forms of microscopy. Elemental compositions impurity concentrations, chemical state identification in bulk materials and thin layers will affect device performance and need to be analyzed if ultimately to be improved upon. Still, electrical measurements provide some of the most sensitive techniques for measuring factors that will fundamentally determine device performance.
48 5.3.1
Physical and Chemical Characterization
To understand the electrical properties of a CeRAM device it is first of critical importance to understand the physical attributes of thin NiO films as well as the chemical composition of these films. X-ray photoelectron spectroscopy (XPS) was used to determine the chemical composition at shallow depth of penetration of the grown NiO films for CeRAM. With this technique it is possible to determine the oxidation states of Ni ions in the NiO bond. Figure 5.5 shows the Ni 2p spectrum of the CeRAM NiO films which match very well with standard results for stoichiometric NiO [63]. From the plot it is clear that the Ni2+ bond state for the NiO is present from the Ni 2p3/2 peak at 854.5 eV as well as someNi3+ species which are present in the Ni2 O3 compound from the peak in the 855.8-856.6 eV energy range. This conformation of the presence of the Ni2+ oxidation state is very significant in that the key to the Mott-like charge transfer metal insulator transition, which is the basis for CeRAM, is reliant on a disproportion reaction occurring in which the Ni2+ ion is both oxidized and reduced to form both Ni1+ and Ni3+ are produced and there is no trapping, only Ni1+ and Ni3+ pair formations as described by Mott. Evidence of both the Ni2+ and Ni3+ oxidation states is also present in the Oxygen 1s band which is shown in figure 5.6. As is evidenced by the plot the Oxygen peak at an energy of 529.8 eV corresponds nicely with stoichiometric NiO while the hump at 531.6 eV shows the existence of Ni2 O3 species in the as deposited films as well. All XPS standard peaks were referenced from the NIST X-ray Photoelectron Spectroscopy Database [64]. The surface topology of a prepared sample can be examined using a Scanning Electron Microscope (SEM). Plane-view SEM imaging techniques were able to observe surface defects on the CSD deposited NiO surface as well as any surface structural properties. The image displayed in figure 5.7 shows a hole in the surface of the film ∼ 400 nm in diameter as well as general surface roughness with features sizes in the 10’s of nanometers. Controlling the
Intensity [a.u.]
x10
3
49
70 65 60 55 50 45 40 35 30 25 20 15 890
Ni
2+
3+
Ni
Ni 2p
880
Ni 2p
1/2
870
3/2
860
850
840
Binding energy [eV]
Figure 5.5: XPS Spectra for Ni 2p energy spectrum in carbonyl ligand doped NiO CeRAM
roughness of the film is critical for scaling down to nanometer sized technology nodes where the desired total dimensions of the active device would be on the order of 50 nm. It would not be possible to rely on structure uniformity in large arrays across an entire wafer if a single grain were on the order of 20% of the total feature size. In order to improve the surface of the CeRAM films, work was done to modify the grain size by altering the molarity concentration of the precursor solution during spin on deposition. To determine the effects on surface morphology observed in the SEM analysis of the solution molarity and number of layers, films were grown of multiple layers with both high and low molarity precursor solutions. Atomic Force Microscopy (AFM) scans were done to determine surface roughness profiles of the films. As you can clearly see from the images in fig. 5.8, the surface roughness of the film can be controlled simply by changing the molarity of the precursor solution during film deposition. Standard film layers of higher molarity solution
x10
3
50
60 50
O 1s
Intensity [a.u.]
NiO
40 30 20
Ni O 2
3
10 0 540
538
536
534
532
530
528
526
Binding energy [eV]
Figure 5.6: XPS Spectra for O 1s energy spectrum in carbonyl ligand doped NiO CeRAM
exhibit larger grains and thus rougher films where as layers deposited at a lower molarity produce smaller grains resulting in smoother films. In addition to the surface morphology that is observed by AFM type scans, and since our ideal structures for switching and memory devices are not homogeneous through the thickness of the film, Transmission Electron Microscopy (TEM) scans were taken so we could observe the crystalline structure of the film through its thickness. Note the formation of large grain type structures throughout the film and the roughness on the top surface (right side of the images) propagated as the large grains are formed throughout the deposited layers all the way up to the surface of the top Pt electrode (Fig. 5.9). At high magnification (Fig. 5.9d) it is straight forward to see that there are many defects in the crystal structure and that multiple different crystalline structures exist in the films. In certain areas it is obvious that cubic NiO is dominant where in other areas of the film it appears that a distorted rhombohedral orientation
51
Figure 5.7: SEM image at 20,000x magnification of defect and surface morphology Nickle Oxide based CeRAM CSD film.
(a) Standard Layer
(b) With surface modifying layer
Figure 5.8: AFM topography scans for NiO films deposited using different precursor molarities (scan size: 2µm)
exists. Scanning Transmission Electron Microscopy (STEM), which is also a high-resolution
52
(a)
(b)
(c)
(d)
Figure 5.9: cross sectional HRTEM images of Pt/CSD deposited NiO/Pt CeRAM
ii
scan but is different than the HRTEM technique used above, has the advantage of showing the distinction in grain or dislocation sizes of the highly doped region and the lower doped region of the CeRAM films (figure 5.10). Additionally, STEM is useful for generating Electron Energy Loss Spectroscopy (EELS) line scan analysis which is useful for determining atomic concentrations through a small cross-sectional scan allowing one to pinpoint concentrations
53 through the thickness of the film; I will present more on this later. As you can see in figure 5.10b, the film layers closer to the bottom Pt corresponding to the higher doped region have larger grains than the lower doped layers closer to the top Pt.
(a)
(b)
Figure 5.10: STEM image of CeRAM cross-sectionii
EELS analysis was used to study the composition and chemical bonding properties of CeRAM samples prepared with both low and high ligand doping compositions. EELS was chosen because it is ideally suited for measuring elements with relatively low atomic number and is perhaps the best method for spectral analysis of carbon compounds. If you study the subfigures in figure 5.11, in which EELS analysis was done on isolated layers with low carbonylligand doping concentrations (5.11b) and high carbonyl-ligand doping concentrations (5.11c), it is exceptionally clear that the carbon content in the highly doped region is roughly double that of the lower doped region which confirms the approach used for controlling this doping concentration was successful. As was previously mentioned the line scan EELS analysis results, shown in figure 5.12, clearly show that the concentration of carbon through the first 25 nm’s of the film on the scan line was nearly double that of the remaining thickness of the film.
54
(a)
(b)
(c)
(d)
(e)
(f)
(g)
Figure 5.11: Electron energy loss spectrum scans for CeRAM sample with layered low carbon doping concentration layers (LD) on top of high carbon concentration layers (HD).ii
55
(a)
(b)
Figure 5.12: EELS line scan through cross section of carbonyl doped NiO based CeRAM test structureii
5.3.2
Experimental Setup
We constructed CeRAM devices of simple MIM-like capacitor structures that can be directly probed from top to bottom as well as structures designed with off device contact pads. These structures are illustrated in Figures 5.2, 5.4. For typical experimentation, devices are constructed of n-type Si with a 500nm thermally grown oxide substrates, Pt bottom electrode, NiO layer, and Pt top electrode. Electrical contact to devices is done using a micro-probing station with probing accuracy down to 1µm. IV characterization was done using a Semiconductor Parameter Analyzer (SPA), and to perform hysteresis cycling and low volume pulse cycling on the devices, a graphic user interface (GUI) was created using LabVIEW for operation of the SPA and data collection (Fig.5.13). The LabVIEW GUI allows the user to perform a variety of tests and plots the data in real time on the screen so the operator can make parametric adjustments on the fly as well as collect data in text files which can later be plotted and analyzed. These tests include: Initial sweep, where the initial as deposited I-V characteristics of the device can be characterized; Single Set/Reset, which performs a single set cycle in either polarity followed by a reset also in either polarity; Full Hysteresis, which performs a set and ii
Images provided by Dr. Ning Lu, Dr. Ce Sun, Dr. Jinguo Wang, Dr. Moon J. Kim, Dr. Geunhee Lee, and Dr. Orlando Auciello, The University of Texas at Dallas.
56 reset sweep in both positive and negative polarity to show any performance variation in bipolar and nonpolar operation; and finally, cycling which performs repeated set/reset cycles for a user defined number of cycles allowing the generation of repeatability and fatigue characteristics of the DUT. CV measurements were performed using an LCR meter and Symetrix Othello software which was specifically designed for testing automation of Ferroelectric capacitors in a similar MIM configuration.
Figure 5.13: LabVIEW GUI
High volume pulse cycling is somewhat more involved than the DC sweep type characterization that is used to generate the characteristic IV data though it is critical to ensure reliable operation in non-volatile memory application. Where the SPA used for generating IV data and sweep cycling data is equipped with an internal current compliance circuit the pulse pattern generator that met the necessary power requirements is not. Because of this
57 lack of internal compliance control in the testing equipment it was necessary to create external circuitry capable of limiting the current on a SET cycle while also being capable of allowing sufficient current for a RESET to occur. This same type of external compliance circuitry is what would need to be incorporated on silicon for memory arrays of CeRAM as well as other forms of resistive memories. High volume pulse cycling is currently performed using a Pulse pattern generator and Oscilloscope to monitor the input and output and using discrete circuit solutions inline to provide current compliance. A labVIEW GUI (Fig.5.14) was also created to perform pulse cycling because of a need to perform many operations in rapid succession and collect data. For example, consider a pulse testing sequence for the 1T1R compliance circuit if figure 5.17. The sequence would be performed as follows all while collecting data to be analyzed in the future: 1) The current state of the device needs to be read by applying a low amplitude read pulse across the 1T1R circuit. A high amplitude pulse is applied to the gate of the transistor to ensure that current can flow freely through the circuit and be sensed at the oscilloscope. 2) Assuming the device is in the off or high resistive state, a set operation is performed by applying a very fast (on the order of 10’s of nanoseconds) high amplitude pulse is applied across the 1T1R circuit while simultaneously pulsing the transistor gate with a precise voltage so as to limit the amount of source to drain current IDS , providing current compliance to the CeRAM. 3) The current state of the device is once again read to determine if the set operation was successful of needs to be repeated. 4) Assuming the set operation was in fact successful, a reset operation is performed by applying a medium amplitude pulse, typically a few orders of magnitude slower than the set pulse for external compliance circuitry (the reason for which will be discussed later), while simultaneously pulsing the transistor gate with a sufficiently high voltage as to not impede current flow through the CeRAM so sufficient current is provided for a successful reset. This entire sequence is then repeated for a specified number of cycles to collect repeatability and fatigue data. Custom testing solutions are currently being investigated that will ease in monitoring high speed switching as well as more accurately emulate real world
58 circuit solutions.
Figure 5.14: Pulse switching GUI
One issue that has had a significant impact on the on the performance of RRAM devices due to their dynamic behavior with respect to current control is parasitic capacitance and CeRAM is no exception. Because the basic operation of CeRAM relies heavily on how accurately we control the current allowed to flow through the device, it is necessary to consider all additional sources of charge when in the low resistance state, excess current can be sourced. In a conventional testing setup for IV characterization for example, there are many sources of excess charge even outside the device itself. Consider a CeRAM connected to an SPA in a conventional manual probe station where bias is supplied to the top electrode of the device and the bottom electrode of the device is grounded. Assume we are using prototypical BNC coaxial cables with a 50Ω impedance and a length of 4’ to connect the top and bottom electrodes to source and ground respectively. Considering that the typical cable in this configuration has about 30pF of capacitance per foot the parasitic capacitance due to cabling alone can be estimated at ∼ 240pF. Additionally, there is capacitance associated with the probe contacts and
59 the built in dielectric capacitance of the device itself. In order to calculate the total additional charge contribution of the various sources of parasitic capacitance one would need to use the following formula: Q = CT otal × ∆V,
(5.5)
where CT otal = (Cp + Cd + · · · ). If CT otal is large enough, the device could experience a hard breakdown destroying that cell for any further operation. For smaller capacitances, the excess charge is not so catastrophic, but can still contribute to a change in the LRS of the device since the LRS is proportional to the total current through the device which is controlled by Icomp . An example of the equivalent circuit with ideal current limiting is shown in Figure 5.15.
Cd
Cp
CeRAM + − I=Icomp
Figure 5.15: Equivalent circuit for testing setup of CeRAM with external compliance circuitry including (a)parasitic capacitance from cables, probes, and contacts, (b)built in dielectric capacitance in off state which causes current “snapback” during set.
It is precisely because of this parasitic capacitance that great care must be taken when implementing current compliance into the testing scheme. Several methods of controlling the switching current of CeRAM devices have been employed to determine the best fit to
60 achieve as close to ideal current limiting as possible. These methods include instrument current compliance provided by parametric analysis equipment (e.g. SPA), load resistor limiting (Fig. 5.16), a 1T1R circuit in which the BE of the CeRAM is connected to the drain side of a mosfet transistor and IDS is controlled by the transistor gate voltage VGS (Fig. 5.17), and the most controllable and consistent of the bunch, but also most complex circuitry, is the cascode current mirror compliance circuit in which the current can be precisely limited for a large range of bias voltages by using a constant current source on the reference leg of the mirror (Fig. 5.18). The simplest method requiring no additional circuit components for parametric analysis would, of course, be the instrument current compliance provided by the SPA, but, as is often the case, the simplest method is also the least reliable. This lack of measurement reliability primarily stems from the fact that the CeRAM switching times are so fast (on the order of ns or smaller) where the instrument response time is relatively slow in comparison (on the order of tens of µs). This means that for a set operation, for instance, the device has already transitioned from the HRS to the LRS long before the instrumentation has time to catch up and measure that the compliance limit has already been overshot.
I IDUT
CeRAM
RLoad
V
(a) (b)
Figure 5.16: Load resistor compliance circuit(a) and I-V response(b)
The next simplest current control method, though faster than the instrument current
61 compliance, would be the serial load resistor configuration and is not significantly better for several reasons. This configuration is faster because the response time of a resistor is a function of its RC time constant and for even a typical axial type resistor the parasitic capacitance Cp is on the order of tenths of pF which for a 1kω resistor equates to a time constant on the order of tenths of ns and is reasonably within range of the CeRAM switching time. The reason this solution is not the most ideal comes from the input response of a resistor as well as the voltage divider created by two resistors in series, which is essentially what we have with a load resistor connected to the Bottom Electrode (BE) of a CeRAM element. The concept is that by utilizing Ohm’s law V = IR, we can pick a resistor such that Icomp = Vin /RLoad (Fig. 5.16b). This load resistor configuration creates several non-trivial problems by its implementation however. First, because there is inevitably going to be some dispersion in the set and reset voltages, it is impossible to pick a resistor that will give the same compliance current from cycle to cycle. Also, if there happened to be any internal dispersion in the CeRAM resistance not due to voltage dispersion, the same problem exists. The issue is that if we were to consider the node between the CeRAM and RLoad as BE which, if we remember from the ideal case, would be grounded until the point when the CeRAM switches from HRS to LRS, we actually have a voltage divider in which
VBE = Vin
RLoad RDU T + RLoad
(5.6)
where RDU T is the series resistance of the CeRAM device. Secondly, a passive circuit element, such as a resistor, allows for no consideration of the current state of the CeRAM device which means that some additional means of allowing sufficient current to flow on a reset cycle is necessary. One potential solution to this problem is to include a Schottky diode in parallel with the load resistor enabling bipolar switching of the CeRAM device where the set operation is performed in the positive polarity and current is limited by the load resistor and the reset operation is performed in the negative polarity and sufficient current is allowed
62 to flow relatively unimpeded through the Schottky diode. This is certainly a viable solution especially when considering crosspoint array structures for 3D architectures, but still fails to address the first issue with the inconsistent current limiting. One additional issue that I have not found discussed anywhere in the literature, but is still a very real issue, is the fact that in a standard CMOS process resistors are an in-plane device and very susceptible to any variations in lithography and etch. Because resistors are made based on knowledge of resistivity of the metal layer material and certain resistances are obtained by creating metal lines of particular widths and lengths, any variation in the line width or length due to etching variations will cause a variation in resistance which changes the voltage needed to obtain a specific current compliance.
IDS
VGS
IDUT
CeRAM
+
VGS
-
VDS
(a) (b)
Figure 5.17: 1T1R MOSFET compliance circuit(a) and I-V response(b)
The next solution which is an improvement over the simple load resistor circuit is to use a MOSFET in a 1T1R configuration to provide the current compliance. This solution more so than the other solutions provided in this section is also the most likely implementation in a large memory array circuit as well because not only can the MOSFET provide current limiting it can also provide isolation to the individual memory cell element necessary for large arrays. The concept of this particular compliance solution is that by placing an adequately sized
63 NMOS transistor between the CeRAM BE and ground, the current allowed to flow through the circuit is controlled by holding a bias on the transistor gate which provides a constant VGS and therefore a relatively constant IDS through the active region of the transistor I-V response. Operationally the 1T1R works as follows: 1) When the memory element is not being programmed or read, VGS = 0V and the transistor is off. 2) During a SET operation a small bias is held on the transistor gate bringing VGS > Vth and operating in the active region of the transistor where IDS ≤ Icomp . 3) During a RESET or read operation VGS >> Vth and IDS ≥ Ireset allowing current to flow through the CeRAM essentially unimpeded. The 1T1R configuration, though significantly better suited than a load resistor, still comes with some implementation and design issues. The transistor must be designed with a W/L ratio that provides sufficient IDS for the different modes of operation in the transistor active region (see Eq. 5.7). It is also important to consider that to achieve consistent compliance over the widest range of operating voltages which can be done by designing the transistor with a larger width W which will increase the transconductance gm (see Eq. 5.8) thereby shortening the triode region and and extending the active region closer to 0V . There are tradeoffs from any of these design modifications and it is important to remember that increasing gm will also increase IDS to changes in VGS and increase parasitic capacitance Cgs (see Eq. 5.9). ID =
µn Cox W (VGS − Vth )2 2 L
r
gm = 2
Cgs =
W µn Cox ID L
εox W L = Cox W L tox
(5.7)
(5.8)
(5.9)
The most elegant solution for providing a consistent current compliance over a larger range of voltages is to implement a Cascode current mirror circuit (Figure 5.18). Because the current through the mirror is provided through a current source on the reference side of the
Icomp
64
IDUT
IDUT
CeRAM
VDUT (a)
(b)
Figure 5.18: Cascode current mirror compliance circuit(a) and I-V response(b)
mirror circuit, a much more precise compliance current can be provided to the CeRAM and with much finer adjustment control.
5.3.3
Results and Discussion
This section will provide experimental results for CeRAM devices covering both basic parametric characteristics and functional characteristics for use in real world application. A better understanding of the testing methodology described in the previous section will be gained from an analysis of the experimental results provided by the various circuit configurations and test implementations.
5.3.3.1
I-V Characteristics
CeRAM devices demonstrate a bi-stable switching behaviors and can be programmed with either bipolar (Fig. 5.19(a)) or unipolar(Fig. 5.19(b)) switching methods. This type of switching behavior has been observed by other groups and is referred to as “nonpolar” switching [52, 65] meaning that bipolar and unipolar switching characteristics coexist creating a polarity independent system. One advantageous characteristic unique to CeRAM devices is the initially
65 conductive or “born-ON” behavior exhibited by as deposited film structures leading to devices that do not require electroforming and thus need only be supplied with Set and Reset voltages for programing in integrated circuit application. By reducing the voltage levels required for operation of the array, low power operation becomes possible and the necessary real-estate required for peripheral circuitry decreases.
Figure 5.19: Typical I-V characteristics for (a)bipolar and (b)unipolar switching by voltage sweep.
A strong correlation has been established between the level of overshoot current during a Set operation (ISet ) and the maximum current flow required for a Reset operation (IReset ). The “OFF-State” or high resistance state exhibits a strong dependence on device area which directly effects the limit at which ISet must be clamped off. From these relationships we see that there is in fact a strong defining relationship between IOF F and ION which defines the current requirements for limiting and select circuitry which in turn effects the overall minimum size of a memory circuit. For sufficiently large programing current it can be shown that IReset ∝ISet . However, when the programing current is reduced below an arbitrary threshold, IReset begins to saturate. To illustrate this, the mean IReset values of fifteen cycles at varying compliance levels for 10x10µm2 and 20x20µm2 structures are shown in Fig. 5.20. The difference in saturation
66 levels can be explained by the reduction in OFF-State dielectric capacitance with the reduction of device area. This means at low programing current the CeResistor sources current during dielectric snapback at SET and the minimum IReset saturates. Therefore, scaling the device minimizes dielectric capacitance, lowering the minimum IReset and maintaining ON-State resistance. Additionally, it is believed that any external pads, cabling, and equipment are also sources of stray capacitance from which current is sourced during the transition from high to low resistance state “Set”. Refer to the equivalent circuit for a testing setup with external compliance is shown in Fig. 5.15. These observations are consistent with K. Kinoshita et al. [66] who observed that parasitic capacitances from the current limiting circuitry have an adverse effect on the maximum IReset . Moreover, this suggests that the more ideally the current limiting circuitry can be implemented, the closer IReset comes to IReset ∝Icomp . This proportionality can be explained by considering the ON-state of CeRAM as a correlated metal and observing the Mott criterion which describes the critical point at which the metal-insulator transition occurs as: n1/3 aB ≈ 0.26 ,
(5.10)
where n is the electron concentration and aB = 4πǫ~2 /me2 is the effective Bohr radius. In the Mott criterion, n should be referred to as the free electron concentration nf . If the localized electron concentration is nl , then nf + nl = n = const. Though the insulator side always corresponds to nf = 0 nl = n , the metal side is in fact variable. The SET current compliance determines how many electrons become free when the SET occurs, and nf = K1 ICompliance .
67 On the other hand, the free electron concentration determines the ON-state resistance as RON = K2 /nf = K2 /(K1 ICompliance ). Our model predicts that the RESET voltage is stable which has also been confirmed experimentally. Hence, IReset = VReset /RON =
K1 VReset ICompliance . K2
(5.11)
Thus, the current at the Reset point is proportional to the SET compliance current because K1 , K2 and VReset are constants. Evidence of this is shown in figures 5.20 and 5.21. At the point where saturation occurs, IReset is dominated by the parasitics in the system and the above equation no longer holds true.
-2
10
-3
10
(10
2
m)
2
m)
I
Reset
(A)
(20
I
Set
= I
Reset
-4
10
-4
-3
10
10 I
Comp
-2
10
(A)
Figure 5.20: IReset vs. Icomp at varying set compliance levels for 10 × 10µm2 and 20 × 20µm2 structure. By using techniques to reduce IOF F through process tailoring, and appropriately adjusting ISet(orcompliance) /IOF F , we have successfully achieved sub − 100µA reset currents for
68 4
10
R
ON
R
on
(
)
3
10
2
10
-2
-3
10
I
reset
(A)
10
I
Reset
-4
10
-4
-3
10
-2
10
I
10
(A)
Compliance
Figure 5.21: Ron vs. Icomp at varying set compliance levels for 10 × 10µm2 structure
externally current limited devices as large as 25µm2 for which the I-V characteristics are shown in Fig. 5.22. From this example you can see that IReset does not exceed 70µA for ISet limited at 50µA. Taking into account the effect of stray capacitances on IReset and the already observed result of sub − 100µA reset current, with the implementation of on-chip compliance circuitry, the general concern of high currents in these types of devices becomes a non-issue. Cell scaling results also give way to very favorable predictions as dimensions are scaled to meet with deep sub-micron technology nodes. As devices are scaled down, the OFF-state resistance increases at a much faster rate than the ON-state resistance which leads to a widening of the read memory window with scaling. This is easily explained due to the area dependence of the OFF-state resistance and the dependency of the “Reset” operation on Icomp . That is, since the voltage required to perform both set (VSet ) and reset (VReset ) operations remains relatively constant with respect to area and the OFF-state resistance increases as a function of
69
-5
8.0x10
-5
7.0x10
Set Reset
-5
6.0x10
Current (A)
-5
5.0x10
-5
4.0x10
-5
3.0x10
-5
2.0x10
-5
1.0x10
0.0 0.0
0.5
1.0
1.5
Voltage (V)
Figure 5.22: I-V curves for CeRAM cell programmed using a 50µA compliance limit showing a max IReset of approximately 70µA.
area, the compliance current can be reduced to maintain the appropriate ratio of ISet /IOF F . Since IReset has been shown to be dependent of Icomp and VReset does not change, the ONstate resistance must change as a function of Icomp which is a much more gradual change with respect to area.
5.3.3.2
Pulse response
Using external compliance circuitry as was shown in figures 5.16, 5.17, 5.18, CeRAM devices have shown very promising repeatability results from pulse cycling tests indicating high, up to 98% switching repeatability in a 1T1R discrete external compliance configuration 5.23. Consider a discrete 1T1R testing configuration using a Diodes incorporated DMN2004k enhancement mode N-channel MOSFET mounted into a 3 terminal TO-5 package. The DC
70
Figure 5.23: 200 ms Reset pulse, 50 cycles Switching Reliability: 98%
I-V characteristics for a relevant range of gate voltages are shown in figure 5.24 as collected by the HP-4155B semiconductor parameter analyzer. From these curves it was determined that using a gate bias voltage of 0.85 V provided an ∼1 mA current compliance over the desired programming voltage range. The effects of input pulse width on the Set and Reset cycles have been carefully examined. The results have shown that the pulse width on the set cycle is of minimal importance. As long as the appropriate bias level is achieved, pulse widths in the 10’s of nanoseconds have no trouble switching the device from the insulating to the metallic state. The main limitation in this case is that of the pulse generator and from the experiments it has been determined that programming pulse widths of less than 50 ns have a poor pulse shape in this configuration when using an Agilent 81110A pulse pattern generator. Even though the generator is rated to be able to provide pulses with smaller pulse width than this, to actually achieve these pulses it is necessary to accurately program the load resistance into the generator so it can adjust to a proper RC time constant. In our case, since the load resistance changes when the device
71 DMN2004k: N-Channel enhancement mode MOSFET V
=1.00V
V
=0.95V
V
=0.90V
V
=0.85V
V
=0.80V
V
=0.75V
V
=0.70V
GS
-2
10
GS
-3
10
GS
Drain Current I
D
[A]
GS
GS
-4
GS
10
GS
-5
10
-6
10
0
1
2
3
4
Drain to Source voltage V
DS
5
6
[V]
Figure 5.24: MOSFET transistor curves
switches, it is not possible to accurately indicate the load which limits the achievable pulse width. For the reset case however, the pulse width is quite critical and is drastically affected by the testing setup as well as device size. Figure 5.25 shows the effect of the reset pulse widths on switching reliability of a 400 µm2 device over 50 cycles.
5.3.3.3
Reliability and Retention
Using only the external compliance provided by the SPA, we have observed a wide signal margin of more than one order of magnitude for 100 write/read cycles, as shown in Fig. 5.26. Additionally, the dispersion in the ON and OFF state resistance on average is less than one order of magnitude. Since the ON state resistance is believed to be heavily reliant on the accuracy at which the current is clamped off during a set operation, the dispersion in the ONstate resistance is expected to show noticeable improvement with on-chip compliance. As a
72
(a) Switching reliability: 94%
(b) Switching reliability: 64%
(c) Switching reliability: 32%
Figure 5.25: Average read voltage across a 50Ω sense resistor for reset pulse widths of (a) 200 ms, (b) 100 ms, and (c) 50 ms.
result, as devices are scaled down and compliance circuitry is integrated on Si, the read margin should increase while simultaneously the dispersion in ON and OFF state resistances decrease. To read the state of the CeRAM cell a small voltage is applied to the top electrode such that VRead < VReset
(5.12)
and sensing the output current to determine if the CeRAM in the low resistance ON state or high resistance OFF state. In order to test reading endurance out to a high cycle count, two CeRAM devices were programmed into known states and pulsed with a 0.2V square wave at
73 6
10
5
Resistance (Ohms)
10
4
10
3
10
Read Margin
2
10
1
10
R On R Off
0
10
0
20
40
60
80
100
Cycle Number
Figure 5.26: ROn and ROf f resistance of 100 consecutive cycles at room temperature and the corresponding read margin.
a frequency of 50MHz. The output is then sensed using a digital oscilloscope by reading the voltage across a load resistor. The progression of this measurement is as follows: (1) An initial measurement is taken of the Device Under Test (DUT). (2) The DUT is cycled for a given number of cycles which is determined by measurement frequency, time, and total number of fatigue cycles. (3) A subsequent measurement is taken of the DUT. This process repeats until the total number of fatigue cycles has been reached based on total measurement time and a final measurement is taken. The results of read endurance testing is shown in Fig. 5.27. These results show no sigh of degradation in the ON or OFF state resistance after 1012 read cycles at room temperature using a 0.2V read voltage. CeRAM devices have been tested in a wide temperature range from 4K to 150◦ C with minimal observed effects on the I-V Characteristics in samples with external compliance cir-
74
6
10
5
R On/R Off (Ohms)
10
4
10
On State Off State
3
10
2
10
1
10
0
10
-1
10
1
10
3
10
5
10
7
10
9
10
11
10
13
10
Cycles Figure 5.27: Read endurance for high(ROf f ) and low(ROn ) resistance states of a (10×10)µm2 cell at room temperature with 0.2V read voltage.
cuitry (Fig. 5.29). Tested samples exhibited non-polar switching characteristics with stable switching parameters throughout the entire range. To test the nonvolatile data retention at high temperature, cells were programmed into known resistance states and baked at elevated temperatures for 1 hour. At the completion of baking, the samples were removed from the hot plate and tested at room temperature. The respective resistances are shown in Fig. 5.28. As a result we have shown excellent data retention properties with no degradation of either ON or OFF state resistance up to 300◦ C for a period of 1 hour. As it is well known that the Mott transition is a Quantum phase transition, Figure 5.29 shows this characteristic clearly since the quantum phase transition is temperature independent and our devices exhibit switching behavior over the temperature range of -269 ◦ C to +150 ◦ C.
75
5
10
4
Resistance (Ohms)
10
3
10
2
10
1
10
On State Off State
0
10
0
50
100
150
200
250
300
350
o
Hotplate Temperature ( C)
Figure 5.28: Nonvolatile data retention of high and low resistance states at elevated temperatures up to 300◦ C for 1 hour.
5.4
Modeling and Simulation
5.4.1
Circuit simulation
In a resistive memory, the resistance value tells if we have a logical “1” or “0”. When we have a Logical “0” the resistance is very low and behaves as an electrical short circuit. When we have a logical “1” the resistance is very high and behaves as an electrical open circuit. For the purpose of simulating simple circuits and circuit arrays a SPICE model was created for CeRAM that could provide a rough representation of the devices behavior as well as contain some sort of state memory. In the model, an RS latch was used to remember the current storage state of the device (Ron or Rof f ); a voltage controlled switch with two different resistances is used to model the different states of the CeRAM device; Op-amp comparator circuits are used
76
(b)
(a)
(c)
Figure 5.29: Full I-V hysteresis measurement showing bi-stable behavior at operating temperatures (a) -269 ◦ C (b) 25 ◦ C and (c) 150 ◦ C.
to provide the logic for the RS latch to determine if the next operation to be performed is Set or Reset. The schematic representation of the part and simulation results of the CeRAM model are shown in Figures 5.30 and 5.31 respectively. The comparator circuit responsible for determining if a SET or RESET input was provided to the CeRAM and therefor indicate the current state of the CeRAM device needs to detect if an input is within a particular range. For this one Op-amp is used to determine if the input is above a particular level and the other Op-amp is used to determine if the input is below a particular level. The tolerance range of these levels is controlled through the voltage
77 OA1
Vset
R1 AND1
OA2
INPUT
LTCH1
R2
OA3 SW1 R3 AND2
OUTPUT Vreset OA4
R4
Figure 5.30: Circuit schematic representation for CeRAM SPICE model
divider of resistors R1 and R2 using the following equation:
R2 =
R1 (1 − X) X
(5.13)
T 1.05
(5.14)
where X=
and T is the percent tolerance. In order to provide sufficient voltage for the upper tolerance level the source voltage must be set using the following equation: VS = VREF
T 1+ 2
(5.15)
where VREF is either VSET or VRESET and 0 < T < 1. Similarly the tolerance range for the RESET comparator can be controlled through R3 and R4. Both the SET and RESET comparator circuits output +5V signals when the input is in range and 0V otherwise. these signals are compatible with the logic levels used for the AND gates and RS Latch used in the CeRAM model. The truth table for the SR latch in table 5.1 shows that when the set
78 comparator outputs +5V, the SR latch is set and the output Q is +5V. However, if the input voltage is at VRESET then the reset comparator output is at +5V which resets the latch and the output Q is 0V. If the input is not within either threshold for set or reset then both comparators are at 0V and the SR latch maintains the current state. There is potential for instability if somehow both the S and R inputs of the latch were high however, since it is not possible for the input to the circuit to be in the range of both VSET and VRESET simultaneously the unstable case can never occur and can thus be ignored. Table 5.1: SR Latch Truth Table S 1 0 0 0 1
R 0 0 1 0 1
Q 1 1 0 0 0
Q’ 0 0 1 1 0
keep current state keep current state unstable
Up to this point we have described the comparison and state memory portion of the CeRAM circuit but the actual resistance states are are implemented using a simple voltagecontrolled switch. The Q output from the SR latch controls the switch and the RON and ROF F resistances are arbitrarily assigned to meet the specifications of current sample data. The following excerpt from the spice model shows that the default values for RON and ROF F are 1kΩ and 1MΩ respectively. .MODEL SCERAM VSWITCH (VT =2.5 V RON =1k ROFF =1 MEG ) The threshold voltage VT of the switch is set at +2.5V because it falls at the midpoint of the output from the SR latch which is either +5V for SET or 0V for RESET. The complete SPICE model can be found in appendix A listing A.4. The simulation results in figure 5.31 show the input signal and output response of the CeRAM circuit model for a pulsed input. The sequence in the simulation is a SET pulse followed by a read pulse followed by a RESET pulse and lastly another read pulse. As you can
79
Figure 5.31: Pulse simulation of CeRAM cell (Note: Spice Netlist for CeRAM Cell in Appendix A listing A.5 )
see in the simulation there appears to be some time delay between when the VSET value and VRESET values are reached. This is an artifact of the Spice simulation and is due to the way Spice compilers handle input stimulus. When a pulse signal is input using a piecewise linear source, the signal is interpolated between indicated data points which requires some internal calculations and thus time. There are several factors that can however be adjusted to speed up the simulation time which are the tolerances for determining VSET and VRESET as well as the set and reset reference voltages. A schematic representation of two 4x4 array architectures is shown in figure 5.32 (a), and (b). These figures represent a standard 1T1R configuration (a), and a common source configuration (b) in which the footprint of the compliance/select transistors is reduced by overlapping the source region of parallel transistors between bit rows. Figure 5.33 shows a graphical representation of the input stimulus file used for simulating a 4x4 array of 1T1R memory cells. The top plot is the actual programming pulse sequence which follows the Set
BL1
U1
U2
CERAM
CERAM
U3
BL4
BL3
BL2
BL1
WL4
WL3
WL2
WL1
80
U1
U3
U5
U7
CERAM
CERAM
CERAM
CERAM
U4
CERAM
CERAM
CMOSN
CMOSN
CMOSN
CMOSN
M1
M2
M3
M4
WL1
CMOSN
CMOSN
CMOSN
CMOSN
M1
M3
M5
M7
RL1
Vref1 BL2
U5
U6
U7
U8
WL2 CERAM
CERAM
CERAM
M2
M4
M6
M8
CMOSN
CMOSN
CMOSN
CMOSN
CERAM
CMOSN
CMOSN
CMOSN
CMOSN
M5
M6
M7
M8
U2
U4
U6
U8
CERAM
CERAM
CERAM
CERAM
RL2
BL3
U9
U10
CERAM
CERAM
U11 CERAM
U11
U13
U15
CERAM
CERAM
CERAM
CERAM
CMOSN
CMOSN
CMOSN
CMOSN
M9
M10
M11
M12
RL3
BL4
U9 CERAM
U12
WL2
CMOSN
CMOSN
CMOSN
CMOSN
M9
M11
M13
M15
Vref2
U13
U14
CERAM
CERAM
U15
U16
CERAM
WL4
CERAM
CMOSN
CMOSN
CMOSN
CMOSN
M13
M14
M15
M16
M10
M12
M14
M16
CMOSN
CMOSN
CMOSN
CMOSN
U10
U12
U14
U16
CERAM
CERAM
CERAM
CERAM
RL4
(a) standard 4x4 array in 1T1R configuration
(b) 4x4 array with common source 1T1R configuration
Figure 5.32: Circuit schematic representation of CeRAM memory array in standard and common source 1T1R configurations
→ Read → Reset → Read programming sequence. The bottom plot shows the word line bias input on the gate of the compliance/select transistors. The simulation results for the 1T1R V(bl1) 2.0V 1.6V 1.2V 0.8V 0.4V 0.0V
V(wl1)
V(wl2)
V(wl3)
V(wl4)
3.0V 2.4V 1.8V 1.2V 0.6V 0.0V 0µs
40µs
80µs
120µs
160µs
200µs
240µs
280µs
320µs
360µs
400µs
Figure 5.33: simulation input stimulus for simulation 4x4 array in 1T1R circuit configuration
array are shown separated by word line in figure 5.34. Note the presence of a spike in current at the rising edge of the set pulse output signal. This spike in current is due to the fact that simulation of the CeRAM cell is essentially a switch with two linear resistors as the different
81 states of the device. When the switch transitions from high resistance to low resistance this spike occurs in the simulation results. Observationally there is some overshoot of the drain current when testing single 1T1R circuits in a discrete configuration as it was done in previous sections due to the high resistance of the OFF state and the parasitic capacitance present in such a testing configuration but the simulation results show much larger overshoot than is actually observed in implementing such a circuit configuration. All of the SPICE simulation netlist files can be found in Appendix A to replicate these results. 770µA 630µA 490µA 350µA 210µA 70µA -70µA 770µA 630µA 490µA 350µA 210µA 70µA -70µA 770µA 630µA 490µA 350µA 210µA 70µA -70µA 770µA 630µA 490µA 350µA 210µA 70µA -70µA 0µs
Ix(U1:TE)
Ix(U2:TE)
Ix(U3:TE)
Ix(U4:TE)
Ix(U5:TE)
Ix(U6:TE)
Ix(U7:TE)
Ix(U8:TE)
Ix(U9:TE)
Ix(U10:TE)
Ix(U11:TE)
Ix(U12:TE)
Ix(U13:TE)
Ix(U14:TE)
Ix(U15:TE)
Ix(U16:TE)
40µs
80µs
120µs
160µs
200µs
240µs
280µs
320µs
360µs
400µs
Figure 5.34: Simulation output for 4x4 array in 1T1R circuit configuration (Note: Spice Netlist for CeRAM 1T1R 4x4 array in Appendix A listing A.6)
5.4.2
device modeling
The CeRAM device structure in it’s essence is a simple two terminal MIM device which mathematically can be represented as a transfer function with the solution of that transfer function being a total device current or current density for design considerations. The component parts of the current equation can be seen if figure 5.35. The total current is a combination of the MIM diode current which represents the current in the insulating state and phase cur-
82
Figure 5.35: Schematic representation of the CeRAM I-V device model.
rents which are dependent on the Hubbard U and represent the current at the onset of a SET and during the conductive state up to the point of a RESET. Lets first start the modeling process by looking at some I-V curves of a CeRAM device plotted specifically to fit within some standard MIM diode equations. Figure 5.36 shows experimental I-V data collected for a 25µm2 CeRAM device plotted against the thermionic √ emission dominated current plot, Poole-Frenkel tunneling dominated current plot, and V dependent current for both the LRS and HRS states. Thermionic emission is demonstrated by a characteristic linearity in the semi-log plot of I vs. V 1/2 whereas Poole-Frenkel tunneling is characterized by a linear behavior in the semi-log plot of I/V vs. V 1/2 . both plots are quite similar and need to be studied to find the best model that fits the I-V characteristics observed during testing. as you can see from the plot in 5.36a, the HRS current is quite linear through the curve just up to the point where a set occurs which indicates that thermionic emission is the dominant mechanism controlling the CeRAM device in the off state. However, the LRS current does not appear nearly as linear in the thermionic emission plot indicating a different mechanism controlling the on state of CeRAM. Figure 5.36b shows that the LRS of CeRAM is in fact quite linear in the Poole-Frenkel plot which would typically be a great indicator that the on state current is dominated by Poole-Frenkel tunneling if not for the fact that the √ slope tends toward negative and the plot is more ln(I/V ) ∝ −C V + B dependent than it √ is ln(I/V ) ∝ C V . During analysis of the data, it was fairly quickly observed that the LRS showed a rather strong square root dependence that fit better than the other two models and can be observed by the linearity of the LRS in 5.36c.
83 -2
-1
10
10
LRS HRS -3
-2
10 Conductance (I/V)
Current (A)
10
-4
10
-5
10
-3
10
-4
10
LRS HRS -6
-5
10
10 0.0
0.2
0.4
0.6 1/2
V
(V)
0.8
1.0
1.2
1.4
0.0
0.2
0.4
1/2
0.6 1/2
V
(a) Thermionic emission plot
(V)
0.8
1.0
1.2
1/2
(b) Poole-Frenkel tunneling plot
-3
2.0x10
LRS
-3
1.8x10
HRS
-3
1.6x10
-3
Current (A)
1.4x10
-3
1.2x10
-3
1.0x10
-4
8.0x10
-4
6.0x10
-4
4.0x10
-4
2.0x10
0.0 0.0
0.2
0.4
0.6
0.8 1/2
V
(c)
(V)
1.0
1.2
1.4
1/2
√ V dependent plot
Figure 5.36: (a) Thermionic emission limited diode current dominating the behavior in the high resistance state and (b) Poole-Frenkel limited tunneling current, and (c) a square root dependence dominating the low resistance state.
Let us start with the equation for total current density: JT otal = JM IM + Jφ [Θ(V − VReset )] ,
(5.16)
where JM IM is analogous to a leakage current in any MIM device and Jφ is the electronic phase transition current. This equation utilizes a simple unit step function to incorporate both states
84 of the device. Θ(x − y) =
1, 0,
if x = y if x 6= y
The reason for Θ is we can not consider the current for both VReset and VSet simultaneously but we need to account for both JM IM in the ON state and OFF state. Additionally, since JM IM for VSet (i.e. the OFF state) is small, it can be neglected from the equation all together. Now lets consider the possible cases for the phase change current: JOhmic , if U = 0 Jφ = 0, if U 6= 0.
However, we never actually observe Jφ = 0 since Jφ > aB in terms of screening by the free electrons and can show (Nolting and Brewer [58]) √ that the Thomas-Fermi screening length is λT F = 0.44 Rs . The probability of a bound state as Rs → aB can be described by Ψ∗b Ψb ∝ sin2 λT F Kb .
(5.34)
Where Kb is the state vector of the bound state. If Rs → 1, λT F → aB and the bound state is destroyed. But, if λ >> aB the metal becomes an insulator as the bound state interacts with the other electron in the 3d9,10 orbital via the repulsive interaction energy U . To incorporate this into the conductive state current we use a step function with the knowledge that a critical repulsive energy is achieved when the input voltage is equal to the interaction energy term U . Now, 5.33 becomes
J = C(e−qV /kT − 1) where Vreset ∝ U/e.
p
E + qV Θ(Vreset − V )
(5.35)
At this point we can now combine all of the pieces of the CeRAM device model to generate a quite familiar I-V behavior for a positive applied bias. To do this plot the equation for the ON state current 5.35 with the OFF state current equations for JM IM 5.24 and the simplified diode current at the Fermi-level 4.26 from chapter 4. Figure 5.38 shows the CeRAM device model for both the On state square root dependent current and the Off state current which is a combination of thermionic emission through the M-I contact, electron tunneling through the MIM diode barrier, and the off state diode current at the Fermi-level. It is clear that the simulated results agree with the empirical data and that the model theorization that the set operation occurs just as the barrier is overcome and electron movement
88 −3
7
x 10
6
Current (A)
5
4
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5 0.6 Applied Bias (V)
0.7
0.8
0.9
1
Figure 5.37: Conductive state current of a CeRAM element vs. applied bias.(Note: See Appendix A listings A.3 for MATLAB code.) 5
1
10
JOFF
4
10
JON
0.9
3
10
2
10
0.8
1
10
0
10 2
Current Density (A/cm )
Current Density (A/cm2)
0.7
0.6
0.5
0.4
−1
10
−2
10
−3
10
−4
10
−5
10
−6
10
−7
0.3
10
−8
10
0.2
−9
10
−10
10
0.1
J
−11
10
0
J
−12
10
0
0.5
1
1.5
Applied Bias (V)
(a) Linear plot of the Total CeRAM Device model.
0
0.2
0.4
0.6
0.8 1 Applied Bias (V)
1.2
1.4
OFF ON
1.6
(b) Semilog plot of the Total CeRAM model.
Figure 5.38: CeRAM device model for both the ON state current density and the OFF state current density models shown in both linear and semilog plots for a CeRAM device with barrier thickness s = 90nm barrier height ϕ = 1.5eV , and T = 300K. (Note: See Appendix A listings A.2 and A.3 for MATLAB code.)
through the device becomes ballistic. This occurs when Vapplied = VSET where Vset = U/nc e
89 and the simulated data agrees quite well with experimental data. In the ON state of the device the square root dependence is also shown well in the plotted representation of equation 5.33. 5
10
8000 J J 7000
ON ON
(exp) (model)
JOFF(exp) J
(model)
OFF
4
10
Current Density (A/cm2)
2
Current Density (A/cm )
6000
5000
4000
3000
3
10
2
2000
10
JON(exp) JON(model)
1000
JOFF(exp) J 0
1
0
0.2
0.4
0.6
0.8 Applied Bias (V)
1
1.2
1.4
1.6
10
0
0.2
0.4
(a)
0.6
0.8 Applied Bias (V)
1
1.2
OFF
1.4
(model) 1.6
(b)
Figure 5.39: Modeled and Experimental J-V characteristics for CeRAM plotted on a linear scale (a) and a semilog scale (b).
In order to make a direct comparison of experimental J-V data with the device model characteristics, experimentally collected data was imported into MATLAB and the model parameters were adjusted to fit the data curves. For the ON state current, the only parameter that needed to be modified was the scaling factor C from equation 5.37 which was increased to 7000 where as in previous plots, C was set to 1. This scaling factor comes from the fact that JON ∝ JCompliance where JON in this case is larger than JCompliance due to parasitic capacitance in the testing setup and the device itself which causes more current to flow across the CeRAM device than was actually intended by the compliance level. In the OFF state, The fitting process consisted of scaling the baseline current value J0 from the diode equation near the Fermi level 4.26 as well as adding an ideality factor n to the equation which was previously assumed to be 2 for a non-ideal diode. The new equation for the simplified diode current which dominates the OFF state prior to SET is: Jφ (fermi) = J0 eqV /nkT − 1 .
(5.36)
90 The results of the model fitting are shown in figure 5.39. These results clearly show an excellent fit of the device model proposed in this thesis to that of experimentally collected data confirming validity of the model for CeRAM devices.
Chapter 6
Summary and Outlook
The basic concept of CeRAM has been presented in this thesis to be a non-filamentary resistive RAM in which the switching properties of the transition metal oxide (TMO) compounds that could otherwise be negatively affected by non-stoichiometry and defects in the crystal structure are repaired through doping with natural ligands of carbonyl (CO)x and metal-carbonyl’s Mz (CO)y . Once the TMO structure has been properly compensated the e– −e– interaction or repulsion can then be exploited for the switching and memory functions. The presence of carbonyl ligands in these NiO films as a result of the deposition method was investigated using crystallographic and chemical analysis and has not only been confirmed in the films but that carbon content can be easily tuned by simply changing the molarity of the precursor solution and the total number of spun on layers (See figure 5.11). The fabrication process for NiO based CeRAM devices using a chemical solution deposition method commonly referred to a spin-on deposition, with metallization done by DC sputtering and etching by dry ion bombardment or ion milling has been established. the basic switching characteristics of CeRAM structures and devices has been investigated. A wide operating range from -269 ◦ C to 150 ◦ C and nonvolatile data retention at temperatures up to 300 ◦ C has been demonstrated. Sub-100µA operation has been confirmed for relatively large devices using external compliance circuitry and predictions have been made for switching parameters down to a 32nm technology node. In chapters 3 & 4 the necessary background information to build an understanding of the
92 metal-insulator transitions induced by electron density variations during quantum tunneling of electrons and holes was provided. Starting with a review of Hubbard-Mott theory and the physics of the infinitely narrow Hubbard Hamiltonian and it’s application to quantum transport in CeRAMs. The MIM diode and transport current models that created the fundamental pieces of the CeRAM model are presented and their relevancy in modeling such devices confirmed. It his here that the electron density variations responsible for the MIT and it’s reversal have been discussed and the Mott criteria in which the critical number of electrons necessary to induce 1/3
a IMT is established as aB nc
∼ = 0.26 which is necessary for the disproportionation reaction
(d8 + d8 → d7 + d9 ) to occur. The density of states equation that governs the CeRAM model for systems with interacting electrons has been shown to be ρσ = ρ0 [E − Σσ (E − µ)]. where if Σ ∼ = 0, we have a metal and for Σ ∼ = U we have an insulator. In chapter 4 we are able to use the mechanisms and density parameters established in chapter 3 to derive the current equations that were later utilized in the CeRAM model. In the MIM diode, the I-V characteristics are affected both by thermal effects through the Metal Insulator interfaces and tunneling effects through the barrier. It was shown that up to just before the point where the barrier is overcome by electron injection, the thermal affected current dominates the diode behavior. However, at a critical point, tunneling effect takes over and electron transfer becomes nearly ballistic. The total equation representing the MIM diode is n o 1/2 ′ ¯ )1/2 ¯ −Atun ϕ¯ − (ϕ¯ + eV )e−Atun (ϕ+eV JM IM = Ath T 2 e−ϕ /kT (1 − e−eV /kT ) + J0 ϕe . The phase limited tunneling current which is necessary to represent the resistive state of the CeRAM element near the IMT energy level was shown to be Jφ (fermi) = J0 eqV /kT − 1 . which is, the current density near fermi level.
93 Chapter 5 is where all of the previous concepts come together to describe CeRAM storage device from concept to fabrication, modeling, and simulation. A. electrical testing methodology has been established for both collecting I-V data using voltage sweeps in a more parametric testing mode, as well as for pulse testing in more of a memory testing mode including potential compliance circuitry which is critical to controlling the amount of current that flows through a CeRAM during the SET operation and can affect fatiguing and power consumption in a memory application. The fabrication process for NiO based CeRAM devices using a chemical solution deposition method commonly referred to a spin-on deposition, with metallization done by DC sputtering and etching by dry ion bombardment or ion milling has been established. the basic switching characteristics of CeRAM structures and devices has been investigated. A wide operating range from -269 ◦ C to 150 ◦ C and nonvolatile data retention at temperatures up to 300 ◦ C has been demonstrated. Sub-100µA operation has been confirmed for relatively large devices using external compliance circuitry and predictions have been made for switching parameters down to a 32nm technology node. A spice model that can be used for circuit simulation in which the fundamental behavior of a CeRAM device is that it is a device capable of two distinct resistances was created by combining an RS latch with supporting sense-amps and a voltage controlled switch. by looping the output of the RS latch back to its input it is possible to create as simulated memory effect and the remainder of the CeRAM memory elements can be tested against the different resistance states and for different switching times. A physical model has been presented that combines the generalized forms of thermionic and tunneling limited current presented by Simmons [60, 61] with a phase limited current model that utilizes the Meir-Wingreen formula for hole current in the conductive phase and tunneling current in the resistive phase. The device model was compared to experimental data and after the fitting process, and adjustments to the scaling constants, it was confirmed to be an exceptional fit to the data confirming the validity of the presented model.
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Appendix A
Code for simulations
Listing A.1: MATLAB code for Potential barrier in MIM diode structure 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
% Physical Constants e =1.60 e -19; kB =8.61733 e -5; h =4.1357 e -15; m =9.109 e -31; % ########################################################################## % Input Parameters n =1000; % Step count s =90; % Thickness ( nm ) x =0: s / n : s ; % Position ( nm ) x2 =0; K =1; % Permittivity B =1; V =1; T =300; Phim1 =1; % Metal work function Left ( eV ) Phim2 =1; % Metal work function Right ( eV ) phi1 =1; % Barrier height left phi2 =1; % Barrier height right % ########################################################################## % Barrier equations dPhi = Phim1 - Phim2 ; % Metal work function delta ( eV )
23 24 25 26
phi = phi1 +( dPhi - V ) .*( x ./ s ) ; Vim = -2.88.* s ./( K * x .*( s - x ) ) ; Vtot = phi + Vim ;
% Potential Energy ( eV ) % Image Potential ( eV ) % Total Potential
for K =1:4 , phi = phi1 +( dPhi - V ) .*( x ./ s ) ; Vim = -2.88.* s ./( K * x .*( s - x ) ) ; Vtot = phi + Vim ; end
% Potential Energy ( eV ) % Image Potential ( eV ) % Total Potential
27 28 29 30 31 32
Listing A.2: MATLAB code for Thermionic and tunneling current 1 2
clear all % Physical Constants
102 3 4 5 6 7
e =1.60 e -19; kB =1.38 e -23; h =6.63 e -34; m =9.109 e -31; % ##########################################################################
8 9
% Input Parameters
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
n =1000; % Step count s =90; % Thickness ( nm ) x =0: s / n : s ; % Position ( nm ) x2 =0; K =1; % Permittivity B =1; V =1.5; Vapp =0:(1.5) / n :1.5; T =300; Phim1 =1.5; % Metal work function Left ( eV ) Phim2 =1.5; % Metal work function Right ( eV ) phi1 =1.5; % Barrier height left phi2 =1.5; % Barrier height right % ##########################################################################
25 26 27
% Barrier equations dPhi = Phim1 - Phim2 ;
% Metal work function delta ( eV )
phi = phi1 +( dPhi - V ) .*( x ./ s ) ; Vim = -2.88.* s ./( K * x .*( s - x ) ) ; Vtot = phi + Vim ;
% Potential Energy ( eV ) % Image Potential ( eV ) % Total Potential
28 29 30 31 32 33 34
phip = phi1 -( realsqrt (14.4*(7+ Vapp * K * s ) ) ) /( K * s ) ; % ##########################################################################
35 36 37
Ath =(4* pi * m * e * kB ^2) / h ^3; Atun =(4* pi * B * s *10^ -10/ h ) * realsqrt (2* m ) ;
38 39
J0 = e /(2* pi * h *( B * s *10^ -9) ^2) ;
40 41 42 43 44
fun = @ ( x2 ) phi1 +( dPhi - V ) .*( x2 ./ s ) ; F = integral ( fun ,0 , s ) ; phibar =(1/ s ) * F ; % ##########################################################################
45 46 47
% Current density due to thermionic emission phip = phip * e ; % convert barrier back to SI units
48 49
Jth = Ath * T ^2* exp ( - phip /( kB * T ) ) .*(1 - exp ( -( e * Vapp ) /( kB * T ) ) ) ;
50 51 52 53
% Current density due to tunneling phibar = phibar * e *2.001; % convert to SI units + set average barrier % height so phibar - eV is never negative .
54 55 56
Jtun = J0 *(( phibar -( e * Vapp ) ) .* exp ( - Atun * realsqrt (( phibar -( e * Vapp ) ) ) ) ... - phibar * exp ( - Atun * realsqrt ( phibar ) ) ) ;
57 58 59 60
Jtot = Jth + Jtun ;
103 Listing A.3: MATLAB code for phase current 1 2
clear all % Physical Constants
3 4 5 6 7 8 9
e =1.60 e -19; kB =1.38 e -23; h =6.63 e -34; m =9.109 e -31; % ########################################################################## % Input Parameters
10 11 12 13 14 15 16
n =1000; % Step count Vapp =0:(1.5) / n :1.5; T =300; Vt = kB * T / e ; % Thermal Voltage J_0 =1 e -13; % Baseline Diode current % ##########################################################################
17 18 19 20
% Simplified current density for the phase transition in the OFF state J_Diode = J_0 *( exp ( Vapp /(2* Vt ) ) -1) ;
21 22 23 24
% Current density for the phase transitionin the ON state J_ON = J_Diode + abs ( exp ( - Vapp /(2* Vt ) ) -1) .* realsqrt ( Vapp ) ... .*(1 - heaviside ( Vapp -0.7) ) ;
Listing A.4: CeRAM SPICE model 1 2 3 4 5
. SUBCKT CERAM 5 10 * PINS INPUT OUTPUT VCC 1 0 5.0 V VSET 2 0 2 V VRESET 3 0 1 V
; original value 5.3 V ; original value 2.2 V
6 7 8
XCSET 1 2 5 6 COMPMARG XCRESET 1 3 5 7 COMPMARG
9 10
XLSTATE 1 6 7 8 9 RSLATCH
11 12
SCERAM 5 10 8 0 SCERAM OFF
13 14
. ENDS
15 16 17
. SUBCKT COMPMARG 1 2 5 10 * PINS : VCC , VREF , VIN , STATE
18 19 20
R1 2 6 600 R2 6 0 4.7 K
21 22 23
XCOMP1 2 5 7 COMPARATOR XCOMP2 5 6 8 COMPARATOR
24 25 26
XNAND1 7 8 9 1 NAND XNOT 9 10 1 NOT
27 28
. ENDS
; original value 1 k ; original value 9.5 k
104 29 30 31 32 33 34 35 36 37
. SUBCKT RSLATCH 1 2 3 6 7 * TERMINALS VCC R S Q QNOT XNOT1 2 4 1 NOT XNOT2 3 5 1 NOT XNAND1 4 7 6 1 NAND XNAND2 5 6 7 1 NAND . NODESET V (6) =0 V V (7) =5 V . ENDS
38 39 40 41 42 43 44 45
. SUBCKT NAND 1 2 3 4 * TERMINALS A B OUT VCC RL 3 4 500 CL 3 0 10 PF S1 3 5 1 0 SW S2 5 0 2 0 SW . ENDS
46 47 48 49 50 51 52
. SUBCKT NOT * TERMINALS RL 3 4 CL 3 0 S1 3 0 1 0 . ENDS
1 3 4 A OUT VCC 500 10 PF SW
53 54 55 56 57 58 59 60 61
. SUBCKT COMPARATOR 2 4 6 * TERMINALS INPUT + , INPUT - , OUTPUT * COMPARATOR R1 2 3 1K XOP2 3 4 5 OPAMP1 RLIM 5 6 1000 D1 0 6 DZ1 . ENDS
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
* OP - AMP . SUBCKT OPAMP1 1 2 6 * INPUT IMPEDANCE RIN 1 2 10 MEG * DC GAIN =100 K AND POLE1 =100 HZ * UNITY GAIN = DCGAIN X POLE1 = 10 MHZ EGAIN 3 0 1 2 100 K RP1 3 4 100 K CP1 4 0 0.0159 UF * ZENER LIMITER D1 4 7 DZ0 D2 0 7 DZ0 * OUTPUT BUFFER AND RESISTANCE EBUFFER 5 0 4 0 1 ROUT 5 6 10 * * 15 V ZENER DIODE MODEL . MODEL DZ0 D ( Is =0.05 u Rs =0.1 Bv =15 Ibv =0.05 u ) . ENDS
82 83 84 85 86
* ZENER DIODE MODEL . MODEL DZ1 D ( Is =0.05 u Rs =0.1 Bv =4.685 Ibv =0.05 u ) . MODEL DZ2 D ( Is =0.05 u Rs =0.1 Bv =4.685 Ibv =0.05 u )
105 87 88
. MODEL
SW
VSWITCH ( VON =3 VOFF =2 RON =10 ROFF =100 K )
. MODEL
SCERAM
89 90
VSWITCH ( VT =2.5 V RON =1 k ROFF =1 MEG )
; original RON =1 k
91 92
****************** TRANSISTOR MODELS *******************
93 94
. MODEL MOD1 NMOS ( LEVEL =3 VTO =0.5 LD =0.1 u TOX =80 E -10 NSUB =1 E16 )
Listing A.5: Spice Netlist for CeRAM Cell 1
2 3 4 5 6 7 8 9 10
* C :\ Documents and Settings \ Chris . SYMETRIXCORP \ My Documents \ CeRAM \ Spice \ LTspice \ CeRAM_Cell . asc XU1 VT 0 CERAM V1 VT 0 PWL (0 0 10 u 0 11 u 2 V 20 u 2 V 21 u 0 V + 30 u 0 V 31 u 0.5 V 40 u 0.5 V 41 u 0 V + 50 u 0 V 51 u 1 V 60 u 1 V 61 u 0 V 70 u 0 V + 71 u 0.5 V 80 u 0.5 V 81 u 0 V 90 u 0 V ) . lib CeRAM . lib . tran 100 US . backanno . end
Listing A.6: Spice Netlist for CeRAM 1T1R 4x4 array 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
* C :\ Documents and Settings \ chris \ My Documents \ CeRAM \ Spice \ LTspice \1 T1R \ CeRAM_1T1R_4x4 . asc M1 0 WL1 P001 0 CMOSN l =1.6 u w =16 u m =5 XU1 BL1 P001 CERAM M2 0 WL2 P002 0 CMOSN l =1.6 u w =16 u m =5 XU2 BL1 P002 CERAM M3 0 WL3 P003 0 CMOSN l =1.6 u w =16 u m =5 XU3 BL1 P003 CERAM M4 0 WL4 P004 0 CMOSN l =1.6 u w =16 u m =5 XU4 BL1 P004 CERAM M5 0 WL1 P005 0 CMOSN l =1.6 u w =16 u m =5 XU5 BL2 P005 CERAM M6 0 WL2 P006 0 CMOSN l =1.6 u w =16 u m =5 XU6 BL2 P006 CERAM M7 0 WL3 P007 0 CMOSN l =1.6 u w =16 u m =5 XU7 BL2 P007 CERAM M8 0 WL4 P008 0 CMOSN l =1.6 u w =16 u m =5 XU8 BL2 P008 CERAM M9 0 WL1 P009 0 CMOSN l =1.6 u w =16 u m =5 XU9 BL3 P009 CERAM M10 0 WL2 P010 0 CMOSN l =1.6 u w =16 u m =5 XU10 BL3 P010 CERAM M11 0 WL3 P011 0 CMOSN l =1.6 u w =16 u m =5 XU11 BL3 P011 CERAM M12 0 WL4 P012 0 CMOSN l =1.6 u w =16 u m =5 XU12 BL3 P012 CERAM M13 0 WL1 P013 0 CMOSN l =1.6 u w =16 u m =5 XU13 BL4 P013 CERAM M14 0 WL2 P014 0 CMOSN l =1.6 u w =16 u m =5 XU14 BL4 P014 CERAM M15 0 WL3 P015 0 CMOSN l =1.6 u w =16 u m =5
106 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
XU15 BL4 P015 CERAM M16 0 WL4 P016 0 CMOSN l =1.6 u w =16 u m =5 XU16 BL4 P016 CERAM . model NMOS NMOS . model PMOS PMOS . lib C :\ Program Files \ LTC \ LTspiceIV \ lib \ cmp \ standard . mos * Johns and Martin models for 0.8 micron process jl feb 2008 . MODEL CMOSN NMOS LEVEL =3 , TOX =1.8 E -8 , LD =0.08 U , UO =500 , VMAX =2.0 E5 , PHI =0.6 , + GAMMA =0.5 , NSUB =2.5 E16 , VTO =0.7 , NFS =8.2 E11 , CGSO =2.5 E -10 , CGBO =2.5 E -10 , + CJSW =2.5 E -10 , CGDO =2.5 E -10 , MJ =0.5 , CJ =2.5 E -4 , PB =0.9 , IS =1.0 E -16 , + JS =1.0 E -4 , KF =600 E -27 , AF =0.8 , NLEV =2 , RS =600 , RD =600 , + ETA =0.05 , KAPPA =0.007 , THETA =0.06 , XJ =2.7 E -7 , DELTA =0.7 . MODEL CMOSP PMOS LEVEL =3 , TOX =1.8 E -8 , LD =0.08 U , UO =165 , VMAX =2.7 E5 , PHI =0.80 , + GAMMA =0.75 , NSUB =5.5 E16 , VTO = -0.7 , NFS =7.6 E11 , CGSO =2.5 E -10 , CGBO =2.75 E -10 , + CJSW =3.4 E -10 , CGDO =2.5 E -10 , MJ =0.5 , CJ =3.7 E -4 , PB =0.8 , IS =1.0 E -16 , + JS =1.0 E -4 , KF =400 E -27 , AF =1.0 , NLEV =2 , RS =1200 , RD =1200 , ETA =0.12 , KAPPA =1.5 , + THETA =0.135 , XJ =2.3 E -7 , DELTA =0.3 . include PWL2 . txt . lib CeRAM . lib . tran 0 400 u 0 1 u startup uic . backanno . end
Appendix B Derivations
B.1
MIM Diode current simplification n o Jtun = J0 ϕ¯ exp(−Atun ϕ¯1/2 ) − (ϕ¯ + eV ) exp(−Atun (ϕ¯ + eV )1/2 )
Assume as Simmons [60] did for intermediate voltages, ϕ¯ ∼ = ϕ0 −
eV 2
then Jtun
Jtun
(
" # eV eV 1/2 = J0 ϕ0 − exp −Atun ϕ0 − 2 2 " #) eV 1/2 eV exp −Atun ϕ0 + − ϕ0 + 2 2 " ( # eV 1/2 eV 1/2 exp −Atun ϕ0 1− = J 0 ϕ0 1− 2ϕ0 2ϕ0 " #) eV eV 1/2 1/2 . − 1+ exp −Atun ϕ0 1+ 2ϕ0 2ϕ0
(B.1)
Assume eV /2 >> 1. ( Jtun
" " # #) eV eV 1/2 eV 1/2 eV 1/2 1/2 = J 0 ϕ0 − exp Atun ϕ0 exp −Atun ϕ0 − 2ϕ0 2ϕ0 2ϕ0 2ϕ0 ( " " 1/2 # 1/2 #) eV eV eV 1/2 1/2 exp Atun ϕ0 = −J0 + exp −Atun ϕ0 2 2ϕ0 2ϕ0 " ( " 1/2 #) 1/2 # eV eV eV + exp −Atun (B.2) exp Atun = −J0 2 2 2
which readily reduces to: Jtun
" 1/2 # eV eV exp Atun = −J0 2 2
(B.3)
108
B.2
Tunneling Current 2q J= h
Z
Γ1 Γ2 Γ1 + Γ2
(f (E) − f (E − eV ))ρσ dE.
(B.4)
If we assume that the coupling constants Γ0 = Γ1 = Γ2 which is true for a system with similar electrodes, then: Γ1 Γ2 Γ2 Γ0 = 0 = Γ1 + Γ2 2Γ0 2
(B.5)
and the equation for tunneling current reduces to: Z 2q Γ0 J= (fL (E) − fR (E − eV ))ρσ dE. h 2 J
= = = = = =
q h
(B.6)
(∆f ) X δ(E − ε(k) − Σ)dE N k Z X qΓ0 δ(E − ε(k) − Σ)dE ∆f hN k Z X qΓ0 δ(E − ε(k) − µ − Σ)dE (fL (E) − fR (E − eV )) hN k qΓ0 X J0 [fL (E − ε(k) − µ − Σ) − fR (E − ε(k) − µ − Σ − qV )] hN k X 1 1 J0 − exp (E − ε(k) − µ − Σ) + 1 exp (E − ε(k) − µ − Σ − qV ) + 1 k h i X J0 e−β(E−ε(k)−µ−Σ) − e−β(E−ε(k)−µ−Σ−qV ) Z
Γ0
k
=
X k
B.3
J0 e−(E−E(k))/kT 1 − eqV /kT
(B.7)
LRS Current equatinon derivation ρ0 (E) =
1 X δ(E − (E(k) − µ)) N
(B.8)
k
lets set µ = 0 since we are at the Fermi-level. ρ0 (E) =
1 X ~2 k 2 ✟0 ✟✯ V (x) δ(E − E(k)) with E(k) = +✟ N 2m K
now we change to integration with the knowledge that
P
k
→
R
•dk 3
(B.9)
109
ρ0 (E) = = = =
1 X δ(E − E(k)) N K Z ~2 k 2 V 1 δ E− dk 3 N (2π)3 2m Z Z Z ~2 k 2 V 1 δ E− (k cos θ)(k sin φ)dk N (2π)3 2m Z ∞ 1 ~2 k 2 V 2 dk. K δ E− N (2π)3 2m 0
(B.10)
Now, the trick is to go from 1 (δ(x − α) + δ(x + α)) 2|α|
δ(x2 − α2 ) to
2 ~2 k 2 ~ 2mE 2 δ E− −k =δ 2m 2m ~2 if we use δ(αx) = then
(B.11)
1 δ(x) |α|
~2 k 2 2mE 2m 2 δ E− −k = 2δ 2m ~ ~2
now,
2m δ(x2 − k 2 ) = ~2 so, ρ0 (E) =
1 N
=
1 N
ρ0 (E) =
1 N
∞
2m ~2
(B.12)
1 {δ(x − k) + δ(x + k)} 2|k|
(B.13)
~2 k 2 k δ E− dk 2m 0 ! !) r Z ∞ ( r k 2m 2mE 2mE V δ −k +δ +k dk (2π)3 ~2 2 ~2 ~2 0 ! r Z 2m 1 ∞ 2mE V kδ − k dk (B.14) (2π)3 ~2 2 0 ~2
V (2π)3
Z
2
using δ(x) = δ(−x) 1 ρ0 (E) = N
V (2π)3
2m ~2
1 2
Z
∞ 0
kδ k −
r
2mE ~2
!
dk
(B.15)
and finally 1 ρ0 (E) = 2N √ which is ρ0 (E) = C E as expected.
V (2π)3
2m ~2
r
2mE ~2
(B.16)
110 now for the current equation up to the phase transition in the on state. σp = q 2 Dp (ρ0 )(E)
J φp
= = = = =
Z 2q ((1 − fL (E)) − (1 − fR (E − qV ))) ρ0 (E)dE h Z 2q (fL (E) − fR (E − qV )) ρ0 (E)dE − h 2q − (fL (E) − fR (E − qV )) ρ0 (E)∆E h p −C (fL (E) − fR (E − qV )) Ev − E hp i −Ce−β(E−EF ) 1 − eβqV Ev − E(k) + qV
(B.17)
(B.18)
