Continuous-Time ∆Σ Modulators for RF Applications April 14 2005 Joe Jensen Todd Kaplan HRL Laboratories, LLC

© 2005 HRL Laboratories, LLC. All Rights Reserved

1

ADCs in Digital Receivers: Towards the “Software Radio” Conventional Receiver 0.06 GHz

10 GHz 1 GHz

LP Filter RF

BP Filter

ADC

Digital Video Filter

BP Filter

LP Filter

LO2

LO1

DIGITAL DATA

I/Q Ref

I/Q

Trend - Eliminate Downconversion Advantages: – Digital robustness

ADC

– frequency agility

Phase Split

– Lower I/Q Images

Digital IF Receiver

– Better Channel Match

10 GHz RF

BP Filter

ADC

I/Q

Digital I/Q and Video Filter

DIGITAL DATA

– Flexibility with communication

standards – More Deg of Freedom

LO

Digital RF Receiver

Challenges: – ADC needs enormous dynamic

10 GHz RF

Tuneable BP Filter

ADC

© 2005 HRL Laboratories, LLC. All Rights Reserved

Digital

I/Q Dec. Filter I/Q and Video Filter

DIGITAL DATA I/Q

range – Enormous data reduction

needed in DSP Joe Jensen (310) 317-5250 [email protected]

2 slide #2

Issues in Moving ADC forward in Signal Path in Digital Receivers •

•

•

High ADC sample rates required – High input bandwidth and fast settling needed for sub-sampling approaches – Direct sampling requires higher sample rate than the IF or RF being sampled High ADC dynamic range required – Interfering signals in digital receiver are blocked after the ADC – Additional ADC dynamic range is need to replace blocking filters and AGC functions ADC limitations – Increasing the sample rate of ADCs decreases the ADC dynamic range – Digital receiver requirements stress ADC fundamental limits

Ultra-Fast IC technology will have a major impact on Digital Receiver Technology © 2005 HRL Laboratories, LLC. All Rights Reserved

Joe Jensen (310) 317-5250 [email protected]

3 slide #3

Fundamental Principles Oversampling

Linearity: • Linearity of multibit quantizer determined by accuracy of voltage thresholds (process uniformity) • 1 - Bit quantizer ( = Comparator ) – Inherently linear • 1-Bit quantizer increases quantization noise

1 BIT QUANTIZER

MULTIBIT QUANTIZER Maximum Error

Maximum Error

Noise Spectral Density

Resolution: Oversampling ( = Averaging ) • Improves Resolution @ 3 dB / Octave • Requires High Speed Technology

Signal Band

Very High Oversampling Required for Practical Applications •

10 bit, 50 MHz Requires Comparator Clocked @ 12.5 THz !!

Practical Realization : Add loop filter to shape noise and improve performance.

Frequency

f s /2

Joe Jensen (310) 317-5250 [email protected] slide #4

© 2005 HRL Laboratories, LLC. All Rights Reserved

4

Bandpass ∆Σ Noise Shaping for Digital Receiver Applications Conventional Oversampling ADC x(t)

Multi Bit Quant

Digital LP Filter

y(n)

Delta-Sigma Oversampling ADC x(t) +

Integrator

-

fs

One Bit Quant

Digital LP Filter

y(n)

Bandpass Delta-Sigma ADC x(t) + -

Band Pass Filter

Noise Spectral Density

Noise Spectral Density

Signal Band

Signal Band

Frequency

f s/2

y(n)

One Bit D/A

One Bit D/A

Signal Band

Digital BP Filter

fs

fs

Noise Spectral Density

One Bit Quant

Frequency

f s/2

The Noise Suppression Region Can Be “Tuned” Away From DC By Replacing The Lowpass Filter With A Bandpass Filter

Frequency

f s/2

Joe Jensen (310) 317-5250 [email protected] slide #5

© 2005 HRL Laboratories, LLC. All Rights Reserved

5

Principle of bandpass ∆Σ modulation Resonators A/D converter

DSP

Signal 50

-60

-80

0

Noise power per Hz, dB

DAC

Noise power per Hz, dB

-100

-120

-140

-160

-100

-150

-180

-200 0

∆Σ modulator

-50

200

400

600

800 1000 1200 Frequency (MHz)

1400

1600

1800

2000

-200

0

200

400

600

800 1000 1200 Frequency (MHz)

1400 1600

1800 2000

Digitized output

• A/D converter is put inside a feedback loop • Quantizer error is reduced by the gain of the feedback loop Advantages: Unmatched resolution for high-IF digitization Disadvantages: The DAC and input resonator still require full dynamic range of final desired output © 2005 HRL Laboratories, LLC. All Rights Reserved

6

Continuous Time ∆Σ vs. Discrete Time ∆Σ

•

• •

Clock rate – SC DT ∆ΣM maximum clock rate is limited by op amp bandwidth – maximum clock rate ~ fT/100 – CT ∆ΣM relax the restriction on op amp bandwidth – maximum clock rate ~ fT/20 Switching Transients – SC DT ∆ΣM have larger switching transients than CT ∆ΣM Aliasing – SC DT ∆ΣM require separate filter at their inputs to attenuate aliases sufficiently – CT ∆ΣM have free anti-aliasing – antialiasing is an inherent property of the mathematics of CT ∆ΣM

© 2005 HRL Laboratories, LLC. All Rights Reserved

7

Design Approach for Continuous Time Modulators Available Devices in High Speed Bipolar Technology • NPN transistors • Resistors: Thin Film 50Ω /sq, Base Epi 800 Ω/sq • Capacitors: Metal-Insulator-Metal Consequences • Low OpAmp Voltage Gain (typ < 100) • No Simple Positive Current Sources or Active Loads • No Switched Capacitors Design Approach • Continuous Time Integrators • Transimpedance Amplifiers • Fully Differential Circuitry to Minimize Noise Coupling • Current-Mode Logic Minimizes Switching Noise

© 2005 HRL Laboratories, LLC. All Rights Reserved

8

InP HBT ∆Σ Modulator Implementation 1st Order Low Pass ∆Σ Modulator bias currents integrator

Σ Ij in

latched comparator

C

iout

-

inx gmioutx

+

in inx

A

C

out

C

Q D

IDAC

DFF

1-bit DAC

Basic Approach: High impedance current drive in a feedback integrator • Tolerant of low amplifier gain • Low voltage swing at input to integrating capacitors minimizes integrator leakage • Allows current-summing for dac summing node • Requires positive bias current source Input transconductance cell outside feedback loop-determines overall circuit linearity

clock © 2005 HRL Laboratories, LLC. All Rights Reserved

9

Transconductance Cell Saturation Characteristic Converts differential input voltage to a differential current signal Over all ADC linearity and distortion determined by the performance of this circuit 0

OUT +

Q3

Q4 Q5

-20

9525-01-007

V REF

Q6

3rd Harmonic ( dBc )

OUT -

-40 -60 -80 -100 -120 -140

0.2

0

0.4

0.6

0.8

Peak Input ( Volts ) Q1

0

Q8

-20

R IN +

Q1

-40

Q2

-60

R

dB

-80

IN I2

I1

I1

I2

-100 -120 -140 -160

TRANSCONDUCTANCE CELL -5V

© 2005 HRL Laboratories, LLC. All Rights Reserved

-180

0

50

100

150

200

250

300

350

400

450

500

Frequency ( MHz )

10

Integrator Design

INTEGRATOR

9525-01--010

Vcc1

Vcc2 R3

R1

R2

R4 C2

C1

+7 V O5

O6

I IN O3

O4 O1

I3

I2

O2

I1

© 2005 HRL Laboratories, LLC. All Rights Reserved

I2

• Differential amplifier with gain, A and feedback capacitors, C • Low frequency gain determines the noise floor of ∆Σ modulator near DC • Low frequency gain limited by ARC, where R is the effective resistance as seen at the current summing node

I3

11

Finite Tranimpedance Gain Limits Noise Floor

9 4 0 0 -0 9 - 0 1 1

N O IS E P O W E R S P E C T R A 0 –2 0 –4 0

AR

–6 0 –8 0 – 10 0 – 12 0

Pole Frequency=1/2πARC

– 14 0 – 16 0 – 18 0

0

© 2005 HRL Laboratories, LLC. All Rights Reserved

0 .1

0 .2 F /F

0 .3

0 .4

0 .5

S

12

Positive Current Source Positive current source needs to supply the current for the Gm cell and DAC The effective resistance of the positive current source determines the overall transimpedance gain (ARC) 9525-01--010

Vcc bias currents R1

integrator

C

Σ Ij in

in inx

-

iout

A

inx gmioutx

R1

RC=R1-2VT /Icomp Q2

Q1

+

RC

C

RC

I comp

Ibias

IDAC 1-bit DAC

© 2005 HRL Laboratories, LLC. All Rights Reserved

Ibias

Reff=VA/2Ibias G.A. De Veirman, et.al. JSSC Vol 27, No. 3, March 1992, pp 324-331 13

Comparator and DAC Cells

9525-01-008

9525-01-009

Vout+ Vout-

TO CURRENT SUMMING NODES

V in-

DAC INPUT

V in+

DAC INPUT

Non-return to zero DAC

Vbias -5 V

IDAC

CLOCK -5 V Vcs Vcs

-5 V -5 V

© 2005 HRL Laboratories, LLC. All Rights Reserved

LATCHED COMPARATOR

ONE BIT DAC

14

Asymmetric Rise and Fall Times

Asymmetric Rise and Fall Times Produce a Signal Dependent Distortion

9525-01-004

CLOCK (a) avg = 0

1 0 -1

1 (b) avg = 0 0 -1 1 (c) avg = .25 0 -1 1 (d) avg = .12 0 -1

© 2005 HRL Laboratories, LLC. All Rights Reserved

•

1,-1,1,-1

• 1,-1,1,-1

1,-1,1,-1

•

1,1,-1,-1

•

Ideal DAC waveform: average value of alternating sequence is zero Equal nonzero rise and fall times: average value of an alternating sequence is zero Asymmetric rise and fall times: alternating single pulses dc value not equal to zero Asymmetric rise and fall: alternating pairs of pules has dc value different from alternating single pules 15

Symmetric Rise and Fall Times

9525-01-005 9525-01-006

CLOCK

1

1 0 -1

1

-1

1

-1 0

1

1

+1 1

1

-1

1

-1

1

0

-1

-1

1

sig

+1 1

-1

1

1

-1

1

-1

1

0

-1

1

1 -1

-1

1

1 0

sig

+2

+1 1

+3 1

-1

-1

1

1

1

1

-1

-1

1

-1

sig - sig

0 -1

• Symmetric finite rise and fall times do not effect the integrated area of the pulse train

© 2005 HRL Laboratories, LLC. All Rights Reserved

• Balanced differential signals are inherently symmetric even if the individual components are asymmetric

16

InP HBT 2nd Order ∆Σ Modulator Die Photo

Block Diagram bias currents

bias currents integrator

integrator

C

Σ Ιj in inx

A

gm ioutx

+

latched comparator

C

Σ Ιj in inx

-

iout

DARPA

-

iout

C

A

gm ioutx

C

C

Q

I DAC

I DAC

out

+

D

DFF

1-bit DAC

1-bit DAC

clock

3.2 GHz Sample Rate9525-01-013

2nd Order ∆Σ Modulator 2.0 mm x 1.5 mm Die Size 250 HBTs

9525-01-014

SFDR= 70 dB

Joe Jensen (310) 317-5250 [email protected]

∆Σ Output Spectrum (0 to 1.5 GHz) © 2005 HRL Laboratories, LLC. All Rights Reserved

Signal Band for 100 MSPS ADC

slide #17

17

Conversion of Low Pass ∆Σ Modulator to Bandpass ∆Σ Modulator Low Pass gma0

Bandpass

Comparator

gmx1

x(t)

x(t) C1

gma0

C1

C2

CLK D/A

Comparator

gmx1

C2

Z-1

CLK

gmf1

D/A

D/A

D/A

y(k)

y(k)

Noise Spectral Density

∆f

Noise Spectral Density

fcarrier1

Z-1

∆f

∆f

∆f

fcarrier1

ω 2=

fcarrier2

gmx1gmf1 C1C2

fcarrier3 Frequency

© 2005 HRL Laboratories, LLC. All Rights Reserved

fs/2

Frequency

fs/2 Joe Jensen (310) 317-5250 [email protected]

18 slide #18

Resonator Sensitivity to Interconnect Delay - Q-Tuning Circuit Lead-lag network required for 180o phase. gm0

Ci Ri

gm1

Ci Ri

Frequency and Q can both be tuned by varying a gm gm0

Ci

gm1

gmi

Ci

gm2 gm2

Resonator response is sensitive to Ri. Need tunability gm2

Ci Ri

Redraw resonator gm2

Ci

gm1

gm1

Equivalent circuits if: gmi = gm1gm2Ri

© 2005 HRL Laboratories, LLC. All Rights Reserved

gmi

19

4th Order Bandpass ∆Σ Modulator Continuous Time Architecture Feedback ∆Σ Modulator -g5

-g2 Q C2

C1 x(t)

-

g0

Q

-

g1

g6

-

g3

g7

bias currents

C4

C3

-

g4

g8

+

bias currents

bias currents

Q tune

g0

y(k)

bias currents

integrator

integrator

integrator

C

C

C

C

in inx

A

g1

Σ Ιj

iout

in

-

inx

A +

ioutx

+

ioutx

Z-1

integrator

-

Σ Ιj

iout

inx

CLK

Qfb

g9

Q tune

in

Comparato r

-

Σ Ιj

iout

g3

inx

A

g4

iout

Σ Ιj

-

inx

A

C

C

in

in

+

ioutx

+

ioutx

C

C

in

Qfb reduces signal delay • Improves stability • Improves wideband SNR • Improves gain flatness

g2

1-bit DAC

+

+

Out +

QFB + Clk

Out x

Clk

iout

inx

g5

ioutx

I DAC

Latch

+

+

in

iout

2g 6

Latch

+

inx

Clk

in

Latch

inx

ioutx

2g 7

I DAC

1-bit DAC

2g 8

I DAC

1-bit DAC

2g 9

I DAC 1-bit DAC

Q-tuning eliminates need for positive current source • Q feedback cancels finite impedance of pull up resistors © 2005 HRL Laboratories, LLC. All Rights Reserved

20

Feedforward Architecture Advantages of Feedforward Architecture • Only one feedback DAC is required to be fed to the noiseshaping loop • Less harmonic distortion ??? Better IMD • Less sensitive to circuit imperfection • Can handle more input signal power – Better saturation recovery response Feedforward ∆Σ Modulator -g2

-g5 Q

x(t)

-

g0

g1

gA

g6 gE

Q

C2

C1

C4

C3

-

g3

gB

-

g4

gC

gD

Comparator +

Qfb

CLK

Z-1 y(k)

© 2005 HRL Laboratories, LLC. All Rights Reserved

21

InP HBT IF Bandpass ∆Σ Modulator 4th Order, 1-Bit ∆Σ, 4 GSPS, 2nd IF Sampling * Published JSSC Oct. 2004 Conventional Analog I/Q Receiver

Tuning Range 140-210 MHz 90

10 GHz

1 GHz

0.06 GHz

gmx21

gmx 1

gma0

1 MHz BW

80

4 to 1 PDI/ 1Meg FFT

Comparator

0

gmx2

-10

SNR @1MHz= 78 dB

70

-20

SNR @60MHz= 51dB

60

BP

BP

Clut Rej

Filter

Filter

Filter

LO1

LO2

Filter

ADC

C1

C3

C2

C4

I/Q LP

Low Speed

Filter

ADC gmf1

LO3

CLK

gmf2

Z -1

I/Q

D/A

Ref

LP Filter

High Speed ADC

D/A

D/A

D/A

y(k)

LP

High Speed ADC

Enhanced Performance Lower Power Lower Size & Weight Lower Cost

-40 -50 -60

50

60 MHz BW

40 30

-70

20

-80 -90

10

-100 -110 10

I/Q

Filter

-30

SNR (dB)

RF

Low Speed

Spectral Density (dB)

x(t) LP

0 50

90

130 170 210 250 290 330 370 400

120

IF Frequency (MHz)

4th order, tunable IF, bandpass ∆Σ Modulator

140

160

180

200

IF Frequency (MHz)

SFDR Performance ( 68 dB/1 MHz BW from 250-750 MHz IF IMD