FILE NO.
COLOUR TELEVISION TRAINING MANUAL
Chassis Series FC3G2
CIRCUIT DESCRIPTION BLOCK DIAGRAM OF ICs TROUBLE SHOOTING
REFERENCE XXXXXX
NO.
1 Training Manual FC3G2 Chassis
Table of Contents Part 1 Chassis Description ..................................................................................... 3 1. Chassis Summary ....................................................................................................... 3 2. CPU (System Control) ................................................................................................. 4 2-1 A-D Key Identification Circuit. ..................................................................................... 8 2-2 Memory Option ......................................................................................................... 10 2-3 Power / stand-by circuit............................................................................................. 13 2-4 Protection circuit........................................................................................................ 13 2-5 AFT............................................................................................................................ 14 2-6 Horizontal/Vertical pulse input................................................................................... 18 2-7 Service mode ............................................................................................................ 19 3. IF /Video/Chroma/Deflection .................................................................................... 22 3-1 IF stage...................................................................................................................... 22 3-2 Video/Chroma stage.................................................................................................. 22 3-3 Deflection stage......................................................................................................... 22 4. Audio Output.............................................................................................................. 23 5. Vertical........................................................................................................................ 24 6. Horizontal .................................................................................................................. 24 7. Power Consumption Saving Circuit. ....................................................................... 25
Part 2 Block Diagram of ICs ................................................................................. 28 1. LA76818A (IF/VIDEO/CHROMA/DEFLECTION)....................................................... 28 2. LA78040N (VERTICAL OUTPUT).............................................................................. 30 3. AN17820B (AUDIO OUTPUT).................................................................................... 30 4. LA7642NM (SECAM DECODER)............................................................................... 31 5. 24LC16B/P (IC MEMORY) ......................................................................................... 31
Part 3 Trouble shooting Chart ............................................................................. 32 Trouble Shooting Chart Startpoint symptom: Dead .............................................. 33 Trouble Shooting Chart Starpoint symptom: No picture-no sound ....................... 36 Trouble Shooting Chart Starpoint symptom: No picture-sound OK ...................... 38 Trouble Shooting Chart Starpoint symptom: No sound-picture OK ...................... 39 Trouble Shooting Chart Starpoint symptom: No color & color NG........................ 40 Trouble Shooting Chart Startpoint symptom: No vertical deflection ..................... 41 Trouble Shooting Chart Startpoint symptom: No on-screen display..................... 42 Short – Open Test Report ............................................................................................... 43
2 Training Manual FC3G2 Chassis
Part 1 Chassis Description 1. Chassis Summary The following figure shows a basic block diagram of the FC3G2 chassis. This chassis is constructed by the folowing ICs : AN17820B, IC001, for the audio output circuit LA76818A, IC201, for the IF, video, chroma de-modulation and deflection circuit LA7642NM-TLM-E, IC281, for the SECAM decoder circuit. NJW1142M, IC3701, for audio processor LA78041, IC501, for the vertical deflection output circuit LC863448W-52F1-TLM, IC801, for the CPU (system control unit) of FC3G2 AT24C16A-10PI-2.7, IC802, for the control memory IC. MM1188XS & TC4053BF-TP1, IC1401 & IC 1501, for video selector.
A1901A RC RECEIVER
RC-IN
3
28
4 ON-TIMER POWER
D1910 LED
KEY-IN
SW1901 ~ SW1906
31
19 20 21
12 1/2
S-VIDEO IN (FROM S-TERMINAL)
REAR AV1 INPUT TERMINAL
S-TERMINAL
G
11/12
TV/AV OUT R-IN
26
21 (L-TV-L)1/30
AV1 L-IN
L
G-IN
AV2 L-IN AV2 R-IN
28
9 1
B-OUT
HORIZ.OUT
27
42
Q431 H-DRIVE
7
HV
B
L902 DY
IC501 VERT./DEF.
5
T431 H-DRIVE TRANS.
Q432 H-OUT FOCUS T471 FBT
PCC CIRCUIT Q461-Q462
TV 1 AUDIO OUT
TV-AUDIO
SCREEN
44 INT.VIDEO IN (C-IN)
HV
VIDEO MONITOR OUT 13/14
IC1501 VIDEO SELECTOR AV IN
2
15
MONITOR OUT
4
TV/AV OUT Y-OUT
4 8
FBT
140V
AV-IN 13
AV OUT
14 Y-IN 12
AV1/AV2 (FROM CPU PIN-25) C-IN Y-IN
POWER SUPPLY CIRCUIT
TV IN 1 TV IN 5
AV2/S-INPUT
1
46 VIDEO-IN Y-IN
AV,Y IN 3
3
3
G
VERT.OUT
23
R-OUT
C-IN 6
Y-IN 7
8
G-OUT
20
VIDEO OUT (TV)
3
IC1401 VIDEO SELECTOR
+
2
R-OUT
19
16
29
V
R
CRT
R
HEATER
15
AUDIO CONTROL/ SURROUND
L
B
9
2
AV1 R-IN
R
IF IN
5/6
1
14
AV1/AV2 OUT
10
5
V
AV2 VIDEO IN
FRONT AV2 INPUT TERMINAL
R
IC201 IF/VIDEO/ CHROMA
SDA/SCL
21
AUDIO MONITOR OUT(RIGHT)
IC701 TRIPLE VIDEO OUTPUT AMP.
SDA/SCL
L
IC3701
CRT UNIT
OSD B-OUT
B-IN
AUDIO MONITOR OUT(LEFT)
L R
26
VIDEO MONITOR OUT
V
OSD G-OUT
SDA/SCL (FROM CPU)
REAR MONITOR OUT TERMINAL
X161
SAW FILTER
A101 TUNER
OSD R-OUT
R
6
2
IC802 EEPROM
L-OUT
L-OUT
24
8
AV1 VIDEO IN
SP901
R-OUT 12
5 6
11
IC001 AUDIO AMP. SP902
SCL
32
IC801 CPU
FRONT CONTROL KEYS
SDA
11
9
36V
TUNER
24V
HORIZ. DEF.
11V
MAIN SOUND AMP.
AV-OUT Y-OUT
VERT. DEF.
9V
10
S-INPUT
9V
IC201, AUDIO CTL.
5V
CPU, EEPROM
TV/AV (FROM CPU PIN-24)
Figure of FC3G2 block diagram
3 Training Manual FC3G2 Chassis
2. CPU (System Control) The following firgure shows a block diagram of the CPU peripheral circuit. CPU that use for FC3G2 is AC5G2 CPU. TERMINAL ASSIGNMENT (AC5G2 CPU) LC863448W-52F1-TLM (ROM:48Kbytes) * P03
BUS SDAÅÆ V/C IC BUS SCL Å
1
IIC SDA ÅÆ EEPROM IIC SCL Å
3
P12/SDA1
4
P13/SCLK1
P00
Vss(GND) Å
5
Vss
P17
CPU OSC input Æ (X’tal 32.768KHz) CPU OSC output Æ
6
XT1
P16/PWM3
7
XT2
P15/PWM2
VDD(+5V) Æ
8
VDD
P14/PWM1
SECAM Killer Input Æ
9
P04/AN4
P73/INT3
29 Æ Sound Mute output (High:Mute ON) 28 Å remote control signal input
10 P05/AN5
P72/INT2
27 Å Power failure input
AFT signal input Æ S-Video input (Low: S-in) Æ panel key input Æ RESET input Æ
P10/SDA0
36 Å Status input(factory) (Low:factory mode) P02 35 Æ ACK output(factory) (Low:factory mode) * P01 34 Æ BASS output & Woofer Output
2 P11/SCLK0
11 P06/AN6 *
P71/INT1
12 P07/AN7
P70/INT0
13 RESET
P32
Filter for PLL Å 14 FILT (Connect to ground through CR) CV input(no use=open) Æ 15 CVIN
P31 BLNK
33 Æ VIF-M output (High:NTSC,Low:other) 32 Æ ON timer LED on/off output (Low:Timer on) 31 Æ Power on/off output (High:on) 30 Æ Volume PWM output
26 Æ TV/AV1/AV2/AV3 option output 25 Æ 50/60 output (Low:60Hz) (PAL:50Hz, NTSC:60Hz) 24 Æ TV/AV1/AV2/AV3 option output 23 Æ L/R or L/L 22 Æ OSD Blanking signal output
Bilingual output Å (Low:S-1,High:S-2) V-sync signal input Æ
16 P30
B
21 Æ OSD Blue signal output
17 VS
G
20 Æ OSD Green signal output
H-sync signal input Æ
18 HS
R
19 Æ OSD Red signal output
NOTE : * N-ch.open drain output (Vout max.+5V)
4 Training Manual FC3G2 Chassis
The following table shows pin description of CPU. Port Description Table PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Port Name SDA0 SCL0 SDA1 SCL1 VSS XT1 XT2 VDD AN4 AN5 AN6 AN7 RES FILT CVIN P30 VS HS R G B BLNK P31 P32 P70 P71 P72 P73 P14 PWM2 P16 P17 P00 P01 P02 P03
Use IIC DATA IIC CLOCK BUS DATA BUS CLOCK GND X’tal input X’tal output +5V SECAM Killer input AFT IN S-Terminal input Panel keys input RESET FILTER for PLL CV input Bilingual output V-sync signal input H-sync signal input OSD Red output OSD Green output OSD Blue output OSD Blanking output L/R or L/L output TV/AV123 output 50/60Hz output TV/AV123 output Power failure input Remotecontrol signal Sound Mute output Volume PWM output Power on/off output On timer LED output VIF-M Bass expander ACK Status input
I/O I/O O I/O O I O I I I I I I O I O I I O O O O O O O O I I O O O O O I/O O I
Output Input Reset Structure p-up R Notes Nch-OD No Hz BUS IC Nch-OD No Hz BUS IC Nch-OD No Hz EEPROM Nch-OD No Hz EEPROM 32.768KHz Nch-OD No High: SECAM No AFT signal Nch-OD No Low: S-In No Panel keys Reset:Low (Composite Video) yes Active Low Active Low C-MOS L Active High C-MOS L Active High C-MOS L Active High C-MOS L Active High C-MOS Hz Low:L/R C-MOS yes Hz Option TV/AV1/AV2/AV3 C-MOS No Hz Low:60Hz C-MOS No Hz Option TV/AV1/AV2/AV3 Nch-OD No Hz Low:fail Nch-OD No Hz Active High C-MOS No Hz High:Mute on C-MOS No Hz C-MOS No Hz High:Power on C-MOS No Hz Low:timer on C-MOS No Hz High:NTSC Nch-OD No Hz High:BASS on C-MOS No Hz Factory:Low Nch-OD No Hz Factory:Low
Note : Hz = High impedance
5 Training Manual FC3G2 Chassis
≪CPU Specification outline≫ This tuning system is equipped with the F/S tuning system for AC5G2 chassis. It has the following specification. (1) Monaural, Simple AV Stereo & AV stereo Function (2) Maximum 256 Positions. Optional 100 or 256 Position (E PROM : 16k bit for 256 Pos) ① The direct tuning function can be work by pressing “[0]~[9] key” and “[-/--] key” ② The sequential tuning function can be work by pressing [POS -] and [POS +] key ③ The alternate tuning function can be work by [Alt] key (3) PRESET function [Automatic Tuning/Semi-Auto Tuning/Manual Tuning] Plug & Play function (4) Channel Swap function & Channel Skip function (5) Bilingual system (6) Option system A. Memory options ① Color system selection : Five kinds ② Sif system selection : Six kinds ③ AV input option : AV only or AV1/AV2 or AV1/AV2/AV3 ④ BASS EXPANDER selection : with or without ⑤ SURROUND selection : with or without B. Special function (Dealer) options ① Tuning Lock : on or off ② Volume Lock : on or off ③ AV start : on or off ④ Music mode : on or off (7) Digital AFT (Auto Fine Tuning) function (8) Front controls ◦ [Volume Up] / [Volume Down] ◦ [Programme Up] / [Programme Down] ◦ [TV/AV] Selector (9) OSD is a multi-color display (the R/G/B output). (10) OFF timer function(30/60/90/120 minutes) (11) ON timer function (10 minutes ~ 24 hours) 6 Training Manual FC3G2 Chassis
(12) Auto shut off timer function (10 minute) (13) FACTORY KEY(R/C DATA code “80h”~ “DFh”) (14) Service mode (Adjustment of bus data : one chip and audio IC etc.) (15) PWR Error Detection Function (16) I2C bus correspondence (One chip : LA76818) (17) EEPROM (8k bit for 100 position, 16k bit for 256 position) (18) GAME (Air Tennis) (19) Six Language OSD ① English ② Thai ③ Arabic ④ Russian ⑤ French ⑥ Bahasa Indonesia (20) White Tone user adjustable
7 Training Manual FC3G2 Chassis
2-1 A-D Key Identification Circuit. The key identification circuit used in this chassis uses a switched resistive ladder network in a A-D conversion circuit to generate and send a voltage to the CPU when a key pressed. The CPU uses this voltage to determine which key was pressed. This resistive circuit eliminates the need for encoder/decoder devices, simplifying design and adding to the reliability of the TV. The table shows the voltage input to CPU pin 12, when a given key pressed. Front Control Key Input 1) Action Front panel SW is decied by the input voltage of A/D port (12pin). 2) Circuit * S-terminal-less model key port 12PIN 5V
K6
K5
K4
K3
K2
K1 R12K R5.6K R3.9K R2.2K R1.8K R1.0K
CPU 12 PIN KEY SW INPUT
R10K
* S-terminal model key port (12PIN) 5V
K6
K5
K4
K3
K2
K1
R27K R12K R5.5K R3.9K R2.2K R1.8K R1.0K R10K
CPU 12 PIN KEY SW INPUT
8 Training Manual FC3G2 Chassis
* Key Table Key
VOL. Range(Vcc ratio)
(V)
ΣR
K6
109/128Vcc ≦ K6 < 127/128Vcc
4.26~ Vcc
1.0K
K5 K4 K3 K2 K1 OFF 2 OFF 1
93/128Vcc ≦ K5 < 109/128Vcc 77/128Vcc ≦ K4 < 93/128Vcc 61/128Vcc ≦ K3 < 77/128Vcc 45/128Vcc ≦ K2 < 61/128Vcc 29/128Vcc ≦ K1 < 45/128Vcc 13/128Vcc ≦ OFF< 29/128Vcc OFF < 13/128Vcc
2.8K 3.63~4.26 5.0K 3.01~3.63 8.9K 2.38~3.01 1.76~2.38 14.5K 1.13~1.76 26.5K 0.51~1.13 53.5K OPEN <0.51
FUNCTION TV/AV MENU VOLUME VOLUME + POSITION POSITION + OFF (S-Available) OFF (S-N/A)
* Mechanism SW is used for K1-7. 3. Action * The Key scan will be performed every 20 msec. It judges whether the key was pressed or not . * When the Key signal is match within two consecutive time at intervals of 20msec , the key is decided. * The Key scan priority is K6 -> K1. * The high priority key has pushed, other keys cannot operate. 4. S-input Option * The “KEY OFF” voltage distinguishes availability of S-Terminal. * The “KEY OFF” voltage range is divided into two kinds. 1. When KEY OFF voltage is less than 0.51V, it is decide as an S-terminal-less model. 2. When KEY OFF voltage is from 0.51 to 1.13V, it is decide as S-terminal model. * Judgment is always (20 ms) performed. (agrement with two consecutive time * This option is decided only in KEY OFF. An option does not change when K1 ~ K6 was inputted. □Bus data of LA76818 VIDEO OFF 1 SW (S term less) Address TV AV 14H DAO 0 1
OFF 2 (S term) TV AV 1 1
9 Training Manual FC3G2 Chassis
2-2 Memory Option This chassis uses the option function to determine several different specifications of the TV set. The CPU determines the specification of TV by setting the data of memory option. Following table shows the option function of the CPU. The SERVICE MODE NO From 83 to 96 is EEPROM MEMORY OPTION. 《SERVICE MODE NO 83》 * ”STEREO” OR “MONO” OPTION Bit OPTION 0 MONO 1 Simple AV Stereo 2,3 AV Stereo ※ AV STEREO : Control by Audio IC (NJW1142) Simple AV : Control By CPU PWM port MONO : Control by Volume ATT register of One chip IC. 《SERVICE MODE NO 84》 * VOLUME TABLE 1, 2 SWITCHING Bit VOL TABLE 1 VOLUME TABLE2 0 VOLUME TABLE1 ※ Refer to “volume.doc”. 《SERVICE MODE NO 85》 * MPP FUNCTION option Bit 1 MPP ON 0 MPP OFF * M.P.P. function memorize VOLUME/BRIGHT/CONTRAST/SHARPNESS/TINT for every channel (1~30 POS). * Refer to 121Multi_PP_Level.DOC 《SERVICE MODE NO 86》 * TUNER option Bit 1 Matsushita Tuner 0 ALPS Tuner
10 Training Manual FC3G2 Chassis
《SERVICE MODE NO 87》 * AV1, AV2, AV3 Option Bit 0 TV→AV→TV 1 TV→AV1→AV2→TV 2-3 TV→AV1→AV2→AV3→TV 《SERVICE MODE NO 91》 《Description》 * A color system option is changed by a setup in Service Mode No. 91 OPT COL. * A color system option is shown below. There are five kinds of color systems. * COLOR SYSTEM OPTIONS Tabel SVS data 0,1 2 3
OPTION
NO SYSTEM VMT SYSTEM CHINA, INDONESIA 4 3 SYSTEM 5,6,7 MULTI SYSTEM
TV
AV
(No Display) PAL only (No Display) PAL + NTSC only AUTO→PAL→NTSC4.43→NTSC
same as the TV MODE. AUTO→PAL→NTSC4.43→NTSC same as the TV MODE.
AUTO→PAL→SECAM→NTSC4.43 AUTO→PAL→SECAM→NTSC4.43→NTSC
same as the TV MODE. same as the TV MODE.
《The option selection method》 * An option is changed by Service Mode NO. 91 OPT COL. * The Option check will be carry out on RESET START. * A judgment is performed only once after RESET START. 《SERVICE MODE NO 92》 《Description》 * A SIF system option is changed by Service Mode. * A SIF system option is shown below. There are six kinds of SIF systems. * The bilingual operation differs from the other SIF system option * SIF SYSTEM OPTIONS SVS OPTION BG (5.5M) D/K (6.5M) I (6.0M) M (4.5M) Data 0,1,7 NO SYSTEM (BG) No display --- --- --- 2 BILINGUAL SYSTEM --- --- ○(S-1) ○(S-2) 3 SYSTEM A ○(S-1) ○(S-3) ○(S-2) ○(S-4) 4 SYSTEM B ○(S-1) --- --- ○(S-2) 5 SYSTEM C ○(S-1) ○(S-2) --- --- 6 SYSTEM D ○(S-1) ○(S-2) ○(S-3) ※Bilingual specification is displayed as S-1 and S-2. The other modes, each SIF system name is displayed. 11 Training Manual FC3G2 Chassis
《The option selection method》 * An option is changed by Service Mode Data No.92 OPT SIF * The voltage is read in a RESET START after operation. * This judgment operation carry out only a RESET START. 《SERVICE MODE NO 93》 * BASS EXPANDER FUNCTION option Bit Display 0 No Display 1 “BASS” 2 “BASS EXPANDER” 3 “WOOFER” * If Bass Exp Option is ‘0’ on MONO and Simple AV mode then there will be No AUDIO Menu on MAIN Menu * This function is available only when using Audio Control IC. * In AV Stereo Mode While BASS EXPANDER ON, AUDIO IC of Bass/Treble DATA is set as : Bass : +10 dB, Treble : +6 dB * In MONO & Simple AV Stereo Mode if BASS EXPANDER ON, Pin 34 will be “High” 《SERVICE MODE NO 94》 * SURROUND option Bit 1 Surround 0 No Surround 《SERVICE MODE NO 95》 * SUB - BASS/TREBLE adjustment of Audio Control IC (NJW1142) Bit 0 BASS TREBLE Gain –3 db 1 BASS TREBLE Gain 0 db 2,3 BASS TREBLE Gain +3 db * This function available only when using Audio Control IC. 《SERVICE MODE NO 96》 * AGC setting Audio Control IC (NJW1142) Bit 0 AGC OFF 1 AGC ON Level= 600 Mv 2 AGC ON Level= 500 mV 3 AGC ON Level= 300 mV * This function available only when using Audio Control IC
12 Training Manual FC3G2 Chassis
2-3 Power On/ Stand-by circuit. Power on / stand-by The power on/stand-by signal is output from pin 31 of the CPU. When the stand-by mode is selected the voltage of pin 31 changes from Hi(5V) to Low(0V) to turn off Q681and Q652. Q652 turning off causes Q653 and Q654 to turn off. +24V supply for vertical and horizontal output circuit, +9V supply for IF/VIDEO/Chroma circuit and +5V for tuner circuit are all cut off, resulting in the TV set going into the stand-by mode. When the TV is switched back into the power on mode, Q681 and Q652 are turned on and the relevant voltage are supplied back to each circuit. Q681 TO HEATER PROTECT & HOLDDOWN CIRCUIT TO VERTICAL DEFL. CIRCUIT (FOR PROTECTION) IC681 TO CPU TO IC201, IC281 AUDIO PROCESSOR, AV SWITCH & CRT UNIT
TO VIDEO PROCESSOR, TUNER & DEFLECTION
Q652 TO HOR & VER, DEFLECTION CIRCUIT
TO AUDIO AMP. IC TO TUNER AND HOR DEFL. CIRCUIT
Fig. of Power On/Stand by Circuit
2-4 Protection circuit This chassis employs two kinds of protection circuit, one controlled by software through the CPU and the other by hardware. . Protection circuit (software) The protection circuit is provided to disable the operation of the TV set in case of a circuit malfunction. When an abnormality occurs during TV reception it causes pin 31 of the CPU to go continually Low (less then 0.8V) for about one second. The CPU detects that circuit malfunction has occurred and cut off the signal output to Q681. . Protection circuit (hardware) When a power failure is detected by diodes D655, D690 and D468, this protection circuit operates causing the power oscillation to stop. If one of above diode is turned on, the voltage of Q661-emitter decreases, and it turns on completely. Photo-coupler D610 is driven by this and generates a current which drives Q625 on. As a result, the operation of the power oscillation circuit is stopped. Under normal circumstances these parts, D610, Q661, D661, R661, VR661, R662 are operating as the error detection and regulation circuit for +130V power supply. 13 Training Manual FC3G2 Chassis
AT3
PROTECT Q690 AH
R691 1/16GJ 47KC
R694 5.6K C691
R692 1/16GJ 20KC
D691 35EM47
AA
C690 EM2.2 CT
D690 1SS355 R695 DJ6.8K
AD Q693
R690 1/16GJ 47KC
R693 1/16GJ 10KC
D692 EU1
R696 1/16GJ 4.7KC
R697 1/16GJ 47KC
C693 16EM47 11V D693 AA R645 X
4 3
X
C656 1000KK 470(CRD:NH)
1 L652 J
2
4
BA178M05T: MC78M05CT: UPC78M05AHF: L78M05CV C657 R646 1000KK470 J (CRD:NH) L653 J
14
5
D653 FE301-1L43: RU4YXLF-L1
X
7
12
X
C658 1000KK470 L654 (CRD:NH) J 1
R653 1FJ5.6
D652 RN1Z
C652 35EM 470T
IC681
5VRC
1
2
R652 33K JP653 1/16GZ0C
R658 X Q653 R659 X X
D659 X
C665 16EM470 R656 1SJ270
X
R654 C654 15K C653 25EM PM1 3300 C655 1000KK680 (CRD:NH) L651 JP631 J J
Q651 AD
TP-130 X
R672 12K R651 1K
R671 C663 22K EM0.22
R660 X
Q681 AE
D671 AA
R681 22K
L-ST H-ON
R682 1/16GJ 560KC B1 130V
3
D651 RU3AM C651 160EM 220XJ
D655 AA
16EM220: 16EM220LBWA
X
2400030
C664
R673 1/16GJ 560KC
D662 MTZJ 6.8A: DZXLB ZA6.8A
9V
D664 MTZJ10B: RD10EB2: DZXLBZA10B
11V AUDIO
R667 1/16GJ 10KC Q663 AH
Q654 2SD1913 (QRA:RRA)
D654 YG901C2-LB
13 2
Q662 AC
R669 2SJ 12
C643 25EM 1000T
R666 1/16GJ 22KC
24V
R657 DJ3.9K R668 2SJ12
C681 10EM470
16
17
R655 DJ10K Q652 2SB1565E
3
15 6
JP652 X
JP633 X X
R664 1SJ27K
R661 DJ100K
VR651 R3D6222NJ: R3D7222NJ
Q661 AH R662 1/16GJ 3.9KC
C639 X R665 R663 DJ12K 150K D661 MTZJ6.2C: RD6.2EB3: DZXLBZA6.2C
2-5 AFT * Basic operation of tuning (Common operation : Direct tuning / Sequential tuning / Alternate tuning) (1) The tuned-in position is memorized to E2PROM as a last position. (2) The transient MUTE is performed at the time of tuning. ( direct / alternate tuning.) (3) A position OSD is displayed for 5 seconds. (4) Digital AFT operation is performed after 240ms. * This tuning system is F/S tuning, thus digital AFT is unnecessary in principle at least. But, AFT is carrying out for the following reasons. (1)If some hundreds of kHz RF shifts by move etc.,the claim will occur that NICAM and TEXT do not operate. (2)The old chassis of F/S tuning system shown below that has the digital AFT function. F/S tuning system model : EB1/EB3/WB2A/WB2B/AB3A/AB3B. (3)The V/S tuning system quality standards are satisfied that RF change can be corrected to ±800kHz. (In case of the China national standard, it is necessary to receive to ±1MHz.) 14 Training Manual FC3G2 Chassis
《Digital AFT》 * Digital AFT is substitute of the “hardware AFT” inside a tuner. In order to set the tuning voltage as the optimal value, center frequency is searched from the starting frequency which deducted 1MHZ from the local frequency memorized by E2PROM. However, this digital AFT is terminated when rise/down processing of tuning voltage becomes 100 times. - LOCAL frequency is controlled by AFT voltage of the following table. direction UP Vol. CENTER Vol. DOWN Vol.
AFT Vol. 3.5v2.0v-3.0v -1.5v
①The starting frequency data is outputed to Tuner. Wait for 240msec. → If AFT voltage is less than [ 1.5V ]. Jump to ④ → Other, To the next. ②Frequency is raised by 500KHz/40msec (Tab.1-A) until AFT voltage becomes more than UP voltage (3.5v). - In case of following, Local frequency is set to an EEPROM data. Jump to ⑤ - Tuning data raised to +1.5MHz on the way, - The digital AFT was performd 100 times or more, ③Frequency is raised by 100KHz/40msec (Tab.1-B) until AFT voltage becomes more than DOWN voltage (1.5v). - If a synchronized signal is lost on the way, it will return to ② - In case of following, Local frequency is set to an EEPROM data. Jump to ⑤ 1. Tuning data raised to +1.5MHz on the way, 2. The digital AFT was performed 100 times or more. ④Frequency is raised by 50KHz/40msec (Tab.1-C) until AFT vol becomes more than CENTER voltage (2.0v). - If a synchronized signal is lost on the way, it will return to ② - In case of following, Local frequency is set to an EEPROM data. Jump to ⑤ 1. Tuning data raised to +1.5MHz on the way, 2. The digital AFT was performd 100 times or more, ⑤Digital AFT complete. Tab. 1
Digital AFT tuning speed A B C high speed up mid speed up low speed down 500KHz/40msec 100KHz/40msec 50KHz/40msec
15 Training Manual FC3G2 Chassis
* Input (1) Detection of the synchronized signal of TV/AV. Read register of the 1 chip IC (LA76818) Judgment Non - sign sign
Status(D1 bit) 1 0
- It is determined by two continuation correspondence (20ms interval). (2) Detection of an AFT signal uses a A-D input port (10pin). - The AFT signal (0V-9V) outputted from an AFT circuit that is changed to 0V-5V by resistance. - This A-D input terminal port which consists of a 6-bit D-A conversion and a comparator. - Tuner always output AFT voltage of the TV signal, even if AV. - An AFT signal is judged as follows: The voltage level is read every 10ms. ←3.5v AFT signal
↓f1 3.5v→ center freq ←2.0v 1.5v→
↑f2
Synchronized signal (Attention) The necessary condition of the sensitivity of an AFT signal is f2-f1 > 50kHz. Input Vol. Level L(0v~1.5v) M(2.0v~3.0v) H(3.5v~5v)
Judgment TU Vol. down TU Vol. center TU Vol. up
《Output》 * IIC bus is used for PLL control. (Matsushita PAL standardization F/S tuner) * PLL control (transmission of data) is not performed in standby mode. (the power voltage is not supplied to a PLL circuit) * PLL control is not performed during bus open mode. * PLL control register is refreshed every 20ms.
16 Training Manual FC3G2 Chassis
* The following data is transmitted. Output DATA(bit) 7 6 5 4 3 2 1 0 Slave address 1 1 0 0 0 0 1 0 Prog. divider 0 N14 N13 N12 N11 N10 N9 N8 Prog. divider N7 N6 N5 N4 N3 N2 N1 N0 Charge-pump 1 CP 0 0 1 RSA RSB 0 Band 0 0 0 0 B4 B3 B2 B1 - Prog. Divider control-> N14-N0 - CP=1 (High current) - Dividing ratio : 640 (50KHz) Charge pump
1 CP 0 0 1 RSA RSB 0 11001 0 0 0 -BAND control -> P6-P4.
* Matsushita Tuner BAND CHANNEL
DATA
※CHANNEL No.